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| REJ09B0452-0100 16 H8S/2117R Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2117R R4F2117R All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Apr. 28, 2008 Rev. 1.00 Apr. 28, 2008 Page ii of xxvi Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Apr. 28, 2008 Page iii of xxvi General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Apr. 28, 2008 Page iv of xxvi How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8S/2117R Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8S/2117R Group Hardware Manual Software Manual H8S/2600 Series REJ09B0139 H8S/2000 Series Software Manual The latest versions are available from our web site. Application Note Renesas Technical Update Rev. 1.00 Apr. 28, 2008 Page v of xxvi 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Apr. 28, 2008 Page vi of xxvi 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Table of Bits] (1) Bit 15 14 13 to 11 10 9 (2) Bit Name - - ASID2 to ASID0 - - - (3) (4) Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. (5) Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Apr. 28, 2008 Page vii of xxvi 4. Description of Abbreviations The abbreviations used in this manual are listed below. * Abbreviations specific to this product Description Bus controller Clock pulse generator Interrupt controller Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer Abbreviation BSC CPG INT SCI TMR TPU WDT * Abbreviations other than those listed above Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Description Asynchronous communication interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Apr. 28, 2008 Page viii of xxvi Contents Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Functions.............................................................................................. 2 List of Products ...................................................................................................................... 7 Block Diagram ....................................................................................................................... 8 Pin Descriptions ..................................................................................................................... 9 1.4.1 Pin Assignments ....................................................................................................... 9 1.4.2 Pin Assignment in Each Operating Mode............................................................... 12 1.4.3 Pin Functions .......................................................................................................... 19 1.2 1.3 1.4 Section 2 CPU......................................................................................................29 2.1 Features................................................................................................................................ 29 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 30 2.1.2 Differences from H8/300 CPU ............................................................................... 31 2.1.3 Differences from H8/300H CPU............................................................................. 31 CPU Operating Modes......................................................................................................... 32 2.2.1 Normal Mode.......................................................................................................... 32 2.2.2 Advanced Mode...................................................................................................... 34 Address Space...................................................................................................................... 36 Registers............................................................................................................................... 37 2.4.1 General Registers.................................................................................................... 38 2.4.2 Program Counter (PC) ............................................................................................ 39 2.4.3 Extended Control Register (EXR) .......................................................................... 39 2.4.4 Condition-Code Register (CCR)............................................................................. 40 2.4.5 Multiply-Accumulate Register (MAC)................................................................... 41 2.4.6 Initial Values of CPU Registers .............................................................................. 41 Data Formats........................................................................................................................ 42 2.5.1 General Register Data Formats ............................................................................... 42 2.5.2 Memory Data Formats ............................................................................................ 44 Instruction Set ...................................................................................................................... 45 2.6.1 Table of Instructions Classified by Function .......................................................... 46 2.6.2 Basic Instruction Formats ....................................................................................... 56 Addressing Modes and Effective Address Calculation........................................................ 57 2.7.1 Register DirectRn ............................................................................................... 57 2.7.2 Register Indirect@ERn ....................................................................................... 57 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 1.00 Apr. 28, 2008 Page ix of xxvi 2.8 2.9 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 58 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..... 58 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 58 2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 59 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ...................................... 59 2.7.8 Memory Indirect@@aa:8 ................................................................................... 60 2.7.9 Effective Address Calculation ................................................................................ 61 Processing States.................................................................................................................. 63 Usage Note........................................................................................................................... 65 2.9.1 Notes on Using the Bit Operation Instruction......................................................... 65 Section 3 MCU Operating Modes ....................................................................... 67 3.1 3.2 Operating Mode Selection ................................................................................................... 67 Register Descriptions........................................................................................................... 68 3.2.1 Mode Control Register (MDCR) ............................................................................ 68 3.2.2 System Control Register (SYSCR)......................................................................... 69 3.2.3 Serial Timer Control Register (STCR) ................................................................... 71 3.2.4 System Control Register 3 (SYSCR3) .................................................................... 73 Operating Mode Descriptions .............................................................................................. 73 3.3.1 Mode 2.................................................................................................................... 73 Address Map ........................................................................................................................ 74 3.3 3.4 Section 4 Exception Handling ............................................................................. 75 4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 75 Exception Sources and Exception Vector Table .................................................................. 76 Reset .................................................................................................................................... 79 4.3.1 Reset Exception Handling ...................................................................................... 79 4.3.2 Interrupts Immediately after Reset.......................................................................... 80 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 80 Interrupt Exception Handling .............................................................................................. 81 Trap Instruction Exception Handling................................................................................... 81 Exception Handling by Illegal Instruction ........................................................................... 82 Stack Status after Exception Handling................................................................................. 83 Usage Note........................................................................................................................... 84 4.4 4.5 4.6 4.7 4.8 Rev. 1.00 Apr. 28, 2008 Page x of xxvi Section 5 Interrupt Controller ..............................................................................85 5.1 5.2 5.3 Features................................................................................................................................ 85 Input/Output Pins ................................................................................................................. 87 Register Descriptions ........................................................................................................... 88 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .............................................. 89 5.3.2 Address Break Control Register (ABRKCR) ......................................................... 91 5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 92 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 93 5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 96 5.3.6 IRQ Status Registers (ISR16, ISR) ......................................................................... 97 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR) ........................................... 99 5.3.8 IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR)................................................................. 103 5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER).............................. 104 Interrupt Sources................................................................................................................ 105 5.4.1 External Interrupt Sources .................................................................................... 105 5.4.2 Internal Interrupt Sources ..................................................................................... 108 Interrupt Exception Handling Vector Tables ..................................................................... 108 Interrupt Control Modes and Interrupt Operation .............................................................. 117 5.6.1 Interrupt Control Mode 0 ...................................................................................... 119 5.6.2 Interrupt Control Mode 1 ...................................................................................... 121 5.6.3 Interrupt Exception Handling Sequence ............................................................... 124 5.6.4 Interrupt Response Times ..................................................................................... 125 Address Breaks .................................................................................................................. 126 5.7.1 Features................................................................................................................. 126 5.7.2 Block Diagram...................................................................................................... 126 5.7.3 Operation .............................................................................................................. 127 5.7.4 Usage Notes .......................................................................................................... 127 Usage Notes ....................................................................................................................... 129 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 129 5.8.2 Instructions for Disabling Interrupts ..................................................................... 130 5.8.3 Interrupts during Execution of EEPMOV Instruction........................................... 130 5.8.4 Vector Address Switching .................................................................................... 130 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode.................... 131 5.8.6 Noise Canceller Switching.................................................................................... 131 5.8.7 IRQ Status Register (ISR)..................................................................................... 131 5.4 5.5 5.6 5.7 5.8 Rev. 1.00 Apr. 28, 2008 Page xi of xxvi Section 6 Bus Controller (BSC) ........................................................................ 133 6.1 Register Descriptions......................................................................................................... 133 6.1.1 Bus Control Register (BCR) ................................................................................. 133 6.1.2 Wait State Control Register (WSCR) ................................................................... 134 Section 7 I/O Ports............................................................................................. 135 7.1 Register Descriptions......................................................................................................... 143 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) ............... 144 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9).......................................................... 145 7.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J)............................................. 145 7.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 9, B to D, F, H, and J) Pull-Up MOS Control Register (KMPCR) (Port 6).............................................. 146 7.1.5 Output Data Register (PnODR) (n = A to D and F to J) ....................................... 149 7.1.6 Noise Canceler Enable Register (PnNCE) (n = 6, C, and G)................................ 149 7.1.7 Noise Canceler Decision Control Register (PnNCMC) (n = 6, C, and G)............ 150 7.1.8 Noise Cancel Cycle Setting Register (PnNCCS) (n = 6, C, and G) ...................... 150 7.1.9 Port Nch-OD Control Register (PnNOCR) (n = C, D, and F to J)........................ 152 7.1.10 Pin Functions ........................................................................................................ 153 Output Buffer Control........................................................................................................ 154 7.2.1 Port 1..................................................................................................................... 154 7.2.2 Port 2..................................................................................................................... 154 7.2.3 Port 3..................................................................................................................... 155 7.2.4 Port 4..................................................................................................................... 155 7.2.5 Port 5..................................................................................................................... 159 7.2.6 Port 6..................................................................................................................... 161 7.2.7 Port 7..................................................................................................................... 162 7.2.8 Port 8..................................................................................................................... 163 7.2.9 Port 9..................................................................................................................... 166 7.2.10 Port A.................................................................................................................... 168 7.2.11 Port B.................................................................................................................... 169 7.2.12 Port C.................................................................................................................... 173 7.2.13 Port D.................................................................................................................... 177 7.2.14 Port E .................................................................................................................... 177 7.2.15 Port F .................................................................................................................... 178 7.2.16 Port G.................................................................................................................... 181 7.2.17 Port H.................................................................................................................... 185 7.2.18 Port I ..................................................................................................................... 187 7.2.19 Port J ..................................................................................................................... 187 Change of Peripheral Function Pins................................................................................... 194 7.3.1 Port Control Register 0 (PTCNT0) ....................................................................... 194 7.2 7.3 Rev. 1.00 Apr. 28, 2008 Page xii of xxvi 7.3.2 7.3.3 Port Control Register 1 (PTCNT1) ....................................................................... 195 Port Control Register 2 (PTCNT2) ....................................................................... 196 Section 8 8-Bit PWM Timer (PWMU)..............................................................197 8.1 8.2 8.3 Features.............................................................................................................................. 197 Input/Output Pins ............................................................................................................... 199 Register Descriptions ......................................................................................................... 200 8.3.1 PWM Control Register A (PWMCONA) ............................................................. 202 8.3.2 PWM Control Register B (PWMCONB).............................................................. 202 8.3.3 PWM Control Register C (PWMCONC).............................................................. 205 8.3.4 PWM Control Register D (PWMCOND) ............................................................. 206 8.3.5 PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5) ............................. 207 8.3.6 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5) ...................... 209 Operation ........................................................................................................................... 210 8.4.1 Single-Pulse Mode (8 Bits, 16 Bits)...................................................................... 210 8.4.2 Pulse Division Mode............................................................................................. 214 Usage Note......................................................................................................................... 217 8.5.1 Setting Module Stop Mode ................................................................................... 217 8.5.2 Note on Using 16-Bit Single-Pulse PWM Timer.................................................. 217 8.4 8.5 Section 9 14-Bit PWM Timer (PWMX)............................................................219 9.1 9.2 9.3 Features.............................................................................................................................. 219 Input/Output Pins ............................................................................................................... 220 Register Descriptions ......................................................................................................... 220 9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 221 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).......................... 222 9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 224 9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 225 Bus Master Interface .......................................................................................................... 226 Operation ........................................................................................................................... 229 Usage Notes ....................................................................................................................... 236 9.6.1 Module Stop Mode Setting ................................................................................... 236 9.4 9.5 9.6 Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................237 10.1 Features.............................................................................................................................. 237 10.2 Input/Output Pins ............................................................................................................... 241 10.3 Register Descriptions ......................................................................................................... 242 10.3.1 Timer Control Register (TCR).............................................................................. 243 10.3.2 Timer Mode Register (TMDR) ............................................................................. 247 10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 249 Rev. 1.00 Apr. 28, 2008 Page xiii of xxvi 10.4 10.5 10.6 10.7 10.8 10.3.4 Timer Interrupt Enable Register (TIER)............................................................... 258 10.3.5 Timer Status Register (TSR)................................................................................. 260 10.3.6 Timer Counter (TCNT)......................................................................................... 263 10.3.7 Timer General Register (TGR) ............................................................................. 263 10.3.8 Timer Start Register (TSTR) ................................................................................ 263 10.3.9 Timer Synchro Register (TSYR) .......................................................................... 264 Interface to Bus Master...................................................................................................... 265 10.4.1 16-Bit Registers .................................................................................................... 265 10.4.2 8-Bit Registers ...................................................................................................... 265 Operation ........................................................................................................................... 267 10.5.1 Basic Functions..................................................................................................... 267 10.5.2 Synchronous Operation......................................................................................... 273 10.5.3 Buffer Operation................................................................................................... 275 10.5.4 PWM Modes......................................................................................................... 279 10.5.5 Phase Counting Mode........................................................................................... 283 Interrupts............................................................................................................................ 288 10.6.1 Interrupt Source and Priority ................................................................................ 288 10.6.2 A/D Converter Activation..................................................................................... 289 Operation Timing............................................................................................................... 290 10.7.1 Input/Output Timing............................................................................................. 290 10.7.2 Interrupt Signal Timing ........................................................................................ 294 Usage Notes ....................................................................................................................... 297 10.8.1 Input Clock Restrictions ....................................................................................... 297 10.8.2 Caution on Period Setting ..................................................................................... 297 10.8.3 Conflict between TCNT Write and Clear Operations........................................... 298 10.8.4 Conflict between TCNT Write and Increment Operations ................................... 298 10.8.5 Conflict between TGR Write and Compare Match............................................... 299 10.8.6 Conflict between Buffer Register Write and Compare Match.............................. 299 10.8.7 Conflict between TGR Read and Input Capture ................................................... 300 10.8.8 Conflict between TGR Write and Input Capture .................................................. 301 10.8.9 Conflict between Buffer Register Write and Input Capture.................................. 301 10.8.10 Conflict between Overflow/Underflow and Counter Clearing ............................. 302 10.8.11 Conflict between TCNT Write and Overflow/Underflow .................................... 303 10.8.12 Multiplexing of I/O Pins ....................................................................................... 303 10.8.13 Module Stop Mode Setting ................................................................................... 303 Rev. 1.00 Apr. 28, 2008 Page xiv of xxvi Section 11 16-Bit Cycle Measurement Timer (TCM) .......................................305 11.1 Features.............................................................................................................................. 305 11.2 Input/Output Pins ............................................................................................................... 307 11.3 Register Descriptions ......................................................................................................... 307 11.3.1 TCM Timer Counter (TCMCNT) ......................................................................... 309 11.3.2 TCM Cycle Upper Limit Register (TCMMLCM) ................................................ 309 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM).............................................. 310 11.3.4 TCM Input Capture Register (TCMICR).............................................................. 310 11.3.5 TCM Input Capture Buffer Register (TCMICRF) ................................................ 310 11.3.6 TCM Status Register (TCMCSR) ......................................................................... 311 11.3.7 TCM Control Register (TCMCR)......................................................................... 313 11.3.8 TCM Interrupt Enable Register (TCMIER).......................................................... 315 11.4 Operation ........................................................................................................................... 317 11.4.1 Timer Mode .......................................................................................................... 317 11.4.2 Cycle Measurement Mode .................................................................................... 319 11.5 Interrupt Sources................................................................................................................ 324 11.6 Usage Notes ....................................................................................................................... 325 11.6.1 Conflict between TCMCNT Write and Count-Up Operation ............................... 325 11.6.2 Conflict between TCMMLCM Write and Compare Match.................................. 325 11.6.3 Conflict between TCMICR Read and Input Capture ............................................ 326 11.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to TCMMLCM or TCMMINCM ............................................................ 326 11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of TCMMDS Bit in TCMCR ................................................................. 327 11.6.6 Settings of TCMCKI and TCMMCI..................................................................... 327 11.6.7 Setting for Module Stop Mode ............................................................................. 327 Section 12 16-Bit Duty Period Measurement Timer (TDP) ..............................329 12.1 Features.............................................................................................................................. 329 12.2 Input/Output Pins ............................................................................................................... 331 12.3 Register Descriptions ......................................................................................................... 331 12.3.1 TDP Timer Counter (TDPCNT) ........................................................................... 333 12.3.2 TDP Pulse Width Upper Limit Register (TDPWDMX) ....................................... 333 12.3.3 TDP Pulse Width Lower Limit Register (TDPWDMN)....................................... 334 12.3.4 TDP Cycle Upper Limit Register (TDPPDMX)................................................... 334 12.3.5 TDP Cycle Lower Limit Register (TDPPDMN) .................................................. 334 12.3.6 TDP Input Capture Register (TDPICR)................................................................ 335 12.3.7 TDP Input Capture Buffer Register (TDPICRF) .................................................. 335 12.3.8 TDP Status Register (TDPCSR) ........................................................................... 335 Rev. 1.00 Apr. 28, 2008 Page xv of xxvi 12.3.9 TDP Control Register 1 (TDPCR1)...................................................................... 338 12.3.10 TDP Control Register 2 (TDPCR2)...................................................................... 340 12.3.11 TDP Interrupt Enable Register (TDPIER) ............................................................ 341 12.4 Operation ........................................................................................................................... 343 12.4.1 Timer Mode .......................................................................................................... 343 12.4.2 Cycle Measurement Mode .................................................................................... 345 12.5 Interrupt Sources................................................................................................................ 350 12.6 Usage Notes ....................................................................................................................... 351 12.6.1 Conflict between TDPCNT Write and Count-Up Operation ................................ 351 12.6.2 Conflict between TDPPDMX Write and Compare Match.................................... 351 12.6.3 Conflict between Input Capture and TDPICR Read ............................................. 352 12.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to the Upper Limit or Lower Limit Register ........................................... 352 12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit Clearing.......................................................................................... 353 12.6.6 Settings for TDPCKI and TDPMCI...................................................................... 353 12.6.7 Setting for Module Stop Mode ............................................................................. 353 Section 13 8-Bit Timer (TMR).......................................................................... 355 13.1 Features.............................................................................................................................. 355 13.2 Input/Output Pins............................................................................................................... 358 13.3 Register Descriptions......................................................................................................... 359 13.3.1 Timer Counter (TCNT)......................................................................................... 360 13.3.2 Time Constant Register A (TCORA) ................................................................... 361 13.3.3 Time Constant Register B (TCORB).................................................................... 361 13.3.4 Timer Control Register (TCR).............................................................................. 362 13.3.5 Timer Control/Status Register (TCSR)................................................................. 367 13.3.6 Time Constant Register C (TCORC).................................................................... 372 13.3.7 Input Capture Registers R and F (TICRR and TICRF)......................................... 372 13.3.8 Timer Connection Register I (TCONRI) .............................................................. 373 13.3.9 Timer Connection Register S (TCONRS) ............................................................ 373 13.3.10 Timer XY Control Register (TCRXY) ................................................................. 374 13.4 Operation ........................................................................................................................... 375 13.4.1 Pulse Output ......................................................................................................... 375 13.5 Operation Timing............................................................................................................... 376 13.5.1 TCNT Count Timing ............................................................................................ 376 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 377 13.5.3 Timing of Timer Output at Compare-Match......................................................... 377 13.5.4 Timing of Counter Clear at Compare-Match........................................................ 378 13.5.5 TCNT External Reset Timing............................................................................... 378 Rev. 1.00 Apr. 28, 2008 Page xvi of xxvi 13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 379 13.6 TMR_0 and TMR_1 Cascaded Connection ....................................................................... 380 13.6.1 16-Bit Count Mode ............................................................................................... 380 13.6.2 Compare-Match Count Mode ............................................................................... 380 13.7 TMR_Y and TMR_X Cascaded Connection ..................................................................... 381 13.7.1 16-Bit Count Mode ............................................................................................... 381 13.7.2 Compare-Match Count Mode ............................................................................... 381 13.7.3 Input Capture Operation ....................................................................................... 382 13.8 Interrupt Sources................................................................................................................ 384 13.9 Usage Notes ....................................................................................................................... 385 13.9.1 Conflict between TCNT Write and Counter Clear................................................ 385 13.9.2 Conflict between TCNT Write and Count-Up ...................................................... 385 13.9.3 Conflict between TCOR Write and Compare-Match............................................ 386 13.9.4 Conflict between Compare-Matches A and B ...................................................... 386 13.9.5 Switching of Internal Clocks and TCNT Operation.............................................. 387 13.9.6 Mode Setting with Cascaded Connection ............................................................. 389 13.9.7 Module Stop Mode Setting ................................................................................... 389 Section 14 Watchdog Timer (WDT)..................................................................391 14.1 Features.............................................................................................................................. 391 14.2 Input/Output Pins ............................................................................................................... 393 14.3 Register Descriptions ......................................................................................................... 393 14.3.1 Timer Counter (TCNT)......................................................................................... 394 14.3.2 Timer Control/Status Register (TCSR)................................................................. 394 14.4 Operation ........................................................................................................................... 398 14.4.1 Watchdog Timer Mode ......................................................................................... 398 14.4.2 Interval Timer Mode............................................................................................. 399 14.5 Interrupt Sources................................................................................................................ 400 14.6 Usage Notes ....................................................................................................................... 400 14.6.1 Notes on Register Access...................................................................................... 400 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 401 14.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 402 14.6.4 Changing Value of PSS Bit................................................................................... 402 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 402 Rev. 1.00 Apr. 28, 2008 Page xvii of xxvi Section 15 Serial Communication Interface (SCI)............................................ 403 15.1 Features.............................................................................................................................. 403 15.2 Input/Output Pins............................................................................................................... 405 15.3 Register Descriptions......................................................................................................... 406 15.3.1 Receive Shift Register (RSR) ............................................................................... 407 15.3.2 Receive Data Register (RDR)............................................................................... 407 15.3.3 Transmit Data Register (TDR).............................................................................. 407 15.3.4 Transmit Shift Register (TSR) .............................................................................. 407 15.3.5 Serial Mode Register (SMR) ................................................................................ 408 15.3.6 Serial Control Register (SCR) .............................................................................. 411 15.3.7 Serial Status Register (SSR) ................................................................................. 414 15.3.8 Smart Card Mode Register (SCMR)..................................................................... 418 15.3.9 Bit Rate Register (BRR) ....................................................................................... 419 15.4 Operation in Asynchronous Mode ..................................................................................... 424 15.4.1 Data Transfer Format............................................................................................ 425 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 426 15.4.3 Clock..................................................................................................................... 427 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 428 15.4.5 Serial Data Transmission (Asynchronous Mode) ................................................. 429 15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 431 15.5 Multiprocessor Communication Function.......................................................................... 435 15.5.1 Multiprocessor Serial Data Transmission ............................................................. 437 15.5.2 Multiprocessor Serial Data Reception .................................................................. 438 15.6 Operation in Clocked Synchronous Mode ......................................................................... 441 15.6.1 Clock..................................................................................................................... 441 15.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 442 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 443 15.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 445 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 447 15.7 Smart Card Interface Description ...................................................................................... 449 15.7.1 Sample Connection............................................................................................... 449 15.7.2 Data Format (Except in Block Transfer Mode) .................................................... 450 15.7.3 Block Transfer Mode ............................................................................................ 451 15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 452 15.7.5 Initialization.......................................................................................................... 453 15.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 453 15.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 456 Rev. 1.00 Apr. 28, 2008 Page xviii of xxvi 15.7.8 Clock Output Control............................................................................................ 458 15.8 Interrupt Sources................................................................................................................ 460 15.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 460 15.8.2 Interrupts in Smart Card Interface Mode .............................................................. 461 15.9 Usage Notes ....................................................................................................................... 462 15.9.1 Module Stop Mode Setting ................................................................................... 462 15.9.2 Break Detection and Processing ........................................................................... 462 15.9.3 Mark State and Break Sending.............................................................................. 462 15.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 462 15.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 462 15.9.6 SCI Operations during Mode Transitions ............................................................. 463 15.9.7 Notes on Switching from SCK Pins to Port Pins .................................................. 466 15.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception .......................................................... 467 Section 16 CIR Interface....................................................................................469 16.1 Features.............................................................................................................................. 469 16.2 Input Pins ........................................................................................................................... 471 16.3 Register Description........................................................................................................... 471 16.3.1 Receive Control Register 1 (CCR1)...................................................................... 472 16.3.2 Receive Control Register 2 (CCR2)...................................................................... 473 16.3.3 Receive Status Register (CSTR) ........................................................................... 474 16.3.4 Interrupt Enable Register (CEIR) ......................................................................... 476 16.3.5 Bit Rate Register (BRR) ....................................................................................... 477 16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17) .................................. 478 16.3.7 Header Minimum/Maximum High-Level Period Register (HHMIN and HHMAX) ....................................................................................... 478 16.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX)............................................................................................... 480 16.3.9 Data Level 1 Minimum/Maximum Period Register (DT1MIN/DT1MAX) ....................................................................................... 480 16.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) ........................................................................................... 481 16.3.11 Repeat Header Minimum/Maximum Low-Level Period Register (RMIN/RMAX) .................................................................................................... 481 16.4 Operation ........................................................................................................................... 482 16.4.1 Determination of Signal Type by Low/High-Level Period................................... 484 16.4.2 Operation of FIFO Register .................................................................................. 486 16.4.3 Operation in Watch Mode..................................................................................... 487 Rev. 1.00 Apr. 28, 2008 Page xix of xxvi 16.5 16.6 16.7 16.8 16.4.4 Switching between System Clock and Sub Clock ................................................ 487 Noise Canceler Circuit....................................................................................................... 488 Reset Conditions ................................................................................................................ 490 Interrupt Sources................................................................................................................ 490 Usage Note......................................................................................................................... 491 Section 17 Serial Communication Interface with FIFO (SCIF)........................ 493 17.1 Features.............................................................................................................................. 493 17.2 Input/Output Pins............................................................................................................... 495 17.3 Register Descriptions......................................................................................................... 496 17.3.1 Receive Shift Register (FRSR) ............................................................................. 497 17.3.2 Receive Buffer Register (FRBR) .......................................................................... 497 17.3.3 Transmitter Shift Register (FTSR)........................................................................ 498 17.3.4 Transmitter Holding Register (FTHR).................................................................. 498 17.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 498 17.3.6 Interrupt Enable Register (FIER).......................................................................... 499 17.3.7 Interrupt Identification Register (FIIR) ................................................................ 500 17.3.8 FIFO Control Register (FFCR)............................................................................. 502 17.3.9 Line Control Register (FLCR) .............................................................................. 503 17.3.10 Modem Control Register (FMCR)........................................................................ 504 17.3.11 Line Status Register (FLSR)................................................................................. 506 17.3.12 Modem Status Register (FMSR)........................................................................... 510 17.3.13 Scratch Pad Register (FSCR)................................................................................ 511 17.3.14 SCIF Control Register (SCIFCR) ......................................................................... 512 17.4 Operation ........................................................................................................................... 514 17.4.1 Baud Rate ............................................................................................................. 514 17.4.2 Operation in Asynchronous Communication........................................................ 515 17.4.3 Initialization of the SCIF ...................................................................................... 516 17.4.4 Data Transmission/Reception with Flow Control................................................. 519 17.4.5 Data Transmission/Reception Through the LPC Interface ................................... 525 17.5 Interrupt Sources................................................................................................................ 528 17.6 Usage Note......................................................................................................................... 528 17.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 528 Section 18 I2C Bus Interface (IIC)..................................................................... 529 18.1 Features.............................................................................................................................. 529 18.2 Input/Output Pins............................................................................................................... 533 18.3 Register Descriptions......................................................................................................... 534 18.3.1 I2C Bus Data Register (ICDR) .............................................................................. 536 18.3.2 Slave Address Register (SAR).............................................................................. 537 Rev. 1.00 Apr. 28, 2008 Page xx of xxvi 18.3.3 Second Slave Address Register (SARX) .............................................................. 538 18.3.4 I2C Bus Mode Register (ICMR)............................................................................ 540 18.3.5 I2C Bus Control Register (ICCR).......................................................................... 543 18.3.6 I2C Bus Status Register (ICSR)............................................................................. 551 18.3.7 I2C Bus Control Initialization Register (ICRES)................................................... 555 18.3.8 I2C Bus Extended Control Register (ICXR).......................................................... 556 18.4 Operation ........................................................................................................................... 560 18.4.1 I2C Bus Data Format ............................................................................................. 560 18.4.2 Initialization .......................................................................................................... 562 18.4.3 Master Transmit Operation ................................................................................... 562 18.4.4 Master Receive Operation..................................................................................... 567 18.4.5 Slave Receive Operation....................................................................................... 570 18.4.6 Slave Transmit Operation ..................................................................................... 574 18.4.7 IRIC Setting Timing and SCL Control ................................................................. 577 18.4.8 Noise Canceler...................................................................................................... 579 18.4.9 Initialization of Internal State ............................................................................... 579 18.5 Interrupt Sources................................................................................................................ 581 18.6 Usage Notes ....................................................................................................................... 582 18.6.1 Module Stop Mode Setting ................................................................................... 585 Section 19 Keyboard Buffer Control Unit (PS2)...............................................587 19.1 Features.............................................................................................................................. 587 19.2 Input/Output Pins ............................................................................................................... 589 19.3 Register Descriptions ......................................................................................................... 590 19.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 591 19.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 593 19.3.3 Keyboard Control Register H (KBCRH) .............................................................. 594 19.3.4 Keyboard Control Register L (KBCRL) ............................................................... 596 19.3.5 Keyboard Data Buffer Register (KBBR) .............................................................. 598 19.3.6 Keyboard Buffer Transmit Data Register (KBTR) ............................................... 598 19.4 Operation ........................................................................................................................... 599 19.4.1 Receive Operation................................................................................................. 599 19.4.2 Transmit Operation ............................................................................................... 601 19.4.3 Receive Abort ....................................................................................................... 602 19.4.4 KCLKI and KDI Read Timing.............................................................................. 605 19.4.5 KCLKO and KDO Write Timing.......................................................................... 605 19.4.6 KBF Setting Timing and KCLK Control.............................................................. 606 19.4.7 Receive Timing..................................................................................................... 607 19.4.8 Operation during Data Reception ......................................................................... 607 19.4.9 KCLK Fall Interrupt Operation............................................................................. 608 Rev. 1.00 Apr. 28, 2008 Page xxi of xxvi 19.4.10 First KCLK Falling Interrupt................................................................................ 609 19.5 Usage Notes ....................................................................................................................... 613 19.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 613 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 614 19.5.3 Module Stop Mode Setting ................................................................................... 614 19.5.4 Medium-Speed Mode ........................................................................................... 614 19.5.5 Transmit Completion Flag (KBTE) ...................................................................... 614 Section 20 LPC Interface (LPC)........................................................................ 615 20.1 Features.............................................................................................................................. 615 20.2 Input/Output Pins............................................................................................................... 617 20.3 Register Descriptions......................................................................................................... 618 20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 620 20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 626 20.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 629 20.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 630 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 631 20.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 632 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 634 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 636 20.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 637 20.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 637 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 638 20.3.12 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 638 20.3.13 SERIRQ Control Register 0 (SIRQCR0).............................................................. 645 20.3.14 SERIRQ Control Register 1 (SIRQCR1).............................................................. 649 20.3.15 SERIRQ Control Register 2 (SIRQCR2).............................................................. 653 20.3.16 SERIRQ Control Register 3 (SIRQCR3).............................................................. 656 20.3.17 SERIRQ Control Register 4 (SIRQCR4).............................................................. 657 20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 658 20.3.19 Host Interface Select Register (HISEL)................................................................ 659 20.4 Operation ........................................................................................................................... 660 20.4.1 LPC interface Activation ...................................................................................... 660 20.4.2 LPC I/O Cycles..................................................................................................... 661 20.4.3 Gate A20............................................................................................................... 664 20.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 667 20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 671 20.4.6 LPC Interface Clock Start Request ....................................................................... 673 20.4.7 SCIF Control from LPC Interface......................................................................... 673 20.5 Interrupt Sources................................................................................................................ 674 Rev. 1.00 Apr. 28, 2008 Page xxii of xxvi 20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ..................................................... 674 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 675 20.6 Usage Note......................................................................................................................... 678 20.6.1 Data Conflict......................................................................................................... 678 Section 21 FSI Interface ....................................................................................681 21.1 Features.............................................................................................................................. 681 21.2 Input/Output Pins ............................................................................................................... 683 21.3 Register Description........................................................................................................... 684 21.3.1 FSI Control Register 1 (FSICR1).......................................................................... 686 21.3.2 FSI Control Register 2 (FSICR2).......................................................................... 688 21.3.3 FSI Byte Count Register (FSIBNR)...................................................................... 689 21.3.4 FSI Instruction Register (FSIINS) ........................................................................ 690 21.3.5 FSI Instruction Register (FSIRDINS)................................................................... 691 21.3.6 FSI Program Instruction Register (FSIPPINS) ..................................................... 691 21.3.7 FSI Status Register (FSISTR)............................................................................... 691 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)............................... 693 21.3.9 FSI Receive Data Register (FSIRDR) .................................................................. 693 21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL) ............................................................................. 694 21.3.11 FSI Flash Memory Size Register (FSISR) ............................................................ 694 21.3.12 FSI Command Host Base Address Registers H and L (CMDHBARH and CMDHBARL) ...................................................................... 695 21.3.13 FSI Command Register (FSICMDR).................................................................... 696 21.3.14 FSI LPC Command Status Register 1 (FSILSTR1).............................................. 696 21.3.15 FSI LPC Command Status Register 2 (FSILSTR2).............................................. 698 21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) ........................... 699 21.3.17 FSI LPC Control Register (SLCR) ....................................................................... 699 21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL) ............. 700 21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL).............................. 701 21.4 Operation ........................................................................................................................... 703 21.4.1 LPC/FW Memory Cycles ..................................................................................... 703 21.4.2 SPI Flash Memory Transfer.................................................................................. 705 21.4.3 Flash Memory Instructions ................................................................................... 706 21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI)................................ 707 21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer).............................................. 714 21.4.6 SPI Flash Memory Write Operation Mode ........................................................... 722 21.5 Reset Conditions ................................................................................................................ 723 Rev. 1.00 Apr. 28, 2008 Page xxiii of xxvi 21.6 Interrupt Sources................................................................................................................ 725 21.7 Usage Note......................................................................................................................... 725 21.7.1 Longword Transfer in FW Memory Write Cycles................................................ 725 Section 22 A/D Converter ................................................................................. 727 22.1 Features.............................................................................................................................. 727 22.2 Input/Output Pins............................................................................................................... 729 22.3 Register Descriptions......................................................................................................... 730 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .............................................. 731 22.3.2 A/D Control/Status Register (ADCSR) ................................................................ 732 22.3.3 A/D Control Register (ADCR) ............................................................................. 734 22.4 Operation ........................................................................................................................... 735 22.4.1 Single Mode.......................................................................................................... 735 22.4.2 Scan Mode ............................................................................................................ 736 22.4.3 Input Sampling and A/D Conversion Time .......................................................... 737 22.5 Interrupt Source ................................................................................................................. 739 22.6 A/D Conversion Accuracy Definitions .............................................................................. 739 22.7 Usage Notes ....................................................................................................................... 741 22.7.1 Module Stop Mode Setting ................................................................................... 741 22.7.2 Permissible Signal Source Impedance .................................................................. 741 22.7.3 Influences on Absolute Accuracy ......................................................................... 742 22.7.4 Setting Range of Analog Power Supply and Other Pins....................................... 742 22.7.5 Notes on Board Design ......................................................................................... 742 22.7.6 Notes on Noise Countermeasures ......................................................................... 743 22.7.7 Module Stop Mode Setting ................................................................................... 744 22.7.8 Note on activation of the A/D converter by an external trigger............................ 745 Section 23 RAM ................................................................................................ 747 Section 24 Flash Memory.................................................................................. 749 24.1 24.2 24.3 24.4 24.5 24.6 24.7 Features.............................................................................................................................. 749 Mode Transition Diagram.................................................................................................. 750 Flash Memory MAT Configuration................................................................................... 752 Block Structure .................................................................................................................. 753 Programming/Erasing Interface ......................................................................................... 754 Input/Output Pins............................................................................................................... 756 Register Descriptions......................................................................................................... 757 24.7.1 Programming/Erasing Interface Registers ............................................................ 759 24.7.2 Programming/Erasing Interface Parameters ......................................................... 765 24.8 On-Board Programming Mode .......................................................................................... 776 Rev. 1.00 Apr. 28, 2008 Page xxiv of xxvi 24.9 24.10 24.11 24.12 24.13 24.8.1 Boot Mode ............................................................................................................ 776 24.8.2 User Program Mode.............................................................................................. 780 24.8.3 User Boot Mode.................................................................................................... 789 24.8.4 Storable Areas for On-Chip Program and Program Data...................................... 793 Protection ........................................................................................................................... 798 24.9.1 Hardware Protection ............................................................................................. 798 24.9.2 Software Protection............................................................................................... 799 24.9.3 Error Protection..................................................................................................... 799 Switching between User MAT and User Boot MAT ......................................................... 801 Programmer Mode ............................................................................................................. 802 Standard Serial Communication Interface Specifications for Boot Mode ......................... 802 Usage Notes ....................................................................................................................... 831 Section 25 Clock Pulse Generator .....................................................................833 25.1 Oscillator............................................................................................................................ 834 25.1.1 Connecting Crystal Resonator .............................................................................. 834 25.1.2 External Clock Input Method................................................................................ 835 25.2 Duty Correction Circuit ..................................................................................................... 838 25.3 Subclock Input Circuit ....................................................................................................... 838 25.4 Subclock Waveform Forming Circuit................................................................................ 839 25.5 Clock Select Circuit ........................................................................................................... 839 25.6 Usage Notes ....................................................................................................................... 840 25.6.1 Notes on Resonator............................................................................................... 840 25.6.2 Notes on Board Design ......................................................................................... 840 Section 26 Power-Down Modes ........................................................................841 26.1 Register Descriptions ......................................................................................................... 841 26.1.1 Standby Control Register (SBYCR) ..................................................................... 842 26.1.2 Low-Power Control Register (LPWRCR) ............................................................ 844 26.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) ............................................ 845 26.2 Mode Transitions and LSI States ....................................................................................... 848 26.3 Medium-Speed Mode......................................................................................................... 850 26.4 Sleep Mode ........................................................................................................................ 851 26.5 Software Standby Mode..................................................................................................... 851 26.6 Watch Mode....................................................................................................................... 853 26.7 Module Stop Mode ............................................................................................................ 854 26.8 Usage Notes ....................................................................................................................... 854 26.8.1 I/O Port Status....................................................................................................... 854 26.8.2 Current Consumption when Waiting for Oscillation Stabilization ....................... 854 Rev. 1.00 Apr. 28, 2008 Page xxv of xxvi Section 27 List of Registers............................................................................... 855 27.1 27.2 27.3 27.4 27.5 Register Addresses (Address Order).................................................................................. 856 Register Bits....................................................................................................................... 878 Register States in Each Operating Mode ........................................................................... 896 Register Selection Condition ............................................................................................. 912 Register Addresses (Classification by Type of Module) ................................................... 934 Section 28 Electrical Characteristics ................................................................. 957 28.1 Absolute Maximum Ratings .............................................................................................. 957 28.2 DC Characteristics ............................................................................................................. 958 28.3 AC Characteristics ............................................................................................................. 963 28.3.1 Clock Timing ........................................................................................................ 964 28.3.2 Control Signal Timing .......................................................................................... 966 28.3.3 Timing of On-Chip Peripheral Modules ............................................................... 968 28.4 A/D Conversion Characteristics ........................................................................................ 979 28.5 Flash Memory Characteristics ........................................................................................... 980 28.6 Usage Notes ....................................................................................................................... 981 Appendix A. B. C. D. ......................................................................................................... 983 I/O Port States in Each Pin State........................................................................................ 983 Product Lineup................................................................................................................... 984 Package Dimensions .......................................................................................................... 985 Treatment of Unused Pins.................................................................................................. 988 Index ......................................................................................................... 989 Rev. 1.00 Apr. 28, 2008 Page xxvi of xxvi Section 1 Overview Section 1 Overview 1.1 Features The core of each product in the H8S/2117R Group of CISC (complex instruction set computer) microcomputers is an H8S/2600 CPU, which has an internal 16-bit architecture. The H8S/2600 CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcomputers; H8/300, H8/300H, and H8S. As peripheral functions, each LSI of the group includes a serial communication interface with FIFO, an I2C bus interface, an A/D converter, and various types of timers. Together, the modules realize low-cost system configurations. The power consumption of these modules is kept down dynamically by power-down modes. The on-chip ROM is a flash memory (F-ZTATTM*) with a capacity of 160 Kbytes. Note: * F-ZTATTM is a trademark of Renesas Technology Corp. 1.1.1 Applications Examples of the applications of this LSI include PC peripheral equipment, office automation equipment, and industrial equipment. Rev. 1.00 Apr. 28, 2008 Page 1 of 994 REJ09B0452-0100 Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of this LSI in outline. Table 1.1 Overview of Functions Module/ Function ROM RAM CPU CPU Description * * * ROM lineup: Flash memory version H8S/2117R: 160 Kbytes RAM capacity: 8 Kbytes 16-bit high-speed H8S/2600 CPU (CISC type) Upward-compatibility with H8/300, H8/300H, and H8S CPUs at object level * * * General-register architecture (sixteen 16-bit general registers) Eight addressing modes 4-Gbyte address space Program: 4 Gbytes available Data: 4 Gbytes available * 69 basic instructions (bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, multiply-and-accumulate instructions, and others) Minimum instruction execution time: 50.0 ns (for an ADD instruction while system clock = 20 MHz and VCC = 3.0 to 3.6 V) On-chip multiplier (16 x 16 32 bits) Supports multiply-and-accumulate instructions (16 x 16 + 32 32 bits) Advanced and single-chip modes Classification Memory * * * Operating mode * Rev. 1.00 Apr. 28, 2008 Page 2 of 994 REJ09B0452-0100 Section 1 Overview Classification CPU Module/ Function MCU operating mode Description Mode 2: Single-chip mode (selected by driving the MD2 and MD0 pins low and MD1 pin high) Mode 4: Boot mode (selected by driving the MD2 high and MD1 and MD0 pins low) Mode 6: On-chip emulation mode (selected by driving the MD2 and MD1 pins high and the MD0 pin low) Note: MD0 is not available as a pin and is internally fixed to 0. * Power-down state (transition to the power-down state made by the SLEEP instruction) 41 external interrupt pins (NMI, IRQ15 to IRQ0 (ExIRQ15 to ExIRQ6), KIN15 to KIN0, and WUE15 to WUE8) 66 internal interrupt sources Two interrupt control modes (specified by the system control register) Two levels of interrupt priority orders specifiable (by setting the interrupt control register) Independent vector addresses Two clock generation circuits Clock pulse generator and subclock input circuit System clock () synchronization: 8 to 20 MHz Five power-down modes: Medium-speed mode, sleep mode, watch mode, software standby mode, and module stop mode 10-bit resolution x 16 input channels Sample and hold function included Conversion time: 4 s per channel (with A/D conversion clock ADCLK at 10 MHz operation) Two operating modes: single mode and scan mode Three methods to start A/D conversion: software and two timer (TPU/TMR) triggers Interrupt (source) Interrupt controller * * * * * Clock Clock pulse * generator * (CPG) * A/D converter A/D converter (ADC) * * * * * Rev. 1.00 Apr. 28, 2008 Page 3 of 994 REJ09B0452-0100 Section 1 Overview Classification Timer Module/ Function 8-bit PWM timer (PWMU) Description * * * * 8-bit timers A/B x six channels Selectable from four clock sources Cycle selectable for each channel Supports 8-bit single pulse mode, 16-bit single pulse mode, and 8-bit pulse division mode. 14 bits x two channels Pulse division method Selectable from sixteen operation clocks by combination of eight system clock cycles and two base cycles 16 bits x three channels Selectable from eight counter input clocks for each channel Maximum 8-pulse inputs/outputs The following operations can be set. Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously. Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 7-phase PWM output possible by combination with synchronous operation * * * Supports buffer operation and phase counting mode (twophase encoder input) for some channels Supports input capture function Supports output compare function (waveform output at compare match) 16 bits x four channels Selectable from seven clocks: six internal clocks and one external clock Capable of measuring the periods of input waveforms 16 bits x three channels Selectable from seven clocks: six internal clocks and one external clock Capable of measuring the periods and pulse width of input waveforms 14-bit PWM * timer * (PWMX) * 16-bit timer * pulse unit * (TPU) * * 16-bit cycle * measurem- * ent timer (TCM) * 16-bit duty * period * measurement timer * (TDP) Rev. 1.00 Apr. 28, 2008 Page 4 of 994 REJ09B0452-0100 Section 1 Overview Classification Timer Module/ Function 8-bit timer (TMR) Description * * * 8 bits x four channels (also works as 16 bits x two channels) Selectable from seven clocks: six internal clocks and one external clock Pulse output or PWM output with an arbitrary duty cycle 8 bits x two channels (selectable from eight counter input clocks) Switchable between watchdog timer mode and interval timer mode One channel (asynchronous mode) 16-stage FIFO buffers for transmission and reception Full-duplex communication capability On-chip baud rate generator allows any bit rate to be selected Direct control from the LPC host Two channels (choice of asynchronous or clocked synchronous serial communication mode) Full-duplex communication capability Selection of the desired bit rate and LSB-first or MSB-first transfer The SCI module supports a smart card (SIM) interface. Three channels (two channels are switchable between input pin and output pin) Two types of communication formats 2 I C bus format: addressing format with an acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only Four channels Conforms to PS/2 interface specifications Direct bus drive Interrupt and error detection Four channels Serial transfer of cycle type, address, and data in synchronization with the PCI clock Supports LPC interface I/O read and I/O write cycles Supports the shutdown function (LPCPD) of the LPC interface Watchdog timer Watchdog timer (WDT) Serial interface Serial communication interface with FIFO (SCIF) Serial communication interface (SCI) Smart card/ SIM HighI2C bus performance interface communication (IIC) * * * * * * * * * * * * * * * Keyboard buffer control unit (PS2) LPC interface (LPC) * * * * * * * * Rev. 1.00 Apr. 28, 2008 Page 5 of 994 REJ09B0452-0100 Section 1 Overview Classification Module/ Function Description * * * * * * * * * * * * * * * * * * * * One channel Supports communications between this LCI and SPI flash memory Capable of operating as a master Supports LPC reset and LPC shut-down One channel Selectable from four sampling clocks: Three internal clocks and subclock 18-byte FIFO incorporated Input-only pins: 13 pins Input/output pins: 112 pins (TFP-144V and TLP-145V) 128 pins (BP-176V) 76 pull-up resistors for TFP-144V and TLP-145V, and 84 pullup resistors for BP-176V 40 pins with LED drive capability 24 on-chip noise cancellers 144-pin thin QFP package (PTQP0144LC-A) (old code: TFP-144V, package dimensions: 16 x 16 mm, pin pitch: 0.40 mm) 176-pin BGA package (PLBG0176GA-A) (old code: BP-176V, package dimensions: 13 x 13 mm, pin pitch: 0.80 mm) 145-pin TLP package (PTLG0145JB-A) (package dimensions: 9 x 9 mm, pin pitch: 0.65 mm) Lead- (Pb-) free version Operating frequency: 8 to 20 MHz Power supply voltage: Vcc = 3.0 to 3.6 V, AVcc = 3.0 to 3.6 V Supply current: 25 mA (typ.) (Vcc = 3.3 V, AVcc = 3.3 V, = 20 MHz) -20 to +75C (regular specifications) FSI Highinterface performance communication (FSI) CIR interface (CIR) I/O ports Package Operating frequency/ Power supply voltage Operating peripheral temperature (C) Rev. 1.00 Apr. 28, 2008 Page 6 of 994 REJ09B0452-0100 Section 1 Overview 1.2 List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.2 Part No. R4F2117R List of Products ROM Capacity 160 Kbytes RAM Capacity 8 Kbytes Package Remarks PTQP0144LC-A Flash memory PLBG0176GA-A version PTLG0145JB-A Part no. R 4 F 2117R Indicates the product-specific number. H8S/2117R Indicates the type of ROM device. F: On-chip ROM Indicates the product classification Microcomputer R indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Name Code Rev. 1.00 Apr. 28, 2008 Page 7 of 994 REJ09B0452-0100 Section 1 Overview 1.3 Block Diagram Internal address bus Internal Data bus VCC VCC VCC VCL VSS VSS VSS VSS VSS RES XTAL EXTAL MD2 MD1 NMI ETRST PJ0*2 PJ1*2 PJ2*2 PJ3*2 PJ4*2 PJ5*2 PJ6*2 PJ7*2 PI0*2 PI1*2 PI2*2 PI3*2 PI4*2 PI5*2 PI6*2 PI7*2 PH0/ExIRQ6/TDPCYI2 PH1/ExIRQ7/TDPCKI2/TDPMCI2 PH2/CIRI PH3 PH4 PH5 PG0/ExIRQ8/TMIX/TDPCYI1 PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 PG2/ExIRQ10/SDA2 PG3/ExIRQ11/SCL2 PG4/ExIRQ12/ExSDAA PG5/ExIRQ13/ExSCLA PG6/ExIRQ14/ExSDAB PG7/ExIRQ15/ExSCLB PF0/PWMU0A/IRQ8 PF1/PWMU1A/IRQ9 PF2/TMOY/IRQ10/TDPCYI0 PF3/TMOX/IRQ11/TDPCKI0/TDPMCI0 PF4/PWMU2A PF5/PWMU3A PF6/PWMU4A PF7/PWMU5A PE0/ExEXCL PE1*1/ETCK PE2*1/ETDI PE3*1/ETDO PE4*1/ETMS PC0/TIOCA0/WUE8 PC1/TIOCB0/WUE9 PC2/TIOCC0/TCLKA/WUE10 PC3/TIOCD0/TCLKB/WUE11 PC4/TIOCA1/WUE12 PC5/TIOCB1/TCLKC/WUE13 PC6/TIOCA2/WUE14 PC7/TIOCB2/TCLKD/WUE15 H8S/2600CPU Bus controller Clock pulse generator RAM P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P40/TMI0/TxD2/TCMCYI0 P41/TMO0/RxD2/TCMCKI0/TCMMCI0 P42/SDA1/TCMCYI1 P43/TMI1/SCK2/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWX0/PWMU4B/TCMCYI3 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 P50/FTxD P51/FRxD P52/SCL0 ROM (flasf memory) CIR (1 channel) Port J FSI (1 channel) 16-bit TCM (4 channels) Address bus Data bus SCIF (1 channel) 16-bit TDP (3 channels) Port I Interrupt controller WDT (2 channels) Port 4 Port H 8-bit timer (4 channels) PS2 (4 channels) Port 5 SCI (2 channels) Smart Card I/F (2 channels) Port G 8-bit PWM (12 channels) Port 3 Port 2 Port 1 IIC (3 channels) Port F 14-bit PWM (2 channels) P60/KIN0 P61/KIN1 P62/KIN2 P63/KIN3 P64/KIN4 P65/KIN5 P66/IRQ6/KIN6 P67/IRQ7/KIN7 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 PD0/AN8 PD1/AN9 PD2AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15 Port E H-UDI 16-bit TPU (3 channels) Port D Port C Port B Port A Port 9 Port 8 Port 7 P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/TxD1/IRQ3 P85/RxD1/IRQ4 P86/SCK1/SCL1/IRQ5 10-bit A/D converter (16 channels) LPC (4 channels) Port 6 P90/IRQ2 P91/IRQ1 P92/IRQ0 P93/IRQ12 P94/IRQ13 P95/IRQ14 P96//EXCL P97/IRQ15/SDA0 PA0/KIN8/PS2DC PA1/KIN9/PS2DD PA2/KIN10/PS2AC PA3/KIN11/PS2AD PA4/KIN12/PS2BC PA5/KIN13/PS2BD PA6/KIN14/PS2CC PA7/KIN15/PS2CD Notes: 1. Not supported by the system development tool (emulator) 2. Not supported by TFP-144 V and TLP-145 V Rev. 1.00 Apr. 28, 2008 Page 8 of 994 REJ09B0452-0100 PB0/LSMI PB1/LSCI PB2/RI/PWMU0B PB3/DCD/PWMU1B PB4/DSR/FSIDO PB5/DTR/FSIDI PB6/CTS/FSICK PB7/RTS/FSISS AVref AVCC AVSS Figure 1.2 Internal Block Diagram Section 1 Overview 1.4 1.4.1 Pin Descriptions Pin Assignments P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS PC0/TIOCA0/WUE8 PC1/TIOCB0/WUE9 PC2/TIOCC0/TCLKA/WUE10 PC3/TIOCD0/TCLKB/WUE11 PC4//TIOCA1/WUE12 PC5/TIOCB1/TCLKC/WUE13 PC6//TIOCA2/WUE14 PC7/TIOCB2/TCLKD/WUE15 VCC P67/IRQ7/KIN7 P66/IRQ6/KIN6 P65/KIN5 P64/KIN4 P63/KIN3 P62/KIN2 P61/KIN1 P60/KIN0 AVref AVCC P77/AN7 P76/AN6 P75/AN5 P12 P11 VSS P10 FSISS/PB7/RTS FSICK/PB6/CTS FSIDI/PB5/DTR FSIDO/PB4/DSR PB3/DCD/PWMU1B PB2/RI/PWMU0B PB1/LSCI PB0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 P40/TMI0/TxD2/TCMCYI0 P41/TMO0/RxD2/TCMCKI0/TCMMCI0 P42/SDA1/TCMCYI1 VSS PH3 PH4 PH5 XTAL EXTAL 108 106105 103 101 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 104 102 100 107 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 H8S/2117R Group PTQP0144LC-A TFP-144V (Top View) 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVSS PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15 PG0/ExIRQ8/TMIX/TDPCYI1 PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 PG2/ExIRQ10/SDA2 PG3/ExIRQ11/SCL2 PG4/ExIRQ12/ExSDAA PG5/EXIRQ13/ExSCLA PG6/ExIRQ14/ExSDAB PG7/ExIRQ15/ExSCLB PF0/IRQ8/PWMU0A PF1/IRQ9/PWMU1A PF2/IRQ10/TMOY/TDPCYI0 PF3/IRQ11/TMOX/TDPCKI0/TDPMCI0 PF4/PWMU2A PF5/PWMU3A PF6/PWMU4A PF7/PWMU5A VSS PA0/KIN8/PS2DC PA1/KIN9/PS2DD PA2/KIN10/PS2AC PA3/KIN11/PS2AD PA4/KIN12/PS2BC Note: * Not supported by the system development tool (emulator) VCC P43/TMI1/SCK2/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWX0/PWMU4B/TCMCYI3 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 VSS RES MD1 PH0/ExIRQ6/TDPCYI2 NMI PH1/ExIRQ7/TDPCKI2/TDPMCI2 VCL P52/SCL0 P51/FRxD P50/FTxD P97/SDA0/IRQ15 P96//EXCL P95/IRQ14 P94/IRQ13 P93/IRQ12 P92/IRQ0 P91/IRQ1 P90/IRQ2 MD2 PH2/CIRI ETRST PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/ExEXCL PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD VCC Figure 1.3 Pin Assignments (TFP-144V) Rev. 1.00 Apr. 28, 2008 Page 9 of 994 REJ09B0452-0100 Section 1 Overview 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P12 PJ4 VSS PB6 PB3 PB1 P32 P36 P81 P85 P40 VSS NC P14 P13 VSS P10 PB4 PB0 P33 PJ1 P82 P86 P41 VSS PH5 P17 P15 P11 PJ3 PB5 PJ2 P31 P35 P80 P84 PJ0 PH3 P43 P22 P21 P20 P16 PB7 PB2 P30 P34 P37 P83 P42 PH4 P46 P25 P24 P26 P23 PJ5 P27 VSS VSS PC1 PC0 PC2 PC3 PC5 PC4 PC6 PC7 VCC PJ6 P67 P66 PJ7 P65 P64 P63 P62 AVref AVCC P77 P75 P73 P71 P61 AVref AVCC P74 P60 NC NC NC PD0 PD7 NC P76 P72 P70 AVSS AVSS PD3 PD6 PG2 PI0 PI1 PF3 PF7 NC PA3 PD1 PD4 PG0 PG3 PG6 PF1 PF6 VSS PA1 VCC VCC PD2 PD5 PG1 PG4 PG7 PF2 PF5 VSS PA0 PA2 PA4 H8S/2117R Group PLBG0176GA-A BP-176V (Top View) PG5 PF0 PF4 PI2 NC RES NMI PH1 P52 VCL P51 PI7 P97 P50 PI6 PI5 P95 P96 P94 P93 P91 P92 P90 PI4 PH2 PE3* PA6 PI3 PE0 XTAL EXTAL P45 VCC P44 P47 VSS MD1 VSS PH0 PE4* PE1* PA5 MD2 ETRST PE2* PA7 A INDEX B C D E F G H J K L M N P R : Non-connection pin (with solder ball) Note: * Not supported by the system development tool (emulator) Figure 1.4 Pin Assignments (BP-176V) Rev. 1.00 Apr. 28, 2008 Page 10 of 994 REJ09B0452-0100 Section 1 Overview 13 12 11 10 9 8 7 6 5 4 3 P11 P12 PB7 PB3 P30 P34 P80 P84 P41 P13 P10 VSS PB5 PB2 PB0 P33 P81 P85 P42 PH4 P15 P16 PB6 PB4 PB1 P32 P82 P86 VSS PH5 P47 P44 P46 C P20 P22 P14 P17 P31 P35 P36 P37 P83 P40 RES VSS MD1 D * P24 P25 P21 P27 P26 PC2 P23 VSS PC1 PC5 PC0 PC4 PC3 P67 PC6 VCC PC7 P63 P66 P65 P64 P61 P62 PD2 PD6 P60 P75 P76 P74 P73 P70 PD1 PD5 PG1 PG5 PF1 PF5 PA0 PA4 PA1 N P77 AVCC AVref P72 P71 PD0 AVSS PD4 PD3 PD7 PG7 PF3 PF6 VSS PA7 PA5 L PG0 PG6 PF2 PF4 PF7 PA2 PA3 VCC M H8S/2117R Group PTLG0145JB-A (Top View) PG2 PG3 PG4 NC PF0 * PE4 PA6 PE2* PE0 K PH3 XTAL P52 NMI P96 P51 P95 P94 P90 * P91 ETRST PE1 P50 P93 G P92 MD2 H PH2 * PE3 J 2 EXTAL P45 1 INDEX P43 A VCC B : NC Pin Note: * PH0 VCL E PH1 P97 F Not supported by the systen development tool (emulator) Figure 1.5 Pin Assignments (TLP-145V) Rev. 1.00 Apr. 28, 2008 Page 11 of 994 REJ09B0452-0100 Section 1 Overview 1.4.2 Pin Assignment in Each Operating Mode H8S/2117R Group Pin Assignment in Each Operating Mode Pin No. Pin Name TLP145V B1 A1 C2 B2 C1 C3 D2 D3 D1 E2 E3 F2 E1 E4 (N) F3 G2 F1 (N) F4 G4 H4 G1 Single-Chip Mode Mode 2 (EXPE = 0) VCC P43/TMI1/SCK2/TCMCKI1/TCMMCI1 P44/TMO1/PWMU2B/TCMCYI2 P45/PWMU3B/TCMCKI2/TCMMCI2 P46/PWX0/PWMU4B/TCMCYI3 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 VSS NC RES VSS MD1 PH0/ExIRQ6/TDPCYI2 NMI PH1/ExIRQ7/TDPCKI2/TDPMCI2 VCL P52/SCL0 P51/FRxD PI7 P50/FTxD P97/SDA0/IRQ15 PI6 PI5 P96//EXCL P95/IRQ14 P94/IRQ13 P93/IRQ12 Table 1.3 TFP144V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (N) 15 16 17 (N) 18 19 20 21 BP176V A1 C3 B1 C2 D3 C1 D2 E4 E3 D1 E2 E1 F4 F3 F1 F2 (N) G4 G3 (N) G1 G2 (N) H4 (N) H3 (N) H1 H2 J4 J3 Rev. 1.00 Apr. 28, 2008 Page 12 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 22 23 24 25 26 27 BP176V J1 J2 K4 K3 (N) K1 K2 L3 (N) L1 TLP145V H2 G3 J4 H1 J2 H3 K4 (T) J1 K2 (T) J3 (T) K1 (T) L2 (N) K3 (N) L1 (N) M1 N2 (N) M2 (N) M3 (N) N1 (N) N3 (N) L3 M4 L4 Single-Chip Mode Mode 2 (EXPE = 0) P92/IRQ0 P91/IRQ1 P90/IRQ2 PI4 MD2 PH2/CIRI PI3 ETRST PE4*/ETMS PE3*/ETDO PE2*/ETDI PE1*/ETCK PE0/ExEXCL PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD VCC VCC PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9/PA2DD NC PA0/KIN8/PA2DC VSS PI2 VSS PF7/PWMU5A PF6/PWMU4A Pin Name 28 (T) L2 (T) 29 L4 30 (T) M1 (T) 31 (T) M2 (T) 32 (T) M3 (T) 33 (N) N1 (N) 34 (N) M4 (N) 35 (N) N2 (N) 36 P1 P2 37 (N) R1 (N) 38 (N) N3 (N) 39 (N) R2 (N) 40 (N) P3 (N) N4 41 (N) R3 (N) 42 43 44 P4 M5 (N) R4 N5 P5 Rev. 1.00 Apr. 28, 2008 Page 13 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 45 46 47 48 49 50 BP176V R5 M6 N6 R6 P6 M7 N7 (N) TLP145V N4 M5 L5 M6 N5 K5 L6 (N) M7 (N) N6 (N) K6 (N) K7 (N) K8 (N) N7 (N) M8 (N) L7 K9 N8 M9 L8 K10 N9 M10 L9 N10 M11 Single-Chip Mode Mode 2 (EXPE = 0) PF5/PWMU3A PF4/PWMU2A Pin Name PF3/IRQ11/TMOX/TDPCKI0/TDPMCI0 PF2/IRQ10/TMOY/TDPCYI0 PF1/IRQ9/PWMU1A PF0/IRQ8/PWMU0A PI1 PG7/ExIRQ15/ExSCLB PG6/ExIRQ14/ExSDAB PG5/ExIRQ13/ExSCLA PI0 PG4/ExIRQ12/ExSDAA PG3/ExIRQ11/SCL2 NC PG2/ExIRQ10/SDA2 PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 PG0/ExIRQ8/TMIX/TDPCYI1 PD7/AN15 PD6/AN14 PD5/AN13 PD4/AN12 PD3/AN11 PD2/AN10 PD1/AN9 PD0/AN8 AVSS AVSS P70/AN0 P71/AN1 51 (N) R7 (N) 52 (N) P7 (N) 53 (N) M8 (N) N8 (N) 54 (N) R8 (N) 55 (N) P8 (N) M9 (N) 56 (N) N9 (N) 57 (N) R9 (N) 58 (N) P9 (N) 59 60 61 62 63 64 65 66 67 68 69 M10 N10 R10 P10 N11 R11 P11 M11 R12 P12 N12 R13 Rev. 1.00 Apr. 28, 2008 Page 14 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 BP176V M12 P13 R14 P14 R15 N13 P15 N14 M13 N15 M14 L12 M15 L13 L14 L15 K12 K13 K15 K14 J12 J13 J15 J14 H12 H13 H15 H14 G12 TLP145V L10 N11 N12 M13 N13 L12 M12 L11 E5 L13 K12 K11 J12 K13 J10 J11 H12 H10 J13 H11 G12 G10 H13 Single-Chip Mode Mode 2 (EXPE = 0) NC P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC NC AVCC AVref NC AVref P60/KIN0 P61/KIN1 P62/KIN2 P63/KIN3 P64/KIN4 PJ7 P65/KIN5 P66/IRQ6/KIN6 P67/IRQ7/KIN7 VCC PJ6 PC7/TIOCB2/TCLKD/WUE15 PC6/TIOCA2/WUE14 PC5/TIOCB1/TCLKC/WUE13 PC4/TIOCA1/WUE12 PC3/TIOCD0/TCLKB/WUE11 Pin Name Rev. 1.00 Apr. 28, 2008 Page 15 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 BP176V G13 G15 G14 F12 F13 F15 F14 E13 E15 E14 E12 D15 D14 D13 C15 D12 C14 B15 B14 A15 C13 A14 B13 C12 A13 B12 D11 A12 C11 TLP145V F12 G13 G11 F10 E10 F13 E12 E13 F11 D12 E11 D13 D10 C12 C13 D11 B13 A12 A13 B11 B12 A11 C11 B10 Single-Chip Mode Mode 2 (EXPE = 0) PC2/TIOCC0/TCLKA/WUE10 PC1/TIOCB0/WUE9 PC0/TIOCA0/WUE8 VSS VSS PJ5 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 PJ4 VSS PJ3 VSS P10 PB7/RTS/FSISS PB6/CTS/FSICK PB5/DTR/FSIDI Pin Name Rev. 1.00 Apr. 28, 2008 Page 16 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 136 137 BP176V B11 A11 D10 C10 A10 B10 D9 C9 A9 B9 D8 C8 A8 B8 D7 C7 A7 B7 D6 C6 A6 TLP145V C10 A10 B9 C9 B8 A9 D9 C8 B7 A8 D8 D7 D6 A7 B6 C7 D5 A6 B5 C6 (N) D4 A5 B4 (N) C5 A4 Single-Chip Mode Mode 2 (EXPE = 0) PB4/DSR/FSIDO PB3/DCD/PWMU1B PB2/RI/PWMU0B PJ2 PB1/LSCI PB0/LSMI P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK PJ1 P37/SERIRQ P80/PME P81/GA20 P82/CLKRUN P83/LPCPD P84/IRQ3/TxD1 P85/IRQ4/RxD1 P86/IRQ5/SCK1/SCL1 PJ0 P40/TMI0/TxD2/TCMCYI0 Pin Name 135 (N) B6 (N) C5 A5 B5 P41/TMO0/RxD2/TCMCKI0/TCMMCI0 P42/SDA1/TCMCYI1 VSS VSS PH3 138 (N) D5 (N) 139 140 A4 B4 C4 Rev. 1.00 Apr. 28, 2008 Page 17 of 994 REJ09B0452-0100 Section 1 Overview Pin No. TFP144V 141 142 143 144 BP176V A3 D4 B3 A2 B2 TLP145V B3 C4 A3 A2 Single-Chip Mode Mode 2 (EXPE = 0) NC PH4 PH5 XTAL EXTAL Pin Name Notes: (N) in Pin No. indicates the pin is driven by NMOS push-pull/open drain and has 5 V input tolerance. (T) in Pin No. indicates the pin has 5 V input tolerance. * This pin is not supported by the system development tool (emulator). Rev. 1.00 Apr. 28, 2008 Page 18 of 994 REJ09B0452-0100 Section 1 Overview 1.4.3 Pin Functions Pin Functions Pin No. Table 1.4 Type Power supply Symbol TFP-144V BP-176V TLP-145V I/O VCC 1, 36, 86 A1, J15, P1, P2 B1, M1, H10 Input Name and Function Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (that is located near these pins). External capacitance pin for internal step-down power. Connect this pin to VSS through an external capacitor (that is located near this pin) to stabilize internal step-down power. Ground pins. Connect all these pins to the system power supply (0 V). VCL 13 F1 E1 Input VSS 7, 42, 95, D1, D2, D2, L3, 111, 139 P4, R4, F10, B11, F12, F13, C5 B13, A13, A4, B4 143 144 A2 B2 A3 A2 Input Clock XTAL EXTAL Input Input For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For an example of crystal resonator connection, see section 25, Clock Pulse Generator. EXCL 18 18 H1 H1 M3 F4 F4 K1 Output Supplies the system clock to external devices. Input Input 32.768 kHz external sub clock should be supplied. To which pin the external clock is input can be selected from the EXCL or ExEXCL pin. These pins set the operating mode. Inputs at these pins should not be changed during operation. Reset pin. When this pin is low, the chip is reset. ExEXCL 32 Operating MD2 mode MD1 control System control RES 25 9 8 K1 E2 E3 H1 D1 D3 Input Input Rev. 1.00 Apr. 28, 2008 Page 19 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O 11 F4 G2, H2, J4, J3, N6, R6, P6, M7, J13, J12, B6, A6, C6, K4, J2, J1 R7, P7, M8, R8, P8, N9, R9, P9, F3, E1 L1 L2 L4 M1 M2 E3 F1, G4, H4, G1, L5, M6, N5, K5, H12, J11, C6, B5, A6, H2, G3, J4 L6, M7, N6, K6, K7, K8, N7, M8, F2, E2 H3 K4 J1 K2 J3 Input Input Name and Function Nonmaskable interrupt request input pin These pins request a maskable interrupt. To which pin an IRQ interrupt is input can be selected from the IRQn or ExIQRn pin. (n = 15 to 6) Interrupts NMI IRQ15 to 17, IRQ0 19 to 21, 47 to 50, 85, 84, 135 to 133, 24 to 22 ExIRQ15 51 to 58, to 12, 10 ExIRQ6 Input H-UDI ETRST*2 27 ETMS ETDO ETDI ETCK 28 29 30 31 Input Input Interface pins for emulator Reset by holding the ETRST pin to low level regardless of the H-UDI Output activation. At this time, the ETRST Input pin should be held low level for 20 clocks of ETCK. Then, to activate Input the H-UDI, the ETRST pin should be set to high level and the pins ETCK, ETMS, and ETDI should be set appropriately. In the normal operation without activating the HUDI, pins ETCK, ETMS, ETDI, and ETDO should be pulled up to high level. The ETRST pin is pulled up inside the chip. Output Waveform output pins with output compare function 8-bit timer (TMR_0, TMR_1, TMR_X, TMR_Y) TMO0 TMO1 TMOX TMOY TMI0 TMI1 TMIX TMIY 137 3 47 48 136 2 58 57 B5 B1 N6 R6 A5 C3 P9 R9 A5 C2 L5 M6 D4 A1 M8 N7 Input Counter event input and count reset input pins Rev. 1.00 Apr. 28, 2008 Page 20 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type Symbol TFP-144V BP-176V TLP-145V I/O 92 91 89 87 94 93 92 91 90 89 88 87 G13 G12 H15 H12 G14 G15 G13 G12 H14 H15 H13 H12 C1, C2, C3, B5 C1, C2, C3, B5 F12 H13 G12 J13 G11 G13 F12 H13 G10 G12 H11 J13 C3, B2, A1, A5 C3, B2, A1, A5 C1, C2, B4, D4 F2, N7, L5 F2, N7, L5 E2, M8, M6 M4, L4, N4, M5, N5, K5, C3, C1, B2, C2, A10, B9 Input Name and Function Timer external clock input pins 16-bit timer TCLKA pulse unit TCLKB (TPU) TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Input/ Output Input capture input/output compare output/PWM output pins for TGRA_0 to TGRD_0 Input capture input/output compare output/PWM output pins for TGRA_1 and TGRB_1 Input capture input/output compare output/PWM output pins for TGRA_2 and TGRB_2 Timer external clock input pins Input/ Output Input/ Output Input 16-bit cycle TCMCKI3 6, 4, 2, measure- to 137 ment timer TCMCKI0 (TCM) TCMMCI3 6, 4, 2, to 137 TCMMCI0 Input Cycle measurement enable input pins Timer input capture input pins TCMCYI3 5, 3, 138, D3, B1, to 136 D5, A5 TCMCYI0 16-bit duty period measurement timer (TDP) TDPCKI2 12, 57, 47 F3, R9, to N6 TDPCKI0 TDPMCI2 12, 57, 47 F3, R9, to N6 TDPMCI0 TDPCYI2 10, 58, 47 E1, P9, to R6 TDPCYI0 8-bit PWM PWMU5A 43 to 46, timer U to 49, 50, (PWMU) PWMU0A 6 to 3, PWMU5B 117, 118 to PWMU0B N5, P5, R5, M6, P6, M7, C1, D3, C2, B1, A11, D10 Input Input Timer external clock input pins Input Cycle measurement enable input pins Timer input capture input pins Input Output PWM timer pulse output pins Rev. 1.00 Apr. 28, 2008 Page 21 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type Symbol TFP-144V 5 6 133 136 134 137 135 2 39 37 34 41 38 35 33 40 BP-176V TLP-145V I/O D3 C1 C6 A5 A6 B5 B6 C3 R2 R1 M4 R3 N3 N2 N1 P3 N1, M4, N2, R1, N3, R2, P3, R3, J13, J12, K14, K13, K12, L15, L14, L13 H12, H13, H15, H14, G12, G13, G15, G14 C1 C3 A6 D4 B5 A5 C6 A1 M3 N2 K3 N3 M2 L1 L2 N1 Name and Function 14-bit PWM PWX0 timer PWX1 (PWMX) Serial communication interface (SCI_1, SCI_2) TxD1 TxD2 RxD1 RxD2 SCK1 SCK2 PS2AC PS2BC PS2CC PS2DC PS2AD PS2BD PS2CD PS2DD Keyboard control Output PWM timer pulse output pins Output Transmit data output pins Input Receive data input pins Input/ Clock input/output pins Output Output type of SCK1 and SCK2 is NMOS push-pull Input/ Synchronous clock Output input/output pins for the keyboard buffer control unit Input/ Data input/output pins for the Output keyboard buffer control unit Keyboard buffer control unit (PS2) KIN15 to 33 to 35, KIN0 37 to 41, 85 to 78 L2, K3, L1, Input N2, M2, M3, N1, N3, H12, J11, J10, K13, J12, K11, K12, L13 J13, H11, Input G12, G10, H13, F12, G13, G11 Input pins for matrix keyboard. Normally, KIN15 to KIN0 function as key scan inputs, and P17 to P10 and P27 to P20 function as key scan outputs. Thus, composed with a maximum of 16 outputs x 16 inputs, a 256-key matrix can be configured. Wake-up event input pins. Same wake up as key wake up can be performed with various sources. WUE15 87 to 94 to WUE8 Rev. 1.00 Apr. 28, 2008 Page 22 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type Serial communication interface with FIFO (SCIF) Symbol FTxD FRxD RI DCD DSR DTR CTS RTS LPC Interface (LPC) LAD3 to LAD0 TFP-144V 16 15 118 117 116 115 114 113 BP-176V TLP-145V G1 G4 D10 A11 B11 C11 A12 D11 G2 F3 B9 A10 C10 B10 C11 A11 I/O Output Input Input Input Input Output Input Output Name and Function Transmit data output pin Receive data input pin Ring indicator input pin Data carrier detect input pin Data set ready input pin Data terminal ready output pin Transmission permission input pin Transmission request output pin LPC command, address, and data input/output pins Input pin indicating LPC cycle start and forced termination of an abnormal LPC cycle Input pin indicating LPC reset LPC clock input pin LPC serial host interrupt (HIRQ1 to HIRQ15) input/output pin LPC auxiliary output pins. Functionally, they are general I/O ports. GATE A20 control signal output pin. Output state monitoring input is possible. Input/output pin that requests the start of LCLK operation when LCLK is stopped. Input pin that controls LPC module shutdown. 124 to 121 B9, A9, C9, D9 D8 B7, C8, D9, Input/ A9 Output A8 Input LFRAME 125 LRESET LCLK SERIRQ 126 127 128 C8 A8 D7 D8 D7 D6 Input Input Input/ Output LSCI, LSMI, PME GA20 119, 120, 129 130 A10, B10, C7 A7 C9, B8, A7 Input/ Output B6 Input/ Output Input/ Output CLKRUN 131 B7 C7 LPCPD 132 D6 D5 Input Rev. 1.00 Apr. 28, 2008 Page 23 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type FSI interface (FSI) Symbol FSISS FSICK FSIDI FSIDO CIR interface (CIR) CIRI TFP-144V 113 114 115 116 26 BP-176V TLP-145V D11 A12 C11 B11 K2 A11 C11 B10 C10 J2 I/O Output Output Input Output Input Name and Function FSI slave select pin Clock output pin Receive data input pin Transmit data output pin Receive data input pin A/D AN15 to converter AN0 59 to 66, 75 to 68 M10, N10, R10, P10, N11, R11, P11, M11, P15, N13, R15, P14, R14, P13, R13, N12 N14, N15 L7, K9, N8, Input M9, L8, K10, N9, M10, L12, N13, M13, N12, N11, L10, M11, N10 M12 Input Analog input pins AVCC 76 Analog power supply pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3 V). AVref 77 M14, M15 L11 Input Reference power supply pin for the A/D converter. When the A/D converter is not used, this pin should be connected to the system power supply (+3 V). AVSS 67 R12, P12 L9 Input Ground pin for the A/D converter. This pin should be connected to the system power supply (0 V). Rev. 1.00 Apr. 28, 2008 Page 24 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type I C bus interface (IIC) 2 Symbol SCL0 SCL1 SCL2 ExSCLA ExSCLB TFP-144V 14 135 55 53 51 BP-176V TLP-145V F2 B6 P8 M8 R7 E4 C6 K7 N6 L6 I/O Input/ Output Name and Function I2C clock I/O pins. The output type is NMOS open-drain. To which pin the clock is input or output can be selected from the SCL0, SCL1, ExSCLA, and ExSCLB pins. SDA0 SDA1 SDA2 ExSDAA ExSDAB 17 138 56 54 52 G2 D5 N9 R8 P7 F1 B4 K8 K6 M7 Input/ Output I2C data I/O pins. The output type is NMOS open-drain. To which pin the clock is input or output can be selected from the SDA0, SDA1, ExSDAA, and ExSDAB pins. I/O port P17 to P10 104 to 110, C15, D12, 112 C14, B15, B14, A15, C13, B12 96 to 103 F14, E13, E15, E14, E12, D15, D14, D13 D10, C12, C13, D11, B13, A12, A13, B12 E10, F13, E12, E13, F11, D12, E11, D13 D6, D7, D8, A8, B7, C8, D9, A9 C3, C1, B2, C2, A1, B4, A5, D7 Input/ Output 8-bit input/output pins P27 to P20 Input/ Output 8-bit input/output pins P37 to P30 128 to 121 D7, A8, C8, D8, B9, A9, C9, D9 6 to 2, C1, D3, 138 to 136 C2, B1, C3, D5, B5, A5 14 to 16 Input/ Output 8-bit input/output pins P47 to P40 Input/ Output 8-bit input/output pins (The output type of P42 is NMOS push-pull.) 3-bit input/output pins (The output type of P52 is NMOS push-pull.) 8-bit input/output pins P52 to P50 P67 to P60 F2, G4, G1 E4, F3, G2 J13, J12, K14, K13, K12, L15, L14, L13 H12, J11, J10, K13, J12, K11, K12, L13 Input/ Output Input/ Output 85 to 78 Rev. 1.00 Apr. 28, 2008 Page 25 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type I/O port Symbol P77 to P70 TFP-144V 75 to 68 BP-176V TLP-145V P15, N13, R15, P14, R14, P13, R13, N12 L12, N13, M13, N12, N11, L10, M11, N10 I/O Input Name and Function 8-bit input pins P86 to P80 135 to 129 B6, A6, C6, C6, B5, D6, B7, A7, A6, D5, C7 C7, B6, A7 17 to 24 G2, H1, F1, F4, H2, J4, J3, G4, H4, J1, J2, K4 G1, H2, G3, J4 N1, M4, N2, R1, N3, R2, P3, R3 Input/ Output 7-bit input/output pins (The output type of P86 is NMOS push-pull.) 8-bit input/output pins (The output type of P97 is NMOS push-pull.) 8-bit input/output pins (The output type of PA7 to PA0 is NMOS push-pull.) 8-bit input/output pins P97 to P90 Input/ Output PA7 to PA0 33 to 35, 37 to 41 L2, K3, L1, Input/ N2, M2, Output M3, N1, N3 A11, C11, B10, C10, A10, B9, C9, B8 Input/ Output PB7 to PB0 113 to 120 D11, A12, C11, B11, A11, D10, A10, B10 87 to 94 H12, H13, H15, H14, G12, G13, G15, G14 M10, N10, R10, P10, N11, R11, P11, M11 PC7 to PC0 J13, H11, Input/ G12, G10, Output H13, F12, G13, G11 L7, K9, N8, Input/ M9, L8, Output K10, N9, M10 8-bit input/output pins PD7 to PD0 59 to 66 8-bit input/output pins PE4 to PE0*1 PF7 to PF0 28 to 32 43 to 50 L2, L4, M1, K4, J1, K2, Input M2, M3 J3, K1 N5, P5, R5, M6, N6, R6, P6, M7 R7, P7, M8, R8, P8, N9, R9, P9 M4, L4, N4, Input/ M5, L5, Output M6, N5, K5 L6, M7, N6, Input/ K6, K7, K8, Output N7, M8 5-bit input pins 8-bit input/output pins PG7 to PG0 51 to 58 8-bit input/output pins (The output type of PG7 to PG0 is NMOS push-pull.) Rev. 1.00 Apr. 28, 2008 Page 26 of 994 REJ09B0452-0100 Section 1 Overview Pin No. Type I/O port Symbol PH5 to PH0 TFP-144V BP-176V TLP-145V I/O Name and Function 6-bit input/output pins 142 to 140, B3, D4, C4, B3, A4, Input/ 26, 12, 10 C4, K2, F3, J2, F2, E2 Output E1 G3, H4, H3, K3, L5, M5, N7, N8 K15, J14, F15, A14, C12, C10, B8, C5 Input/ Output Input/ Output PI7 to PI0 8-bit input/output pins (The output type of PI7 to PI0 is NMOS push-pull.) 8-bit input/output pins PJ7 to PJ0 Notes: 1. Pins PE4 to PE1 are not supported by the system development tool (emulator). 2. Following precautions are required on the power-on reset signal that is applied to the ETRST pin. The reset signal should be applied on power supply. Set apart the power-on reset circuit from this LSI to prevent the ETRST pin of the emulator from affecting the operation of this LSI. Set apart the power-on reset circuit from this LSI to prevent the system reset of this LSI from affecting the ETRST pin of the emulator. Rev. 1.00 Apr. 28, 2008 Page 27 of 994 REJ09B0452-0100 Section 1 Overview Rev. 1.00 Apr. 28, 2008 Page 28 of 994 REJ09B0452-0100 Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 2 states Rev. 1.00 Apr. 28, 2008 Page 29 of 994 REJ09B0452-0100 Section 2 CPU 16 / 8-bit register-register divide: 12 states 16 x 16-bit register-register multiply: 3 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by the SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions; Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd CLRMAC LDMAC CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC Note: * STMAC MACH,ERd STMAC MACl,ERd H8S/2600 2* 2* 3* 3* 1* 1* 1* 1* 1* H8S/2000 12 20 13 21 Not supported This becomes one state greater immediately after a MAC instruction. In addition, there are differences in address space, CCR and EXR register functions, and power-down modes, etc., depending on the model. Rev. 1.00 Apr. 28, 2008 Page 30 of 994 REJ09B0452-0100 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: * More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements: * More control registers One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 1.00 Apr. 28, 2008 Page 31 of 994 REJ09B0452-0100 Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space Linear access to a 64-kbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table structure in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to H'00FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. Rev. 1.00 Apr. 28, 2008 Page 32 of 994 REJ09B0452-0100 Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Exception vector 1 Exception vector 2 Exception vector 3 Exception vector 4 Exception vector 5 Exception vector 6 Exception vector table Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP (SP * 2 EXR*1 Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 1.00 Apr. 28, 2008 Page 33 of 994 REJ09B0452-0100 Section 2 CPU 2.2.2 Advanced Mode * Address Space Linear access to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 1.00 Apr. 28, 2008 Page 34 of 994 REJ09B0452-0100 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1, *3 CCR PC (24 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 1.00 Apr. 28, 2008 Page 35 of 994 REJ09B0452-0100 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area H'00FFFFFF Data area Cannot be used in this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.5 Memory Map Rev. 1.00 Apr. 28, 2008 Page 36 of 994 REJ09B0452-0100 Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 EXR T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Sign extension MACL 0 41 MACH 32 Figure 2.6 CPU Registers Rev. 1.00 Apr. 28, 2008 Page 37 of 994 REJ09B0452-0100 Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 1.00 Apr. 28, 2008 Page 38 of 994 REJ09B0452-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 I2 I1 I0 All 1 1 1 1 R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Rev. 1.00 Apr. 28, 2008 Page 39 of 994 REJ09B0452-0100 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Rev. 1.00 Apr. 28, 2008 Page 40 of 994 REJ09B0452-0100 Section 2 CPU Bit 1 Bit Name V Initial Value R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Undefined R/W 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 1.00 Apr. 28, 2008 Page 41 of 994 REJ09B0452-0100 Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type 1-bit data Register Number RnH Data Format 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 1.00 Apr. 28, 2008 Page 42 of 994 REJ09B0452-0100 Section 2 CPU Data Type Word data Register Number Rn Data Format 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB [Legend] ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.00 Apr. 28, 2008 Page 43 of 994 REJ09B0452-0100 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.10 Memory Data Formats Rev. 1.00 Apr. 28, 2008 Page 44 of 994 REJ09B0452-0100 Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* 3 3 1 1 Size Types B/W/L 5 W/L L B B/W/L 23 B B/W/L L B/W W/L B B/W/L 4 Arithmetic operation ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS B 14 5 9 1 Total: 69 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP Block data transfer EEPMOV Notes: B-byte; W-word; L-longword. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and MOV.L ERn,@-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Apr. 28, 2008 Page 45 of 994 REJ09B0452-0100 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) Rev. 1.00 Apr. 28, 2008 Page 46 of 994 REJ09B0452-0100 Section 2 CPU Symbol :8/:16/:24/:32 Note: * Description 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Note: * L L Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Apr. 28, 2008 Page 47 of 994 REJ09B0452-0100 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Apr. 28, 2008 Page 48 of 994 REJ09B0452-0100 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size*1 B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS*2 MAC B CLRMAC LDMAC STMAC Note: L 1. Refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Apr. 28, 2008 Page 49 of 994 REJ09B0452-0100 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. OR B/W/L XOR B/W/L NOT B/W/L (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. B/W/L B/W/L B/W/L Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Apr. 28, 2008 Page 50 of 994 REJ09B0452-0100 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B BNOT B ( Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ( Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ( BIAND B BOR B BIOR B Note: * Refers to the operand size. B: Byte Rev. 1.00 Apr. 28, 2008 Page 51 of 994 REJ09B0452-0100 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size*1 B Function C ( BIXOR B BLD B BILD B ( Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C ( BIST B C ( Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 1.00 Apr. 28, 2008 Page 52 of 994 REJ09B0452-0100 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 JMP BSR JSR RTS Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Rev. 1.00 Apr. 28, 2008 Page 53 of 994 REJ09B0452-0100 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B Refers to the operand size. B: Byte W: Word Rev. 1.00 Apr. 28, 2008 Page 54 of 994 REJ09B0452-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W Rev. 1.00 Apr. 28, 2008 Page 55 of 994 REJ09B0452-0100 Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) Rev. 1.00 Apr. 28, 2008 Page 56 of 994 REJ09B0452-0100 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Apr. 28, 2008 Page 57 of 994 REJ09B0452-0100 Section 2 CPU 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn Register indirect with post-increment@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Apr. 28, 2008 Page 58 of 994 REJ09B0452-0100 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Note: Normal mode is not available in this LSI. 2.7.6 Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Rev. 1.00 Apr. 28, 2008 Page 59 of 994 REJ09B0452-0100 Section 2 CPU 2.7.8 Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Normal mode is not available in this LSI. (a) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Mode Rev. 1.00 Apr. 28, 2008 Page 60 of 994 REJ09B0452-0100 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct(Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect(@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 *Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 1.00 Apr. 28, 2008 Page 61 of 994 REJ09B0452-0100 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Note: * Normal mode is not available in this LSI. Rev. 1.00 Apr. 28, 2008 Page 62 of 994 REJ09B0452-0100 Section 2 CPU 2.8 Processing States The H8S/2600 CPU has four main processing states: the reset state, exception handling state, program execution state and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Program Stop State This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For further details, refer to section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 63 of 994 REJ09B0452-0100 Section 2 CPU Program execution state SLEEP instruction with LSON = 0, PSS = 0, and SSBY = 1 End of exception handling SLEEP instruction with LSON = 0 and SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Power-down state*2 Reset state *1 Notes: 1. From any state, a transition to the reset state is made whenever the RES pin goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. The power-down state also includes watch mode. For details, refer to section 26, Power-Down Modes. Figure 2.13 State Transitions Rev. 1.00 Apr. 28, 2008 Page 64 of 994 REJ09B0452-0100 Section 2 CPU 2.9 2.9.1 Usage Note Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag beforehand. Rev. 1.00 Apr. 28, 2008 Page 65 of 994 REJ09B0452-0100 Section 2 CPU Rev. 1.00 Apr. 28, 2008 Page 66 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports three operating modes (modes 2, 4, and 6). The operating mode is determined by the setting of the mode pins (MD2 and MD1). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection Description Single-chip mode Flash memory programming/erasing On-Chip ROM Enabled MCU Operating CPU Operating Mode MD2 MD1 MD0* Mode 2 4 6 Note: * 0 1 1 1 0 1 0 0 0 Advanced Emulation On-chip emulation mode Enabled MD0 is not available as a pin and is internally fixed to 0. Modes 2 is single-chip mode. Modes 0, 1, 3, 5 and 7 are not available in this LSI. Modes 4 and 6 are operating modes for a special purpose. Thus, mode pins should be set to enable mode 2 in the normal program execution state. Mode pin settings should not be changed during operation. After a reset is canceled, the mode pin inputs should be latched by reading MDCR. Mode 4 is a boot mode for programming or erasing the flash memory. For details, see section 24, Flash Memory. Mode 6 is an on-chip emulation mode. In this mode, this LSI is controlled by an on-chip emulator (E10A) via the JTAG, thus enabling on-chip emulation. Rev. 1.00 Apr. 28, 2008 Page 67 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating modes. Table 3.2 Register Configuration Abbreviation MDCR SYSCR STCR SYSCR3 R/W R/W R/W R/W R/W Initial Value Address H'09 H'00 H'60 H'FFC5 H'FFC4 H'FFC3 H'FE7D Data Bus Width 8 8 8 8 Register Name Mode control register System control register Serial timer control register System control register 3 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode. Bit 7 Initial Bit Name Value EXPE 0 All 0 --* --* R/W R/W R R R Description Reserved The initial value should not be changed. 6 to 3 -- 2 1 MDS2 MDS1 Reserved The initial value should not be changed. Mode Select 2 and 1 These bits indicate the input levels at mode pins (MD2 and MD1) (the current operating mode). The MDS2 and MDS1 bits correspond to the MD2 and MD1 pins, respectively. These bits are read-only bits and cannot be written to. The input levels of the mode pins (MD2 and MD1) are latched into these bits when MDCR is read. These latches are canceled by a reset. 0 Note: -- * 0 R Reserved The initial value should not be changed. The initial values are determined by the settings of the MD2 and MD1 pins. Rev. 1.00 Apr. 28, 2008 Page 68 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables access to the on-chip peripheral module registers, and enables or disables the on-chip RAM address space. Bit 7, 6 5 4 Initial Bit Name Value -- INTM1 INTM0 All 0 0 0 R/W R R R/W Description Reserved The initial value should not be changed. Interrupt Control Select Mode 1 and 0 These bits select the interrupt control mode of the interrupt controller. For details on the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Interrupt control mode 1 10: Setting prohibited 11: Setting prohibited 3 XRST 1 R External Reset Indicates the reset source. A reset is caused by an external reset input, or when the watchdog timer overflows. 0: A reset is caused when the watchdog timer overflows 1: A reset is caused by an external reset 2 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input Rev. 1.00 Apr. 28, 2008 Page 69 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes Bit 1 Initial Bit Name Value KINWUE 0 R/W R/W Description Keyboard Control Register Access Enable When the RELOCATE bit is cleared to 0, this bit enables or disables CPU access for the keyboard matrix interrupt registers (KMIMRA and KMIMR), pullup MOS control register (KMPCR), and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC, TCORA_X, TCORB_X, TCONRI, and TCONRS) of 8-bit timers (TMR_X and TMR_Y) 0: Enables CPU access for registers of TMR_X and TMR_Y in areas from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF 1: Enables CPU access for the keyboard matrix interrupt registers and input pull-up MOS control register in areas from H'(FF)FFF0 to H'(FF)FFF7 and from H'(FF)FFFC to H'(FF)FFFF When the RELOCATE bit is set to 1, this bit is disabled. For details, see section 3.2.4, System Control Register 3 (SYSCR3) and section 27, List of Registers. 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 1.00 Apr. 28, 2008 Page 70 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit 7 6 5 Initial Bit Name Value IICX2 IICX1 IICX0 0 0 0 R/W R/W R/W R/W Description I2C Transfer Rate Select 2 to 0 These bits control the IIC operation. These bits select the transfer rate in master mode together with bits CKS2 to CKS0 in the I2C bus mode register (ICMR). For details on the transfer rate, see table 18.4. I2C Master Enable When the RELOCATE bit is cleared to 0, enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR, and ICRES), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL), and SCI registers (SMR, BRR, and SCMR). 0: SCI_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. SCI_2 registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. Access is prohibited in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. 1: IIC_1 registers are accessed in areas from H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to H'(FF)FF8F. PWMX registers are accessed in areas from H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to H'(FF)FFA7. IIC_0 registers are accessed in areas from H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF. ICRES is accessed in areas of H'(FF)FEE6 When the RELOCATE bit is set to 1, this bit is disabled. For details, see section 3.2.4, System Control Register 3 (SYSCR3) and section 27, List of Registers. 4 IICE 0 R/W Rev. 1.00 Apr. 28, 2008 Page 71 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes Bit 3 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Enables or disables CPU access for flash memory registers (FCCS, FPCS, FECS, FKEY, FMATS, and FTDAR), power-down state control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and on-chip peripheral module control registers (PCSR). 0: When RELOCATE is 0, control registers of powerdown state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. Area from H'(FF)FEA8 to H'(FF)FEAE is reserved. When RELOCATE is 1, control registers of powerdown state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. Area from H'(FF)FEA8 to H'(FF)FEAE is reserved. 1: When RELOCATE is 0, control registers of flash memory are accessed in an area from H'(FF)FEA8 to H'(FF)FEAE. Area from H'(FF)FF80 to H'(FF)FF87 is reserved. When RELOCATE is 1, control registers of powerdown state and peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87. Control registers of flash memory are accessed in an area from H'(FF)FEA8 to H'(FF)FEAE. 2 IICS 0 R/(W) I2C Extra Buffer Select Specifies bits 7 to 4 of port A as output buffers similar to 2 SLC and SDA. These pins are used to implement an I C interface only by software. 0: PA7 to PA4 are normal input/output pins. 1: PA7 to PA4 are input/output pins enabling bus driving. 1 0 ICKS1 ICKS0 0 0 R/W R/W Internal Clock Source Select 1 and 0 These bits select a clock to be input to the timer counter (TCNT) and a count condition together with bits CKS2 to CKS0 in the timer control register (TCR). For details, see section 13.3.4, Timer Control Register (TCR). Rev. 1.00 Apr. 28, 2008 Page 72 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes 3.2.4 System Control Register 3 (SYSCR3) SYSCR3 selects the register map and interrupt vector. Bit 7 6 Bit Name -- EIVS* Initial Value 0 1 R/W R/W R/W Description Reserved The initial value should not be changed. Extended interrupt Vector Select* Selects compatible mode or extended mode for the interrupt vector table. 0: H8S/2140B Group compatible vector mode 1: Extended vector mode For details, see section 5, Interrupt Controller. 5 RELOCATE 1 R/W Register Address Map Select Selects compatible mode or extended mode for the register map. When extended mode is selected for the register map, CPU access for registers can be controlled without using the KINWUE bit in SYSCR or the IICE bit in STCR to switch the registers to be accessed. 0: H8S/2140B Group compatible register map mode 1: Extended register map mode For details, see section 27, List of Registers. 4 to 0 -- Note: * All 0 R/W Reserved The initial value should not be changed. Switch the modes when an interrupt occurrence is disabled. 3.3 3.3.1 Operating Mode Descriptions Mode 2 The CPU can access a 16-Mbyte address space in either advanced mode or single-chip mode. The on-chip ROM is enabled. Rev. 1.00 Apr. 28, 2008 Page 73 of 994 REJ09B0452-0100 Section 3 MCU Operating Modes 3.4 Address Map Figures 3.1 shows the address map in each operating mode. Mode 2 (EXPE = 0) Advanced mode Single-chip mode ROM: 160 Kbytes RAM: 8 Kbytes H'000000 On-chip ROM 160 Kbytes H'027FFF H'028000 Reserved area H'0FFFFF H'FF0000 Reserved area H'FFD07F H'FFD080 H'FFEFFF H'FFF800 On-chip RAM 8064 bytes Internal I/O registers 2 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF On-chip RAM 128 bytes Internal I/O registers 1 Figure 3.1 Address Map Rev. 1.00 Apr. 28, 2008 Page 74 of 994 REJ09B0452-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, illegal instruction, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Illegal instruction Interrupt Start of Exception Handling Starts immediately after a low-to-high transition of the RES pin, or when the watchdog timer overflows. Exception handling starts when an undefined code is executed. Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. Starts when a direct transition occurs as the result of SLEEP instruction execution. Started by execution of a trap (TRAPA) instruction. Trap instruction exception handling requests are accepted at all times in the program execution state. Direct transition Trap instruction Low Rev. 1.00 Apr. 28, 2008 Page 75 of 994 REJ09B0452-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to exception sources. Table 4.2 and table 4.3 list the exception sources and their vector addresses. The EIVS bit in the system control register 3 (SYSCR3) allows the selection of the H8S/2140B Group compatible vector mode or extended vector mode. Table 4.2 Exception Handling Vector Table (H8S/2140B Group Compatible Vector Mode) Vector Number 0 1 3 4 5 6 7 8 9 10 11 Reserved for system use 12 15 16 17 18 19 20 21 22 23 Vector Addresses Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'00000C to H'00000F H'000010 to H'000013 H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F Exception Source Reset Reserved for system use Illegal instruction Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8 Rev. 1.00 Apr. 28, 2008 Page 76 of 994 REJ09B0452-0100 Section 4 Exception Handling Exception Source Internal interrupt* Vector Number 24 29 30 31 32 33 34 55 56 57 58 59 60 61 62 63 64 127 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Vector Addresses Advanced Mode H'000060 to H'000063 H'000074 to H'000077 H'000078 to H'00007B H'00007C to H'00007F H'000080 to H'000083 H'000084 to H'000087 H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001FC to H'0001FF Reserved for system use Reserved for system use Reserved for system use External interrupt WUE15 to WUE8 Internal interrupt* External interrupt IRQ8 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Tables. Rev. 1.00 Apr. 28, 2008 Page 77 of 994 REJ09B0452-0100 Section 4 Exception Handling Table 4.3 Exception Handling Vector Table (Extended Vector Mode) Vector Number 0 1 3 4 5 6 7 8 9 10 11 Vector Addresses Advanced Mode H'000000 to H'000003 H'000004 to H'000007 | H'00000C to H'00000F H'000010 to H'000013 H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 | H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'00004F H'000050 to H'000053 H'000054 to H'000057 H'000058 to H'00005B H'00005C to H'00005F H'000060 to H'000063 H'000074 to H'000077 H'000078 to H'00007B H'00007C to H'00007F H'000080 to H'000083 H'000084 to H'000087 Exception Source Reset Reserved for system use Illegal instruction Reserved for system use Direct transition External interrupt (NMI) Trap instruction (four sources) Reserved for system use 12 15 16 17 18 19 20 21 22 23 24 29 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Internal interrupt* External interrupt External interrupt External interrupt KIN7 to KIN0 KIN15 to KIN8 WUE15 to WUE8 30 31 32 33 Reserved for system use Rev. 1.00 Apr. 28, 2008 Page 78 of 994 REJ09B0452-0100 Section 4 Exception Handling Exception Source Internal interrupt* Vector Number 34 55 56 57 58 59 60 61 62 63 64 127 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Vector Addresses Normal Mode H'000088 to H'00008B H'0000DC to H'0000DF H'0000E0 to H'0000E3 H'0000E4 to H'0000E7 H'0000E8 to H'0000EB H'0000EC to H'0000EF H'0000F0 to H'0000F3 H'0000F4 to H'0000F7 H'0000F8 to H'0000FB H'0000FC to H'0000FF H'000100 to H'000103 H'0001FC to H'0001FF External interrupt IRQ8 Internal interrupt* Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Tables. 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer (WDT). 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and then program execution starts from the address indicated by the PC. Rev. 1.00 Apr. 28, 2008 Page 79 of 994 REJ09B0452-0100 Section 4 Exception Handling Figure 4.1 shows an example of the reset sequence. Vector fetch Internal processing Prefetch of first program instruction RES Internal address bus (1) U (1) L (3) Internal read signal Internal write signal Internal data bus (2) U High (2) L (4) (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction Figure 4.1 Reset Sequence (Mode 2) 4.3.2 Interrupts Immediately after Reset If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after a reset, make sure that this instruction initializes the SP (example: MOV.L #xx: 32, SP). 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) are initialized, and all modules except the DTC operate in module stop mode. Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read from and write to these registers, clear module stop mode. For details on module stop mode, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 80 of 994 REJ09B0452-0100 Section 4 Exception Handling 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 4.5 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC) and condition code register (CCR) are saved in the stack. 2. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR after execution of trap instruction exception handling. Table 4.4 Status of CCR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains value prior to execution Set to 1 Rev. 1.00 Apr. 28, 2008 Page 81 of 994 REJ09B0452-0100 Section 4 Exception Handling 4.6 Exception Handling by Illegal Instruction The exception handling by the illegal instruction starts when an undefined code is executed. The exception handling by the illegal instruction is always executable in the program execution state. The exception handling operates as follows: 1. The contents of the PC and CCR are saved in the stack. 2. The interrupt mask bit is updated. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to the PC, and program execution starts from that address. Table 4.5 shows the state of CCR after execution of illegal instruction exception handling. Table 4.5 Status of CCR after Illegal Instruction Exception Handling CCR Interrupt Control Mode 0 1 I Set to 1 Set to 1 UI Retains the previous value Set to 1 Illegal instruction code is not detected for fields that do not affect the definition of the instruction, such as an effective address extension (EA) and register fields. In addition, the instruction code of instructions consisting of multiple words are detected individually and are not detected as combinations of instruction codes. Do not execute instruction codes that are not defined. The contents of general registers are not guaranteed after the execution of an undefined instruction code or exception handling by the illegal instruction. The value of the stack pointer at the time of exception handling by the illegal instruction and the saved contents of the PC are also not guaranteed. Rev. 1.00 Apr. 28, 2008 Page 82 of 994 REJ09B0452-0100 Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode Advanced mode SP CCR CCR* PC (16 bits) SP CCR PC (24 bits) Notes: * Ignored on return. Normal mode is not available in this LSI. Figure 4.2 Stack Status after Exception Handling Rev. 1.00 Apr. 28, 2008 Page 83 of 994 REJ09B0452-0100 Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what occurs when the SP value is odd. CCR SP PC SP SP R1L H'FFEFFA H'FFEFFB H'FFEFFC PC H'FFEFFD H'FFEFFF TRAPA instruction executed SP set to H'FFEFFF [Legend] CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer MOV.B R1L, @-ER7 Contents of CCR lost Data saved above SP Note: This diagram illustrates an example in which interrupt control mode is 0 in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 1.00 Apr. 28, 2008 Page 84 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with ICR An interrupt control register (ICR) is provided for setting in each module interrupt priority levels for all interrupt requests excluding NMI and address breaks. * Three-level interrupt mask control By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask control is performed. * Forty-one external interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing, can be independently selected for IRQ15 to IRQ0. When the EIVS bit in the system control register 3 (SYSCR3) is cleared to 0, the IRQ6 interrupt is generated by IRQ6 or KIN7 to KIN0. The IRQ7 interrupt is generated by IRQ7 or KIN15 to KIN8. When the EIVS bit in the system control register 3 (SYSCR3) is set to 1, interrupts are requested on the falling edge of KIN15 to KIN0. For WUE15 to WUE8, either rising-edge or falling-edge detection can be selected individually for each pin regardless of the EIVS bit setting. * Two interrupt vector addresses are selectable H8S/2140B Group compatible interrupt vector addresses or extended interrupt vector addresses are selected depending on the EIVS bit in system control register 3 (SYSCR3). In extended mode, independent vector addresses are assigned for the interrupt vector addresses of KIN7 to KIN0 or KIN15 to KIN8 interrupts. * General ports for IRQ15 to IRQ6 input are selectable Rev. 1.00 Apr. 28, 2008 Page 85 of 994 REJ09B0452-0100 Section 5 Interrupt Controller EIVS SYSCR3 INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input IRQ input ISR ISCR IER Priority level determination I, UI CCR Interrupt request Vector number CPU KMIMR WUEMR KIN input WUE input Internal interrupt sources WOVI0 to IBFI3 ICR Interrupt controller KIN, WUE input [Legend] Interrupt control register ICR: IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: KMIMR: Keyboard matrix interrupt mask register WUEMR: Wake-up event interrupt mask register SYSCR: System control register SYSCR3: System control register 3 Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00 Apr. 28, 2008 Page 86 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Name NMI IRQ15 to IRQ0, ExIRQ15 to ExIRQ6 Pin Configuration I/O Input Input Function Nonmaskable external interrupt pin Rising edge or falling edge can be selected Maskable external interrupt pins Rising-edge, falling-edge, or both-edge detection, or levelsensing, can be selected individually for each pin. To which pin the IRQ15 to IRQ6 interrupt is input can be selected from the IRQm and ExIRQm pins. (n = 15 to 6) Maskable external interrupt pins When EIVS = 0, falling-edge or level-sensing can be selected. When EIVS = 1, an interrupt is requested at the falling edge. KIN15 to KIN0 Input WUE15 to WUE8 Input Maskable external interrupt pins Either rising edge or falling edge detection can be selected for each pin. Rev. 1.00 Apr. 28, 2008 Page 87 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For details on system control register 3 (SYSCR3), see section 3.2.4, System Control Register 3 (SYSCR3). Table 5.2 Register Configuration Abbreviation ICRA ICRB ICRC ICRD ABRKCR BARA BARB BARC ISCR16H ISCR16L ISCRH ISCRL IER16 IER ISR16 ISR KMIMRA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FEE8 H'FEE9 H'FEEA H'FE87 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEFA H'FEFB H'FEEC H'FEED H'FEF8 H'FFC2 H'FEF9 H'FEEB H'FFF3 H'FE83* KMIMR R/W H'BF H'FF* WUEMR ISSR16 ISSR R/W R/W R/W H'00 H'00 H'00 2 1 Register Name Interrupt control registers A Interrupt control registers B Interrupt control registers C Interrupt control registers D Address break control register Break address registers A Break address registers B Break address registers C IRQ sense control register 16H IRQ sense control register 16L IRQ sense control register H IRQ sense control register L IRQ enable register 16 IRQ enable register IRQ status register 16 IRQ status register Keyboard matrix interrupt mask register A Keyboard matrix interrupt mask register Wake-up event interrupt mask registers IRQ sense port select register 16 IRQ sense port select register Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFF1 H'FE81* H'FE45 H'FEFC H'FEFD 1 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 88 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Register Name Wake-up sense control register Wake-up input interrupt status register Wake-up enable register Note: Abbreviation WUESCR WUESR WER R/W R/W R/W R/W Initial Value Address H'00 H'00 H'00 H'FE84 H'FE85 H'FE86 Data Bus Width 8 8 8 1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when RELOCATE = 1 2. Address in the upper cell: when EIVS = 0, address in the lower cell: when EIVS = 1 5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence between interrupt sources and ICRA to ICRD settings is shown in tables 5.2 and 5.3. Bit Bit Name Initial Value All 0 R/W Description R/W Interrupt Control Level 0: Corresponding interrupt source is interrupt control level 0 (no priority) 1: Corresponding interrupt source is interrupt control level 1 (priority) Note: n: A to D 7 to 0 ICRn7 to ICRn0 Rev. 1.00 Apr. 28, 2008 Page 89 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Source and ICR (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Register Bit 7 6 5 4 3 2 1 0 Note: Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 -- WDT_0 WDT_1 ICRB A/D converter TCM_0, TCM_1, TCM_2, TCM_3 TDP_0, TDP_1, TDP_2 CIR TMR_0 TMR_1 TMR_X, TMR_Y PS2 ICRC SCIF SCI_1 SCI_2 IIC_0 IIC_1, IIC_2 FSI LPC, FSI -- ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 -- WUE8 to WUE15 TPU_0 TPU_1 TPU_2 -- n: A to D : Reserved. The initial value should not be changed. Table 5.4 Correspondence between Interrupt Source and ICR (Extended Vector Mode: EIVS = 1) Register Bit 7 6 5 4 3 2 1 0 Note: Bit Name ICRn7 ICRn6 ICRn5 ICRn4 ICRn3 ICRn2 ICRn1 ICRn0 ICRA IRQ0 IRQ1 IRQ2, IRQ3 IRQ4, IRQ5 IRQ6, IRQ7 -- WDT_0 WDT_1 ICRB A/D converter TCM_0, TCM_1, TCM_2, TCM_3 TDP_0, TDP_1, TDP_2 CIR TMR_0 TMR_1 TMR_X, TMR_Y PS2 ICRC SCIF SCI_1 SCI_2 IIC_0 IIC_1, IIC_2 FSI LPC, FSI -- ICRD IRQ8 to IRQ11 IRQ12 to IRQ15 KIN0 to KIN15 WUE8 to WUE15 TPU_0 TPU_1 TPU_2 -- n: A to D : Reserved. The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 90 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.2 Address Break Control Register (ABRKCR) ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an address break is requested. Bit 7 Bit Name CMF Initial Value Undefined R/W Description R Condition Match Flag Address break source flag. Indicates that an address specified by BARA to BARC is prefetched. [Clearing condition] When an exception handling is executed for an address break interrupt. [Setting condition] When an address specified by BARA to BARC is prefetched while the BIE bit is set to 1. 6 to 1 -- 0 BIE All 0 0 R Reserved These bits are always read as 0 and cannot be modified. R/W Break Interrupt Enable Enables or disables address break. 0: Disabled 1: Enabled Rev. 1.00 Apr. 28, 2008 Page 91 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. * BARA Bit 7 to 0 Bit Name A23 to A16 Initial Value R/W All 0 R/W Description Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus. * BARB Bit 7 to 0 Bit Name A15 to A8 Initial Value R/W All 0 R/W Description Addresses 15 to 8 The A15 to A8 bits are compared with A15 to A8 in the internal address bus. * BARC Bit 7 to 1 Bit Name A7 to A1 Initial Value R/W All 0 R/W Description Addresses 7 to 1 The A7 to A1 bits are compared with A7 to A1 in the internal address bus. 0 -- 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 92 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. * ISCR16H Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 15 to 12) Note: The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 (ISSR16). Rev. 1.00 Apr. 28, 2008 Page 93 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * ISCR16L Bit 7 6 5 4 3 2 1 0 Bit Name IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 11 to 8) Note: The IRQn or ExIRQn pin is selected by IRQ sense port select register 16 (ISSR16). * ISCRH Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn or ExIRQn input 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and rising edges of IRQn or ExIRQn input (n = 7 to 4) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register (ISSR). The ExIRQ5 and ExIRQ4 pins are not supported. Rev. 1.00 Apr. 28, 2008 Page 94 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * ISCRL Bit 7 6 5 4 3 2 1 0 Bit Name IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Sense Control B IRQn Sense Control A BA 00: Interrupt request generated at low level of IRQn input 01: Interrupt request generated at falling edge of IRQn input 10: Interrupt request generated at rising edge of IRQn input 11: Interrupt request generated at both falling and rising edges of IRQn input (n = 3 to 0) Rev. 1.00 Apr. 28, 2008 Page 95 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.5 IRQ Enable Registers (IER16, IER) The IER registers enable and disable interrupt requests IRQ15 to IRQ0. * IER16 Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable The IRQn interrupt request is enabled when this bit is 1. (n = 15 to 8) * IER Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQn Enable The IRQn interrupt request is enabled when this bit is 1. (n = 7 to 0) Rev. 1.00 Apr. 28, 2008 Page 96 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests. * ISR16 Bit 7 6 5 4 3 2 1 0 Bit Name IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial Value 0 0 0 0 0 0 0 0 R/W Description R/(W)* [Setting condition] R/(W)* When the interrupt source selected by the ISCR16 R/(W)* registers occurs R/(W)* [Clearing conditions] R/(W)* * When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* * When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn or R/(W)* ExIRQn input is high * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 15 to 8) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register 16 (ISSR16). Note: * Only 0 can be written for clearing the flag. Rev. 1.00 Apr. 28, 2008 Page 97 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * ISR Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W Description R/(W)* [Setting condition] R/(W)* When the interrupt source selected by the ISCR R/(W)* registers occurs R/(W)* [Clearing conditions] R/(W)* * When writing 0 to IRQnF flag after reading IRQnF = 1 R/(W)* * When interrupt exception handling is executed R/(W)* when low-level detection is set and IRQn or R/(W)* ExIRQn input is high * When IRQn interrupt exception handling is executed when falling-edge, rising-edge, or both-edge detection is set (n = 7 to 0) Note: The IRQn or ExIRQn pin is selected by the IRQ sense port select register (ISSR). The ExIRQ5 to ExIRQ0 pins are not supported. Note: * Only 0 can be written for clearing the flag. Rev. 1.00 Apr. 28, 2008 Page 98 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR) Wake-Up Event Interrupt Mask Registers (WUEMR) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0) and wake-up event interrupt inputs (WUE15 to WUE8). * KMIMRA Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request * KMIMR Bit 7 6 5 4 3 2 1 0 Bit Name KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial Value 1 0/1* 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Matrix Interrupt Mask These bits enable or disable a key-sensing input interrupt request (KIN7 to KIN0). 0: Enables a key-sensing input interrupt request 1: Disables a key-sensing input interrupt request When the EIVS bit in SYSCR3 is cleared to 0, the KMIMR6 bit also simultaneously controls enabling and disabling of the IRQ6 interrupt request. In this case, the initial value of the KMIMR6 bit is 0. When the EIVS bit is set to 1, the initial value of the KMIMR6 bit becomes 1. Note: * The initial value is 0 when EIVS = 0 and the initial value is 1 when EIVS = 1. Rev. 1.00 Apr. 28, 2008 Page 99 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * WUEMR Bit 7 6 5 4 3 2 1 0 Bit Name WUEMR15 WUEMR14 WUEMR13 WUEMR12 WUEMR11 WUEMR10 WUEMR9 WUEMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Mask These bits enable or disable a wake-up event input interrupt request (WUE15 to WUE8). 0: Enables a wake-up event input interrupt request 1: Disables a wake-up event input interrupt request Rev. 1.00 Apr. 28, 2008 Page 100 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Figure 5.2 shows the relation between the IRQ7 and IRQ6 interrupts, KMIMR, and KMIMRA in H8S/2140B Group compatible vector mode. The relation in extended vector mode is shown in figure 5.3. KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) P65/KIN5 KMIMR6 (Initial value of 0) P66/KIN6/IRQ6 IRQ6 internal signal Edge-level selection enable/disable circuit IRQ6 interrupt KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 PH1/ExIRQ7 ISS7 KMIMR8 (Initial value of 1) PA0/KIN8 KMIMR9 (Initial value of 1) PA1/KIN9 IRQ7 internal signal Edge-level selection enable/disable circuit IRQ7 interrupt KMIMR15 (Initial value of 1) PA7/KIN15 Note: The ISS7 bit is an external interrupt pin switch bit. For details, see section 5.3.8, IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR). Figure 5.2 Relation between IRQ7/IRQ6 Interrupts and KIN15 to KIN0 Interrupts, KMIMR, and KMIMRA (H8S/2140B Group Compatible Vector Mode: EIVS = 0) Rev. 1.00 Apr. 28, 2008 Page 101 of 994 REJ09B0452-0100 Section 5 Interrupt Controller In H8S/2140B Group compatible vector mode, interrupt input from the IRQ7 pin is ignored when even one of the KMIMR15 to KMIMR8 bits is cleared to 0. If the KIN7 to KIN0 pins or KIN15 to KIN8 pins are specified to be used as key-sensing interrupt input pins and wake-up event interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing. Note that interrupt input cannot be made from the ExIRQ6 pin. KMIMR0 (Initial value of 1) P60/KIN0 KMIMR5 (Initial value of 1) P65/KIN5 KMIMR6 (Initial value of 1) P66/KIN6/IRQ6 PH0/ExIRQ6 KMIMR7 (Initial value of 1) P67/KIN7/IRQ7 PH1/ExIRQ7 KMIMR8 (Initial value of 1) PA0/KIN8 KMIMR15 (Initial value of 1) PA7/KIN15 ISS7 KIN internal signal Falling-edge detection circuit Edge-level selection enable/disable circuit Edge-level selection enable/disable circuit KIN interrupt (KIN7 to KIN0) IRQ6 interrupt IRQ7 interrupt KINA internal signal Falling-edge detection circuit KINA interrupt (KIN15 to KIN8) Note: The ISS7 bit is an external interrupt pin switch bit. For details, see section 5.3.8, IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR). Figure 5.3 Relation between IRQ7 and IRQ6 Interrupts, KIN15 to KIN0 Interrupts, KMIMR, and KMIMRA (Extended Vector Mode: EIVS = 1) In extended vector mode, the initial value of the KMIMR6 bit is 1. Accordingly, it does not enable of disable the IRQ6 pin interrupt. The interrupt input from the ExIRQ6 pin becomes the IRQ6 interrupt request. Rev. 1.00 Apr. 28, 2008 Page 102 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.8 IRQ Sense Port Select Register 16 (ISSR16) IRQ Sense Port Select Register (ISSR) ISSR16 and ISSR select the IRQ15 to IRQ0 interrupt external input from the IRQ15 to IRQ7 pins and ExIRQ15 to ExIRQ7 pins. * ISSR16 Bit 7 6 5 4 3 2 1 0 Bit Name ISS15 ISS14 ISS13 ISS12 ISS11 ISS10 ISS9 ISS8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: P97/IRQ15 is selected 1: PG7/ExIRQ15 is selected 0: P95/IRQ14 is selected 1: PG6/ExIRQ14 is selected 0: P94/IRQ13 is selected 1: PG5/ExIRQ13 is selected 0: P93/IRQ12 is selected 1: PG4/ExIRQ12 is selected 0: PF3/IRQ11 is selected 1: PG3/ExIRQ11 is selected 0: PF2/IRQ10 is selected 1: PG2/ExIRQ10 is selected 0: PF1/IRQ9 is selected 1: PG1/ExIRQ9 is selected 0: PF0/IRQ8 is selected 1: PG0/ExIRQ8 is selected * ISSR Bit 7 6 to 0 Bit Name ISS7 Initial Value 0 0 R/W R/W R/W Description 0: P67/IRQ7 is selected 1: PH1/ExIRQ7 is selected Reserved The initial values should not be changed. Rev. 1.00 Apr. 28, 2008 Page 103 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt Status Register (WUESR) Wake-Up Enable Register (WER) WUESCR selects the interrupt source of the wake-up event interrupt inputs (WUE15 to WUE8). WUESR is an interrupt request flag register. WER enables/disables interrupts. * WUESCR Bit 7 6 5 4 3 2 1 0 Bit Name WUE15SC WUE14SC WUE13SC WUE12SC WUE11SC WUE10SC WUE9SC WUE8SC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Wake-Up Event Interrupt Source Select These bits select the source that generates an interrupt request at wake-up event interrupt inputs (WUE15 to WUE8). 0: Interrupt request generated at falling edge of WUEn input 1: Interrupt request generated at rising edge of WUEn input (n = 15 to 8) * WUESR Bit 7 6 5 4 3 2 1 0 Note: Bit Name WUE15F WUE14F WUE13F WUE12F WUE11F WUE10F WUE9F WUE8F * Initial Value 0 0 0 0 0 0 0 0 R/W Description R/(W)* Wake-Up Input Interrupt (WUE15 to WUE8) R/(W)* Request Flag Register R/(W)* These bits are status flags that indicate that wakeup input interrupts (WUE15 to WUE8) are R/(W)* requested. R/(W)* [Setting condition] R/(W)* * When a wake-up input interrupt is generated R/(W)* [Clearing condition] R/(W)* * When 0 is written after reading 1 Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 104 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * WER Bit 7 Bit Name WUEE Initial Value 0 R/W R/W Description WUE Enable The WUE interrupt request is enabled when this bit| is 1. 0: Wake-up input interrupt request is disabled 1: Wake-up input interrupt request is enabled 6 to 0 All 0 R/W Reserved The initial values should not be changed. 5.4 5.4.1 Interrupt Sources External Interrupt Sources The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE8. These interrupts can be used to restore this LSI from software standby mode. (1) NMI Interrupt The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling edge on the NMI pin. (2) IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. Interrupts IRQ15 to IRQ0 have the following features: * The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an independent vector address. * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6. * Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER. * The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. Rev. 1.00 Apr. 28, 2008 Page 105 of 994 REJ09B0452-0100 Section 5 Interrupt Controller When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and clear the IRQnF bit (n = 15 to 0) in ISR to 0. If the relevant IRQ input is put back to high level before the interrupt handling starts, the relevant interrupt may not be executed. The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function. A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.4. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S R Q IRQn interrupt request IRQn ISSm ExIRQn n = 15 to 7 m = 15 to 7 Clear signal Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit. Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0 (3) KIN15 to KIN0 Interrupts Interrupts KIN15 to KIN0 are requested by the input signals on pins KIN15 to KIN0. Functions of interrupts KIN15 to KIN0 change as follows according to the setting of the EIVS bit in system control register 3 (SYSCR3). * H8S/2140B Group compatible vector mode (EIVS = 0 in SYSCR3) Interrupts KIN15 to KIN8 correspond to interrupt IRQ7, and interrupts KIN7 to KIN0 correspond to interrupt IRQ6. The pin conditions for generating an interrupt request, whether the interrupt request is enabled, interrupt control level setting, and status of the interrupt request for the above interrupts are in accordance with the settings and status of the relevant interrupts IRQ7 and IRQ6. KIN15 to KIN0 interrupt requests can be masked by using KMIMRA and KMIMR. If the KIN7 to KIN0 pins are specified to be used as key-sensing interrupt input pins, the interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be set to low-level sensing or falling-edge sensing. Rev. 1.00 Apr. 28, 2008 Page 106 of 994 REJ09B0452-0100 Section 5 Interrupt Controller When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8 bits must all be set to 1. If even one of these bits is cleared to 0, the IRQ7 interrupt input from the IRQ7 pin is ignored. * Extended vector mode (EIVS = 1 in SYSCR3) Interrupts KIN15 to KIN8 and KIN7 to KIN0, each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address. Interrupt requests are generated on the falling edge of pins KIN15 to KIN0. Interrupt requests KIN15 to KIN0 can be masked by using KMIMRA and KMIMR. The status of interrupt requests KIN15 to KIN0 are not indicated. An IRQ6 interrupt is enabled only by input to the ExIRQ6 pin. The IRQ6 pin is only available for a KIN interrupt input, and functions as the KIN6 pin. The initial value of the KMIMR6 bit is 1. For the IRQ7 interrupt, either the IRQ7 pin or ExIRQ7 pin can be selected as the input pin using the ISS7 bit. The IRQ7 interrupt is not affected by the settings of bits KMIMR15 to KMIMR8. The detection of interrupts KIN15 to KIN0 does not depend on whether the relevant pin has been set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function. (4) WUE15 to WUE8 Interrupts Interrupt requests WUE15 to WUE8 can be configured regardless of the setting of the EIVS bit in system control register 3 (SYSCR3). A block diagram of interrupts WUE15 to WUE8 is shown in figure 5.5. WUEMRn Rising/falling-edge selection and interrupt enable/disable circuit WUEn input Clear signal S R Q WUEn interrupt request n = 15 to 8 Figure 5.5 Block Diagram of Interrupts WUE15 to WUE8 Rev. 1.00 Apr. 28, 2008 Page 107 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.4.2 Internal Interrupt Sources Internal interrupts issued from the on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. * The control level for each interrupt can be set by ICR. 5.5 Interrupt Exception Handling Vector Tables Tables 5.4 and 5.5 list interrupt exception handling sources, vector addresses, and interrupt priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for the vector addresses by the EIVS bit in system control register 3 (SYSCR3). For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt requests from modules that are set to interrupt control level 1 (priority) by the interrupt control level and the I and UI bits in CCR are given priority and processed before interrupt requests from modules that are set to interrupt control level 0 (no priority). Table 5.5 Interrupt Sources, Vector Addresses, and Interrupt Priorities (H8S/2140B Group Compatible Vector Mode) Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6, KIN7 to KIN0 IRQ7, KIN15 to KIN8 Vector Number 7 16 17 18 19 20 21 22 23 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 Low Priority High Origin of Interrupt Source External pin Rev. 1.00 Apr. 28, 2008 Page 108 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source -- WDT_0 WDT_1 -- Vector Address Name Reserved for system use WOVI0 (Interval timer) WOVI1 (Interval timer) Address break Vector Number 24 25 26 27 28 29 32 Advanced Mode H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'000080 H'000084 H'000088 H'00008C H'000090 H'000094 H'000098 H'00009C H'0000A0 H'0000A4 H'0000A8 H'0000AC H'0000B0 H'0000B4 H'0000B8 H'0000BC H'0000C0 -- ICRB6 ICRD1 ICRD2 ICRD4 ICRD3 ICR -- ICRA1 ICRA0 -- ICRB7 -- Priority High A/D converter ADI (A/D conversion end) -- Reserved for system use External pin TPU_0 WUE15 to WUE8 TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TGI0V (Overflow 0) TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TGI1V (Overflow 1) TGI1U (Underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 2) TGI2U (Underflow 2) Reserved for system use TICI0 (Input capture) TCMI0 (Compare match) TOVMI0 (Cycle overflow) TUDI0 (Cycle underflow) TOVI0 (Overflow) TICI1 (Input capture) TCMI1 (Compare match) TOVMI1 (Cycle overflow) TUDI1 (Cycle underflow) TOVI1 (Overflow) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TPU_1 TPU_2 -- TCM_0 TCM_1 49 H'0000C4 Low Rev. 1.00 Apr. 28, 2008 Page 109 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source TCM_2 Vector Address Name TICI2 (Input capture) TCMI2 (Compare match) TOVMI2 (Cycle overflow) TUDI2 (Cycle underflow) TOVI2 (Overflow) TICI3 (Input capture) TCMI3 (Compare match) TOVMI3 (Cycle overflow) TUDI3 (Cycle underflow) TOVI3 (Overflow) TICI0 (Input capture) TCMI0 (Compare match) TPDMXI0 (Cycle overflow) TPDMNI0 (Cycle underflow) TWDMNI0 (Pulse width lower limit underflow) TWDMXI0 (Pulse width upper limit overflow) TOVI0 (Overflow) TICI1 (Input capture) TCMI1 (Compare match) TPDMXI1 (Cycle overflow) TPDMNI1 (Cycle underflow) TWDMNI1 (Pulse width lower limit underflow) TWDMXI1 (Pulse width upper limit overflow) TOVI1 (Overflow) TICI2 (Input capture) TCMI2 (Compare match) TPDMXI2 (Cycle overflow) TPDMNI2 (Cycle underflow) TWDMNI2 (Pulse width lower limit underflow) TWDMXI2 (Pulse width upper limit overflow) TOVI2 (Overflow) Reserved for system use IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Vector Number 50 Advanced Mode H'0000C8 ICR ICRB6 Priority High TCM_3 51 H'0000CC TDP_0 52 H'0000D0 ICRB5 TDP_1 53 H'0000D4 TDP_2 54 H'0000D8 -- External pin 55 56 57 58 59 60 61 62 63 H'0000DC H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC -- ICRD7 ICRD6 Low Rev. 1.00 Apr. 28, 2008 Page 110 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source TMR_0 Vector Address Name CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) FSII (Transmission/reception completion) Reserved for system use Reserved for system use SCIF (SCIF interrupt) Reserved for system use ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) ERI2 (Reception error) RXI2 (Reception completion) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICI0 (1-byte transmission/reception completion) RENDI (Reception end) OVEI (Overrun error) REPI (Repeat detection) FREI (Framing error) ABI (Abort) HEADFI (Header detection) IICI1 (1-byte transmission/reception completion) IICI2 (1-byte transmission/reception completion) Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Advanced Mode H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 ICR ICRB3 Priority High -- TMR_1 -- ICRB2 -- TMR_X TMR_Y -- ICRB1 FSI -- ICRC2 -- SCIF -- SCI_1 ICRC7 -- ICRC6 SCI_2 ICRC5 IIC_0 CIR ICRC4 ICRB4 IIC_1 IIC_2 94 95 H'000178 H'00017C ICRC3 Low Rev. 1.00 Apr. 28, 2008 Page 111 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source PS2 Vector Address Name KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ KBCC (1st KCLKC) KBID (Reception completion D) KBTID (Transmission completion D)/KBCD (1st KCLKD) LFSII (Command reception)/(Write reception) Reserved for system use OBEI (ODR1 to 4 transmission completion) IBFI4 (IDR4 reception completion) ERR1 (Transfer error, etc.) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) Reserved for system use Vector Number 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 127 Advanced Mode H'000180 H'000184 H'000188 H'00018C H'000190 H'000194 H'000198 H'00019C H'0001A0 H'0001A4 H'0001A8 H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC H'0001C0 H'0001FC Low ICRC1 ICRC1 ICR ICRB0 Priority High FSI -- LPC -- Rev. 1.00 Apr. 28, 2008 Page 112 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Table 5.6 Interrupt Sources, Vector Addresses, and Interrupt Priorities (Extended Vector Mode) Vector Address Name NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector Number 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Advanced Mode H'00001C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 H'00006C H'000070 H'000074 H'000078 H'00007C H'000080 H'000084 H'000088 H'00008C H'000090 H'000094 H'000098 H'00009C H'0000A0 H'0000A4 H'0000A8 ICRD2 ICR -- ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 -- ICRA1 ICRA0 -- ICRB7 -- ICRD5 -- ICRD4 ICRD3 Priority High Origin of Interrupt Source External pin -- WDT_0 WDT_1 -- Reserved for system use WOVI0 (Interval timer) WOVI1 (Interval timer) Address break A/D converter ADI (A/D conversion end) -- External pin -- External pin TPU_0 Reserved for system use KIN7 to KIN0 KIN15 to KIN8 Reserved for system use WUE15 to WUE8 TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TGI0V (Overflow 0) TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TGI1V (Overflow 1) TGI1U (Underflow 1) TPU_1 Low Rev. 1.00 Apr. 28, 2008 Page 113 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source TPU_2 Vector Address Name TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TGI2V (Overflow 1) TGI2U (Underflow 2) Reserved for system use TICI0 (Input capture) TCMI0 (Compare match) TOVMI0 (Cycle overflow) TUDI0 (Cycle underflow) TOVI0 (Overflow) TICI1 (Input capture) TCMI1 (Compare match) TOVMI1 (Cycle overflow) TUDI1 (Cycle underflow) TOVI1 (Overflow) TICI2 (Input capture) TCMI2 (Compare match) TOVMI2 (Cycle overflow) TUDI2 (Cycle underflow) TOVI2 (Overflow) TICI3 (Input capture) TCMI3 (Compare match) TOVMI3 (Cycle overflow) TUDI3 (Cycle underflow) TOVI3 (Overflow) TICI0 (Input capture) TCMI0 (Compare match) TPDMXI0 (Cycle overflow) TPDMNI0 (Cycle underflow) TWDMNI0 (Pulse width lower limit underflow) TWDMXI0 (Pulse width upper limit overflow) TOVI0 (Overflow) TICI1 (Input capture) TCMI1 (Compare match) TPDMXI1 (Cycle overflow) TPDMNI1 (Cycle underflow) TWDMNI1 (Pulse width lower limit underflow) TWDMXI1 (Pulse width upper limit overflow) TOVI1 (Overflow) Vector Number 43 44 45 46 47 48 Advanced Mode H'0000AC H'0000B0 H'0000B4 H'0000B8 H'0000BC H'0000C0 -- ICRB6 ICR ICRD1 Priority High -- TCM_0 TCM_1 49 H'0000C4 TCM_2 50 H'0000C8 TCM_3 51 H'0000CC TDP_0 52 H'0000D0 ICRB5 TDP_1 53 H'0000D4 Low Rev. 1.00 Apr. 28, 2008 Page 114 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source Name TDP_2 TICI2 (Input capture) TCMI2 (Compare match) TPDMXI2 (Cycle overflow) TPDMNI2 (Cycle underflow) TWDMNI2 (Pulse width lower limit underflow) TWDMXI2 (Pulse width upper limit overflow) TOVI2 (Overflow) Reserved for system use IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match B) OVI0 (Overflow) Reserved for system use CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use CMIAY (Compare match A) CMIBY (Compare match B) OVIY (Overflow) ICIX (Input capture) CMIAX (Compare match A) CMIBX (Compare match B) OVIX (Overflow) FSII (Transmission/reception completion) Reserved for system use Reserved for system use SCIF (SCIF interrupt) Reserved for system use ERI1 (Reception error 1) RXI1 (Reception completion 1) TXI1 (Transmission data empty 1) TEI1 (Transmission end 1) Vector Address Vector Number 54 Advanced Mode H'0000D8 ICR Priority ICRB5 High -- External pin 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 H'0000DC H'0000E0 H'0000E4 H'0000E8 H'0000EC H'0000F0 H'0000F4 H'0000F8 H'0000FC H'000100 H'000104 H'000108 H'00010C H'000110 H'000114 H'000118 H'00011C H'000120 H'000124 H'000128 H'00012C H'000130 H'000134 H'000138 H'00013C H'000140 H'000144 H'000148 H'00014C H'000150 H'000154 H'000158 H'00015C -- ICRD7 ICRD6 ICRB3 -- TMR_1 -- ICRB2 -- TMR_X TMR_Y -- ICRB1 FSI SCIF SCI_1 ICRC2 -- ICRC7 -- ICRC6 Low Rev. 1.00 Apr. 28, 2008 Page 115 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Origin of Interrupt Source Name SCI_2 ERI2 (Reception error) RXI2 (Reception completion) TXI2 (Transmission data empty 2) TEI2 (Transmission end 2) IICI0 (1-byte transmission/reception completion) RENDI (Reception end) OVEI (Overrun error) REPI (Repeat detection) FREI (Framing error) ABI (Abort) HEADFI (Header detection) IICI1 (1-byte transmission/reception completion) IICI2 (1-byte transmission/reception completion) KBIA (Reception completion A) KBIB (Reception completion B) KBIC (Reception completion C) KBTIA (Transmission completion A)/ KBCA (1st KCLKA) KBTIB (Transmission completion B)/ KBCB (1st KCLKB) KBTIC (Transmission completion C)/ KBCC (1st KCLKC) KBID (Reception completion D) KBTID (Transmission completion D)/KBCD (1st KCLKD) LFSII (Command reception)/(Write reception) Reserved for system use OBEI (ODR1 to 4 transmission completion) IBFI4 (IDR4 reception completion) ERR1 (Transfer error, etc.) IBFI1 (IDR1 reception completion) IBFI2 (IDR2 reception completion) IBFI3 (IDR3 reception completion) Reserved for system use Vector Address Vector Number 88 89 90 91 92 93 Advanced Mode H'000160 H'000164 H'000168 H'00016C H'000170 H'000174 ICR Priority ICRC5 High IIC_0 CIR ICRC4 ICRB4 IIC_1 94 H'000178 ICRC3 IIC_2 95 H'00017C PS2 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 127 H'000180 H'000184 H'000188 H'00018C H'000190 H'000194 H'000198 H'00019C H'0001A0 H'0001A4 H'0001A8 H'0001AC H'0001B0 H'0001B4 H'0001B8 H'0001BC H'0001C0 H'0001FC ICRB0 FSI LPC ICRC1 ICRC1 Low Rev. 1.00 Apr. 28, 2008 Page 116 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI and address break interrupts are always accepted except for in the reset state. The interrupt control mode is selected by SYSCR. Table 5.7 shows the interrupt control modes. Table 5.7 Interrupt Control Modes Priority Setting Registers ICR Interrupt Mask Bits I Interrupt SYSCR Control Mode INTM1 INTM0 0 0 0 Description Interrupt mask control is performed by the I bit. Priority levels can be set with ICR. 3-level interrupt mask control is performed by the I and UI bits. Priority levels can be set with ICR. 1 0 1 ICR I, UI Figure 5.6 shows a block diagram of the priority determination circuit. I ICR UI Interrupt source Interrupt acceptance control and 3-level mask control Default priority determination Vector number Interrupt control modes 0 and 1 Figure 5.6 Block Diagram of Interrupt Control Operation Rev. 1.00 Apr. 28, 2008 Page 117 of 994 REJ09B0452-0100 Section 5 Interrupt Controller (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.8 shows the interrupts selected in each interrupt control mode. Table 5.8 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode I 0 0 1 1 0 1 UI * * * 0 1 [Legend] *: Don't care Selected Interrupts All interrupts (interrupt control level 1 has priority) NMI and address break interrupts All interrupts (interrupt control level 1 has priority) NMI, address break, and interrupt control level 1 interrupts NMI and address break interrupts (2) Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Rev. 1.00 Apr. 28, 2008 Page 118 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Table 5.9 shows operations and control signal functions in each interrupt control mode. Table 5.9 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control 3-Level Control I IM IM UI -- IM ICR PR PR Interrupt Control Mode INTM1 0 1 0 Setting INTM0 0 1 Default Priority Determination [Legend] : Interrupt operation control is performed IM: Used as an interrupt mask bit PR: Priority is set --: Not used 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than NMI and address break are masked by ICR and the I bit of CCR in the CPU. Figure 5.7 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break interrupts. Rev. 1.00 Apr. 28, 2008 Page 119 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? Yes Yes No NMI No An interrupt with interrupt control level 1? No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IRQ0 Yes IRQ1 IBFI3 Yes Yes IBFI3 Yes No No I=0 Yes No Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Apr. 28, 2008 Page 120 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting. * An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. * An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is cleared to 0. When both the I and UI bits are set to 1, the interrupt request is held pending. For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level 0) is shown below. Figure 5.8 shows a state transition diagram. * All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...) * Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI = 0. * Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1. I All interrupt requests are accepted I 0 0 1, UI Only NMI, address break, and interrupt control level 1 interrupt requests are accepted I Exception handling execution or I 1, UI 1 0 UI 0 Exception handling execution or UI 1 Only NMI and address break interrupt requests are accepted Figure 5.8 State Transition in Interrupt Control Mode 1 Rev. 1.00 Apr. 28, 2008 Page 121 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Figure 5.9 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt request with the highest priority is accepted according to the priority order, an interrupt handling is requested to the CPU, and other interrupt requests are held pending. 3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or when the I bit is set to 1 while the UI bit is cleared to 0. An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0. When both the I and UI bits are set to 1, only NMI and address break interrupt requests are accepted, and other interrupts are held pending. When the I bit is cleared to 0, the UI bit does not affect acceptance of interrupt requests. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I and UI bits in CCR are set to 1. This masks all interrupts except for NMI and address break interrupts. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Apr. 28, 2008 Page 122 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI No An interrupt with interrupt control level 1? No Hold pending Yes No No IRQ1 Yes IBFI3 Yes No IRQ0 Yes IRQ1 Yes IBFI3 Yes No IRQ0 Yes I=0 Yes No I=0 No Yes No UI = 0 Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 1.00 Apr. 28, 2008 Page 123 of 994 REJ09B0452-0100 5.6.3 REJ09B0452-0100 Internal processing Stack access Vector fetch Prefetch of instruction in Internal interrupt processing handling routine (1) (3) (5) (7) (9) (11) (13) Section 5 Interrupt Controller Interrupt is accepted Interrupt level determination and Instruction wait for end of prefetch instruction Rev. 1.00 Apr. 28, 2008 Page 124 of 994 Interrupt request signal Internal address bus Interrupt Exception Handling Sequence Internal read signal Internal write signal (2) (8) (4) (6) (10) (12) (14) Internal data bus Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.10 Interrupt Exception Handling (6) (8) Saved PC and CCR (9) (11) Vector address (10) (12) Start address of interrupt handling routine (contents of vector address) (13) Start address of interrupt handling routine ((13) = (10) (12)) (14) First instruction in interrupt handling routine (1) Instruction prefetch address (Not executed. Address is saved as PC contents, becoming return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP - 2 (7) SP - 4 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.10 shows interrupt response times - the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 5.10 Interrupt Response Times No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode 3 1 to 21 2 2 Number of wait states until executing instruction ends*2 Saving of PC and CCR in stack Vector fetch Instruction fetch* 3 4 2 2 12 to 32 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and prefetch of interrupt handling routine. Internal processing after interrupt acceptance and internal processing after vector fetch. Rev. 1.00 Apr. 28, 2008 Page 125 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.7 5.7.1 Address Breaks Features With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate an address break interrupt, using the ABRKCR and BAR registers. When an address break interrupt is generated, address break interrupt exception handling is executed. This function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.7.2 Block Diagram Figure 5.11 shows a block diagram of the address break function. BAR ABRKCR Match signal Comparator Control logic Address break interrupt request Internal address Prefetch signal (internal signal) Figure 5.11 Block Diagram of Address Break Function Rev. 1.00 Apr. 28, 2008 Page 126 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.7.3 Operation ABRKCR and BAR settings can be made so that an address break interrupt is generated when the CPU prefetches the address set in BAR. This address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. When the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. With an address break interrupt, interrupt mask control by the I and UI bits in the CPU's CCR is ineffective. The register settings when the address break function is used are as follows. 1. Set the break address in bits A23 to A1 in BAR. 2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be requested if the BIE bit is cleared to 0. When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is requested. If necessary, the source should be identified in the interrupt handling routine. 5.7.4 Usage Notes * With the address break function, the address at which the first instruction byte is located should be specified as the break address. Occurrence of the address break condition may not be recognized for other addresses. * If a branch instruction (Bcc, BSR) jump instruction (JMP, JSR), RTS instruction, or RTE instruction is located immediately before the address set in BAR, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. This can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. * As an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. Figure 5.12 shows some address timing examples. Rev. 1.00 Apr. 28, 2008 Page 127 of 994 REJ09B0452-0100 Section 5 Interrupt Controller * Program area in on-chip memory, 1-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch fetch operation Stack save Vector fetch Internal Instruction operation fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP NOP NOP execution execution execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction is executed at breakpoint address H'0312 and next address, H'0314; fetch from address H'0316 starts after end of exception handling. * Program area in on-chip memory, 2-state execution instruction at specified break address Instruction Instruction Instruction Instruction Instruction Internal fetch fetch fetch fetch operation fetch Stack save Vector fetch Internal Instruction operation fetch Address bus H'0310 H'0312 H'0314 H'0316 H'0318 SP-2 SP-4 H'0036 NOP execution MOV.W execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP MOV.W #xx : 16,Rd NOP NOP Breakpoint MOV instruction is executed at breakpoint address H'0312, NOP instruction at next address, H'0316, is not executed; fetch from address H'0316 starts after end of exception handling. * Program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address (Not available in this LSI) Instruction fetch Instruction fetch Instruction fetch Internal operation Stack save Vector fetch Internal operation Address bus H'0310 H'0312 H'0314 SP-2 SP-4 H'0036 NOP execution Interrupt exeption handling Break request signal H'0310 H'0312 H'0314 H'0316 NOP NOP NOP NOP Breakpoint NOP instruction at breakpoint address H'0312 is not executed; fetch from address H'0312 starts after end of exception handling. Figure 5.12 Examples of Address Break Timing Rev. 1.00 Apr. 28, 2008 Page 128 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.8 5.8.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.13 shows an example where the CMIEA bit in TCR of the TMR is cleared to 0. The above conflict will not occur if an interrupt enable bit or interrupt source flag is cleared to 0 while the interrupt is disabled. TCR write cycle by CPU CMIA exception handling Internal address bus TCR address Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.13 Conflict between Interrupt Generation and Disabling Rev. 1.00 Apr. 28, 2008 Page 129 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.8.2 Instructions for Disabling Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request including NMI issued during data transfer is not accepted until data transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during data transfer, interrupt exception handling starts at a break in the transfer cycles. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 5.8.4 Vector Address Switching Switching between H8S/2140B Group compatible vector mode and extended vector mode must be done in a state with no interrupts occurring. If the EIVS bit in SYSCR3 is changed from 0 to 1 when interrupt input is enabled because the KIN15 to KIN0 and WUE15 to WUE8 pins are set at low level, a falling edge is detected, thus causing an interrupt to be generated. The vector mode must be changed when interrupt input is disabled, that is the KIN15 to KIN0 and WUE15 to WUE8 pins are set at high level. Rev. 1.00 Apr. 28, 2008 Page 130 of 994 REJ09B0452-0100 Section 5 Interrupt Controller 5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode * When the pins (IRQ15 to IRQ0, ExIRQ15 to ExIRQ6, KIN15 to KIN0, and WUE15 to WUE8) are used as external input pins in software standby mode or watch mode, the pins should not be left floating. * When the external interrupt pins (IRQ7, IRQ6, ExIRQ15 to ExIRQ8, KIN7 to KIN0, and WUE15 to WUE8) are used in software standby and watch modes, the noise canceller should be disabled. 5.8.6 Noise Canceller Switching The noise canceller should be switched when the external input pins (IRQ7, IRQ6, ExIRQ15 to ExIRQ8, KIN7 to KIN0, and WUE15 to WUE8) are high. 5.8.7 IRQ Status Register (ISR) Since IRQnF may be set to 1 according to the pin state after reset, the ISR should be read after reset, and then write 0 in IRQnF (n = 15 to 0). Rev. 1.00 Apr. 28, 2008 Page 131 of 994 REJ09B0452-0100 Section 5 Interrupt Controller Rev. 1.00 Apr. 28, 2008 Page 132 of 994 REJ09B0452-0100 Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. 6.1 Register Descriptions The bus controller has the following registers. Table 6.1 Register Configuration Abbreviation BCR WSCR R/W R/W R/W Initial Value Address H'D3 H'F3 H'FFC6 H'FFC7 Data Bus Width 8 8 Register Name Bus control register Wait state control register 6.1.1 Bus Control Register (BCR) Initial Bit Name Value -- ICIS0 1 1 Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Idle Cycle Insertion The initial value should not be changed. Burst ROM Enable The initial value should not be changed. Burst Cycle Select 1 The initial value should not be changed. Burst Cycle Select 0 The initial value should not be changed. Reserved The initial value should not be changed. IOS Select 1 and 0 The initial value should not be changed. BRSTRM 0 BRSTS1 1 BRSTS0 0 IOS1 IOS0 0 1 1 Rev. 1.00 Apr. 28, 2008 Page 133 of 994 REJ09B0452-0100 Section 6 Bus Controller (BSC) 6.1.2 Wait State Control Register (WSCR) Initial Bit Name Value -- ABW AST WMS1 WMS0 WC1 WC0 All 1 1 1 0 0 1 1 Bit 7, 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Bus Width Control The initial value should not be changed. Access State Control The initial value should not be changed. Wait Mode Select 1 and 0 The initial value should not be changed. Wait Count 1 and 0 The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 134 of 994 REJ09B0452-0100 Section 7 I/O Ports Section 7 I/O Ports Table 7.1 lists the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port input data register (PIN) used to read the pin states. Port E does not have a DR or a DDR register. Ports 1 to 3, 6, 9, B to D, F, H, and J have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. In addition, ports 1 to 3, C, and D can drive a LED (5 mA sink current). P52, P97, P86, P42, ports A, G, and I are NMOS push-pull outputs and 5-V tolerant inputs. PE4 and PE2 to PE0 are 5-V tolerant inputs. Ports I and J are not supported by TFP-144V and TLP-145V. Rev. 1.00 Apr. 28, 2008 Page 135 of 994 REJ09B0452-0100 Section 7 I/O Ports Table 7.1 Port Functions Function up MOS LED Drive Input Pull- Capability On-Chip Canceler (5 mA Sink Noise Current) O Port Port 1 Description General I/O port Bit I/O 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 Input Output Function O Port 2 General I/O port 7 6 5 4 3 2 1 0 O O Port 3 General I/O port also functioning as LPC input/output 7 6 5 4 3 2 1 0 P37/SERIRQ P36 P35 P34 P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0 LCLK LRESET LFRAME O O Rev. 1.00 Apr. 28, 2008 Page 136 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Port 4 Description General I/O port also functioning as PWMX and PWMU_B outputs, TCM input, and TMR_0, TMR_1, IIC_1, and SCI_2 inputs/outputs 2 1 P42/SDA1 P41 3 P43/SCK2 TMI1/TCMCKI1/ TCMMCI1 TCMCYI1 RxD2/TCMCKI0/ TCMMCI0 0 Port 5 General I/O port also functioning as IIC_0 and SCIF inputs/outputs Port 6 General I/O port also functioning as 7 6 P67 P66 P65 P64 P63 P62 P61 P60 KIN7/IRQ7 KIN6/IRQ6 KIN5 KIN4 KIN3 KIN2 KIN1 KIN0 O 2 1 0 P40 P52/SCL0 P51 P50 TMI0/TCMCYI0 FRxD TxD2 FTxD TMO0 4 P44 5 P45 TCMCKI2/ TCMMCI2 TCMCYI2 TMO1/PWMU2B PWMU3B 6 P46 Bit I/O 7 P47 Input TCMCKI3/ TCMMCI3 TCMCYI3 PWX0/PWMU4B Output Function LED Drive Input Pull- Capability Current) On-Chip Canceler (5 mA Sink Noise PWX1/PWMU5B O interrupt input 5 and keyboard 4 input 3 2 1 0 Rev. 1.00 Apr. 28, 2008 Page 137 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Port 7 Description Bit I/O P86/SCK1/ SCL1 5 4 3 2 1 0 Port 9 General I/O port also functioning as external subclock, interrupt input, IIC_0 input/output, and system clock output 7 6 5 4 3 2 1 0 P85 P84 P83 RxD1/IRQ4 IRQ3 LPCPD TxD1 O (P95 to P90) Input P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 IRQ5 Output Function LED Drive Input Pull- Capability Current) On-Chip Canceler (5 mA Sink Noise General input 7 port also functioning as analog input 6 A/D converter 5 4 3 2 1 0 Port 8 General I/O port also functioning as interrupt input, IIC_1, SCI_1, and LPC inputs/outputs 6 P82/CLKRUN P81/GA20 P80/PME P97/SDA0 P96 P95 P94 P93 P92 P91 P90 IRQ15 EXCL IRQ14 IRQ13 IRQ12 IRQ0 IRQ1 IRQ2 Rev. 1.00 Apr. 28, 2008 Page 138 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Port A Description General I/O port also functioning as keyboard input and PS2 input/output Bit I/O 7 6 5 4 3 2 1 0 Port B General I/O port also functioning as LPC, SCIF and FSI inputs/outputs and PWMU output 7 6 5 4 3 2 1 0 Port C General I/O port also functioning as and TPU input/output 7 6 PA7/PS2CD PA6/PS2CC PA5/PS2BD PA4/PS2BC PA3/PS2AD PA2/PS2AC PA1/PS2DD PA0/PS2DC PB7 PB6 PB5 PB4 PB3 PB2 PB1/LSCI PB0/LSMI Input KIN15 KIN14 KIN13 KIN12 KIN11 KIN10 KIN9 KIN8 CTS FSIDI DSR DCD RI Output RTS/FSISS FSICK DTR FSIDO PWMU1B PWMU0B O O Function LED Drive Input Pull- Capability Current) On-Chip Canceler (5 mA Sink Noise PC7/TIOCB2 TCLKD/WUE15 PC6/TIOCA2 WUE14 PC5/TIOCB1 TCLKC/WUE13 PC4/TIOCA1 WUE12 PC3/TIOCD0 TCLKB/WUE11 PC2/TIOCC0 TCLKA/WUE10 PC1/TIOCB0 WUE9 PC0/TIOCA0 WUE8 O O wake-up input 5 4 3 2 1 0 Rev. 1.00 Apr. 28, 2008 Page 139 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Port D Description General I/O port also functioning as analog input Bit I/O 7 6 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 Input AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 PE4* /ETMS PE3* 1 1 LED Drive Input Pull- Capability Output ETDO PWMU5A PWMU4A PWMU3A PWMU2A TMOX O Function O Current) O On-Chip Canceler (5 mA Sink Noise A/D converter 5 4 3 2 1 0 Port E General input 4 port also functioning as clock input, emulator input/output Port F General I/O port also functioning as interrupt and TDP inputs, TMR_X, TMR_Y, and PWM outputs 2 1 0 3 external sub- 2 1 0 7 6 5 4 3 PE2* /ETDI PE1*1 /ETCK PE0/ExEXCL TDPCKI0/ TDPMCI0/IRQ11 1 PF2 PF1 PF0 TDPCYI0//IRQ10 IRQ9 IRQ8 TMOY PWMU1A PWMU0A Rev. 1.00 Apr. 28, 2008 Page 140 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Description Bit I/O 7 6 5 4 3 2 Input Output Function LED Drive Input Pull- Capability Current) On-Chip Canceler O (5 mA Sink Noise Port G General I/O port also functioning as interrupt and TDP inputs, TMR_X and TMR_Y inputs, and IIC0 to IIC2 PG7/ExSCLB ExIRQ15 PG6/ExSDAB ExIRQ14 PG5/ExSCLA ExIRQ13 PG4/ExSDAA ExIRQ12 PG3/SCL2 PG2/SDA2 PG1 ExIRQ11 ExIRQ10 TMIY1/ TDPCKI1/TDPMCI1/ ExIRQ9 inputs/outputs 1 0 PG0 TMIX/TDPCYI1 ExIRQ8 Port H General I/O port also functioning as interrupt and TDP and CIR inputs 5 4 3 2 1 PH5 PH4 PH3 PH2 PH1 CIRI TDPCKI2/ TDPMCI1/ ExIRQ7 O 0 PH0 TDPCYI2/ ExIRQ6 Port I General I/O port 7 6 5 4 3 2 1 0 PI7*2 PI6*2 PI5*2 PI4* PI3* PI2* PI1* PI0* 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 141 of 994 REJ09B0452-0100 Section 7 I/O Ports Function up MOS Port Port J Description General I/O port Bit I/O 7 6 5 4 3 2 1 0 PJ7* PJ6* PJ5* 2 LED Drive Input Pull- Capability On-Chip Canceler (5 mA Sink Noise Current) Input Output Function O 2 2 PJ4*2 PJ3*2 PJ2* PJ1* PJ0* 2 2 2 Notes: 1. Not supported by the system development tool (emulator). 2. Not supported by TFP-144V and TLP-145V. Rev. 1.00 Apr. 28, 2008 Page 142 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1 Register Descriptions Table 7.2 lists each port registers. Table 7.2 Register Configuration in Each Port Number of Pins DDR 8 8 8 8 3 8 8 7 8 8 8 8 8 5 8 8 6 8*1 8* 1 Registers DR O O O O O O Port Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F Port G Port H Port I Port J PIN O* 2 PCR O O O KMPCR ODR NCE NCMC NCCS NOCR O O O O O O O*2 O* O* O* O* O O* O* O O O O O O O O O O 2 2 2 2 2 2 O 2 O O O O O O O O O O O O O O O O O* O* O* 2 O O O O O 2 O O O O O O* 2 O O O O O O O O O O O O O O* 2 O [Legend] O: Register exists : No register exists Notes: 1. Not supported by TFP-144V and TLP-145V. 2. Valid only when the PORTS bit in the port control register 2 (PTCNT2) is 1. Rev. 1.00 Apr. 28, 2008 Page 143 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to J) DDR specifies the port input or output for each bit. The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are reserved. (1) Bit 7 6 5 4 3 2 1 0 PORTS = 0 Bit Name Pn7DDR Pn6DDR Pn5DDR Pn4DDR Pn3DDR Pn2DDR Pn1DDR Pn0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description The corresponding pins act as output ports when these bits are set to 1 and act as input ports when cleared to 0. Note: These bits cannot be set with bit manipulation instructions such as BSET and BCLR. (2) Bit 7 6 5 4 3 2 1 0 PORTS = 1 Bit Name Pn7DDR Pn6DDR Pn5DDR Pn4DDR Pn3DDR Pn2DDR Pn1DDR Pn0DDR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The corresponding pins act as output ports when these bits are set to 1 and act as input ports when cleared to 0. Rev. 1.00 Apr. 28, 2008 Page 144 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9) DR is a register that stores output data of the pins to be used as the general output port. Since the P96DR bit is determined by the state of the P96 pin, the initial value is undefined. The upper five bits in P5DR and the upper one bit in P8DR are reserved. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7DR Pn6DR Pn5DR Pn4DR Pn3DR Pn2DR Pn1DR Pn0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description PnDR stores output data for the pins that are used as the general output port. When the PORTS bit in PTCNT2 is 0, reading this register reads out the current settings of these bits for pins corresponding to PnDDR bits set to 1 and reads out the states of pins corresponding to PnDDR bits cleared to 0. 7.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J) PIN is an 8-bit read-only register that reflects the port pin state. A write to PIN is invalid. The upper five bits in P5PIN, the upper one bit in P8PIN, the upper three bits in PEPIN, and the upper two bits in PHPIN are reserved. Bits P1PIN to P9PIN are valid only when PORTS in PTCNT2 is 1. Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value Pn7PIN Pn6PIN Pn5PIN Pn4PIN Pn3PIN Pn2PIN Pn1PIN Pn0PIN * Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Description When this register is read, the pin states are returned. The initial values of these pins are determined in accordance with the states of pins Pn7 to Pn0. Rev. 1.00 Apr. 28, 2008 Page 145 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 9, B to D, F, H, and J) Pull-Up MOS Control Register (KMPCR) (Port 6) PCR is a register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in the input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 7.3 shows the input pull-up MOS state. The upper two bits in P9PCR and the upper two bits in PHPCR are reserved. PBPCR to PDPCR, PFPCR, and PHPCR are valid only when PORTS in PTCNT2 is 1. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7PCR Pn6PCR Pn5PCR Pn4PCR Pn3PCR Pn2PCR Pn1PCR Pn0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description For pins in the input state corresponding to bits in this register that have been set to 1, the input pullup MOSs are turned on. Rev. 1.00 Apr. 28, 2008 Page 146 of 994 REJ09B0452-0100 Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (1) * Port 1 to 3, 6, 9, and J Port Port 1 Pin State Port output Port input Port 2 Port output Port input Port 3 Port output Port input Port 6 (KMPCR) Port 9 Port output Port input Port output Port input Port J Port output Port input Off Off Off On/Off Off Off On/Off Off Off On/Off Off Off On/Off Off Off On/Off Reset Software Standby Mode Other Operation Off On/Off [Legend] Off: The input pull-up MOS is always off. On/Off: On when PnDDR = 0 and PnPCR = 1; otherwise off. Rev. 1.00 Apr. 28, 2008 Page 147 of 994 REJ09B0452-0100 Section 7 I/O Ports Table 7.3 Input Pull-Up MOS State (2) * Port B to D, F, and H Port Port B Pin State Port output Port input Port C Port output Port input Port D Port output Port input Port F Port output Port input Port H Port output Port input Off Off Off On/Off Off Off On/Off Off Off On/Off Off Off On/Off Reset Software Standby Mode Other Operation Off On/Off [Legend] Off: The input pull-up MOS is always off. On/Off: On when the pin is in the input state, PnDDR = 0, and PnODR = 1; otherwise off (when PORTS = 0). On when the pin is in the input state, PnDDR = 0, and PnPCR = 1; otherwise off (when PORTS = 1). Rev. 1.00 Apr. 28, 2008 Page 148 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.5 Output Data Register (PnODR) (n = A to D and F to J) ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7ODR Pn6ODR Pn5ODR Pn4ODR Pn3ODR Pn2ODR Pn1ODR Pn0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description ODR stores the output data for the pins that are used as the general output port. 7.1.6 Noise Canceler Enable Register (PnNCE) (n = 6, C, and G) NCE enables or disables the noise cancel circuit at port n pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7NCE Pn6NCE Pn5NCE Pn4NCE Pn3NCE Pn2NCE Pn1NCE Pn0NCE Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Noise cancel circuit is enabled when a bit in this register is set to 1, and the pin setting state is fetched in P6DR or PnPIN in the sampling cycle set by the PnNCCS. Rev. 1.00 Apr. 28, 2008 Page 149 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.7 Noise Canceler Decision Control Register (PnNCMC) (n = 6, C, and G) NCMC controls whether 1 or 0 is expected for the input signal to port n pins in bit units. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7NCMC Pn6NCMC Pn5NCMC Pn4NCMC Pn3NCMC Pn2NCMC Pn1NCMC Pn0NCMC Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 expected: 1 is stored in the port data register when 1 is input stably. 0 expected: 0 is stored in the port data register when 0 is input stably. 7.1.8 Noise Cancel Cycle Setting Register (PnNCCS) (n = 6, C, and G) NCCS controls the sampling cycles of the noise canceler. Bit 7 to 3 Bit Name Initial Value Undefined R/W R/W Description Reserved The read value is undefined. The write value should always be 0. 2 1 0 PnNCCK2 PnNCCK1 PnNCCK0 0 0 0 R/W R/W R/W These bits set the sampling cycles of the noise canceler. When is 10 MHz 000: 001: 010: 011: 100: 101: 110: 111: 0.80 s 12.8 s 3.3 ms 6.6 ms 13.1 ms 26.2 ms 52.4 ms 104.9 ms /2 /32 /8192 /16384 /32768 /65536 /131072 /262144 Rev. 1.00 Apr. 28, 2008 Page 150 of 994 REJ09B0452-0100 Section 7 I/O Ports /2, /32, /8192, /16384, /32768, /65536, /131072, /262144 Sampling clock selection t Matching detection circuit Pin input Latch Latch Latch Latch Port data register Interrupt input Keyboard input t Sampling clock Figure 7.1 Noise Cancel Circuit P6n input PCn input PGn input 1 expected P6n input PCn input PGn input 0 expected P6n input PCn input PGn input (n = 7 to 0) Figure 7.2 Schematic View of Noise Cancel Operation Rev. 1.00 Apr. 28, 2008 Page 151 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.9 Port Nch-OD Control Register (PnNOCR) (n = C, D, and F to J) The individual bits of NOCR specify output driver type for the pins of port n that is specified as output. The upper two bits in PHNOCR are reserved. Bit 7 6 5 4 3 2 1 0 Bit Name Pn7NOCR Pn6NOCR Pn5NOCR Pn4NOCR Pn3NOCR Pn2NOCR Pn1NOCR Pn0NOCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0: CMOS (Ports G and I are NMOS push-pull output) (High level driver is enabled) 1: N channel open-drain (High level driver is disabled) Rev. 1.00 Apr. 28, 2008 Page 152 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.1.10 Pin Functions The pin function is switched according to the setting of the PORTS bit in PTCNT2. (Ports B to D, F, and H) (1) DDR NOCR ODR N-ch. driver P-ch. driver Input pull-up MOS Pin function Off Input pin 0 Off Off On PORTS = 0 0 1 0 On Off 0 1 Off On Off Output pin 0 On Off 1 1 1 Off (2) DDR PORTS = 1 0 1 0 0 1 1 NOCR ODR PCR N-ch. Driver P-ch. Driver Input pull-up MOS Pin Function Off 0 1 0 1 Off Off On Input pin On Off Off On Off Output pin On Off Off Rev. 1.00 Apr. 28, 2008 Page 153 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 7.4 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. 7.2.1 (1) Port 1 P17 to P10 The pin function is switched as shown below according to the P1nDDR bit setting. Setting I/O Port Module Name I/O port Pin Function P1n output P1n input (initial setting) P1nDDR 1 0 (n = 7 to 0) 7.2.2 (1) Port 2 P27 to P20 The pin function is switched as shown below according to the P2nDDR bit setting. Setting I/O Port Module Name I/O port Pin Function P2n output P2n input (initial setting) P2nDDR 1 0 (n = 7 to 0) Rev. 1.00 Apr. 28, 2008 Page 154 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.3 (1) Port 3 P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 and LPC3E to LPC1E bits in HICR0 of the LPC, and the P3nDDR bit. LPCENABLE in the following table is expressed by the following logical expression. LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E Setting Module Name LPC I/O port Logical expression Pin Function LPC output P3n output P3n input (initial setting) LPCENABLE 1 0 0 I/O Port P3nDDR 1 0 (n = 7 to 0) 7.2.4 (1) Port 4 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 The pin function is switched as shown below according to the combination of the PWMX and PWMU and the P47DDR bit. Setting Module Name PWMX PWMU I/O port PWMX Pin Function PWX1 output PWMU5B output P47 output P47 input (initial setting) PWX1_OE 1 0 0 0 PWMU PWMU5B_OE 1 0 I/O Port P47DDR 1 1 0 Rev. 1.00 Apr. 28, 2008 Page 155 of 994 REJ09B0452-0100 Section 7 I/O Ports (2) P46/PWX0/PWMU4B/TCMCYI3 The pin function is switched as shown below according to the combination of the PWMX and PWMU and the P46DDR bit. Setting Module Name PWMX PWMU I/O port PWMX Pin Function PWX0 output PWMU4B output P46 output P46 input (initial setting) PWX0_OE 1 0 0 0 PWMU PWMU4B_OE 1 0 I/O Port P46DDR 1 1 0 (3) P45/PWMU3B/TCMCKI2/TCMMCI2 The pin function is switched as shown below according to the combination of the PWMX and the P45DDR bit. Setting Module Name PWMU I/O port PWMU Pin Function PWMU3B output P45 output P45 input (initial setting) PWMU3B_OE 1 0 I/O Port P45DDR 1 1 0 Rev. 1.00 Apr. 28, 2008 Page 156 of 994 REJ09B0452-0100 Section 7 I/O Ports (4) P44/TMO1/PWMU2B/TCMCYI2 The pin function is switched as shown below according to the combination of the TMR and PWMU and the P44DDR bit. Setting Module Name TMR PWMU I/O port TMR Pin Function TMO1 output PWMU2B output P44 output P44 input (initial setting) TMO1_OE 1 0 0 0 PWMU PWMU2B_OE 1 0 I/O Port P44DDR 1 1 0 (5) P43/TMI1/SCK2/TCMCKI1/TCMMCI1 The pin function is switched as shown below according to the combination of the SCI and the P43DDR bit. Setting Module Name SCI I/O port SCI Pin Function SCK2_OE I/O Port P43DDR 1 0 SCK2 input/output 1 P43 output P43 input (initial setting) 0 0 Rev. 1.00 Apr. 28, 2008 Page 157 of 994 REJ09B0452-0100 Section 7 I/O Ports (6) P42/SDA1/TCMCYI1 The pin function is switched as shown below according to the combination of the IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P42DDR bit. When the TCMIPE bit in TCMIER_1 of TCM_1 is set to 1, TCMCYI1 functions as an input pin. Setting Module Name IIC I/O port IIC_1 Pin Function SDA1 output P42 output P42 input (initial setting) SDA1_OE 1 0 0 I/O Port P42DDR 1 0 Note: To use this pin as SDA1, clear the IIC1AS and IIC1BS bits in PTCNT1 to 0. The output format for SDA1 is NMOS output only and direct bus drive is possible. When this pin is used as the P42 output pin, the output format is NMOS push-pull. (7) P41/TMO0/RxD2/TCMCKI0/TCMMCI0 The pin function is switched as shown below according to the combination of the TMR and the P41DDR bit. Setting Module Name TMR SCI I/O port TMR Pin Function TMO0 output RxD2 input P41 output P41 input (initial setting) TMO0_OE 1 0 0 0 SCI RE 0 1 0 0 I/O Port P41DDR 1 0 Note: To use this pin as TMO0 output, clear the RE bit in SCR of the SCI2 to 0. Rev. 1.00 Apr. 28, 2008 Page 158 of 994 REJ09B0452-0100 Section 7 I/O Ports (8) P40/TMI0/TxD2/TCMCYI0 The pin function is switched as shown below according to the combination of the TMR and the SCI and the P40DDR bit. Setting Module Name SCI I/O port SCI Pin Function TxD2 output P40 output P40 input (initial setting) TxD2_OE 1 0 0 I/O Port P40DDR 1 0 7.2.5 (1) Port 5 P52/SCL0 The pin function is switched as shown below according to the combination of the IIC0AS and IIC0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P52DDR bit. Setting Module Name IIC I/O port IIC_0 Pin Function SCL0 output P52 output P52 input (initial setting) SCL0_OE 1 0 0 I/O Port P52DDR 1 0 Note: To use this pin as SCL0, clear the IIC0AS and IIC0BS bits in PTCNT1 to 0. The output format for SCL0 is NMOS output only and direct bus drive is possible. When this pin is used as the P52 output pin, the output format is NMOS push-pull. Rev. 1.00 Apr. 28, 2008 Page 159 of 994 REJ09B0452-0100 Section 7 I/O Ports (2) P51/FRxD The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the SCIF and the SCIFE bit in HICR5 of the SCIF, and the P51DDR bit. SCIFENABLE = 1: SCIFOE1 + SCIFE Setting Module Name SCIF I/O port Logical Expression Pin Function FRxD input P51 output P51 input (initial setting) SCIFENABLE 1 0 0 I/O Port P51DDR 1 0 (3) P50/FTxD The pin function is switched as shown below according to the SCIFOE1 bit in SCIFCR of the SCIF, the SCIFE bit in HICR5, and the P50DDR bit. SCIFENABLE = 1: SCIFOE1 + SCIFE Setting Module Name SCIF I/O port Logical Expression Pin Function FTxD output P50 output P50 input (initial setting) SCIFENABLE 1 0 0 I/O Port P50DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 160 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.6 (1) Port 6 P67/KIN7/IRQ7 When the KMIM7 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN7 input pin. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin. The pin function is switched as shown below according to the state of the P67DDR bit. Setting Module Name I/O port I/O Port Pin Function P67 output P67 input (initial setting) P67DDR 1 0 (2) P66/KIN6/IRQ6 When the KMIM6 bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KIN6 input pin. When the EIVS bit in SYSCR3 is cleared to 0 and the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ6 input pin. The pin function is switched as shown below according to the state of the P66DDR bit. Setting Module Name I/O port I/O Port Pin Function P66 output P66 input (initial setting) P66DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 161 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) P65/KIN5, P64/KIN4, P63/KIN3, P62/KIN2, P61/KIN1, P60/KIN0 When the KMIMn bit in KMIMR of the interrupt controller is cleared to 0, this pin can be used as the KINn input pin. The pin function is switched as shown below according to the state of the P6nDDR bit. Setting Module Name I/O port I/O Port Pin Function P6n output P6n input (initial setting) P6nDDR 1 0 (n = 5 to 0) 7.2.7 (1) Port 7 P77/AN7, P76/AN6, P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0 Module Name A/D converter Pin Function ANn/P7n input (n = 7 to 0) Rev. 1.00 Apr. 28, 2008 Page 162 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.8 (1) Port 8 P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, CKE0 and CKE1 bits in SCR, IIC1AS and IIC1BS bits in PTCNT1, ICE bit in ICCR of IIC_1, and the P86DDR bit. When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin. Setting Module Name SCI IIC I/O port SCI Pin Function SCK1_OE IIC SCL1_OE 0 1 0 0 I/O Port P86DDR 1 0 SCK1 input/output 1 SCL1 input/output 0 P86 output P86 input (initial setting) 0 0 Note: To use this pin as SCL1 input/output, be sure that SCK1_OE is 0. To use this pin as SCL1, the IIC1AS and IIC1BS bits in PTCNT1 must be cleared to 0. The output format for SCL1 is NMOS output only and direct bus drive is possible. When this pin is used as the P86 output pin or SCK1 output pin, the output format is NMOS push-pull. (2) P85/IRQ4/RxD1 The pin function is switched as shown below according to the state of the P85DDR bit. Setting Module Name SCI I/O port SCI Pin Function RxD1 input P85 output P85 input (initial setting) RE 1 0 0 I/O Port P85DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 163 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the register setting of the SCI and the P84DDR bit. Setting Module Name SCI I/O port SCI Pin Function TxD1 output P84 output P84 input (initial setting) TxD1_OE 1 0 0 I/O Port P84DDR 1 0 (4) P83/LPCPD The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E bits in HICR0, and the P83DDR bit. LPCENABLE in the following table is expressed by the following logical expression. LPCENABLE = 1 : FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E Setting Module Name LPC I/O port Logical Expression Pin Function LPCPD input P83 output P83 input (initial setting) LPCENABLE 1 0 0 I/O Port P83DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 164 of 994 REJ09B0452-0100 Section 7 I/O Ports (5) P82/CLKRUN The pin function is switched as shown below according to the combination of the FSILIE bit in SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E bits in HICR0, and the P82DDR bit. LPCENABLE in the following table is expressed by the following logical expression. LPCENABLE = 1 : FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E Setting Module Name LPC I/O port Logical Expression Pin Function CLKRUN output P82 output P82 input (initial setting) LPCENABLE 1 0 0 I/O Port P82DDR 1 0 (6) P81/GA20 The pin function is switched as shown below according to the combination of the register setting of the LPC and the P81DDR bit. Setting Module Name LPC I/O port LPC Pin Function GA20 output P81 output P81 input (initial setting) GA20_OE 1 0 0 I/O Port P81DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 165 of 994 REJ09B0452-0100 Section 7 I/O Ports (7) P80/PME The pin function is switched as shown below according to the combination of the register setting of the LPC and the P80DDR bit. Setting Module Name LPC I/O port LPC Pin Function PME output P80 output P80 input (initial setting) PME_OE 1 0 0 I/O Port P80DDR 1 0 7.2.9 (1) Port 9 P97/IRQ15/SDA0 The pin function is switched as shown below according to the combination of the IIC0AS and IIC0BS bits in PTCNT1, ICE bit in ICCR of IIC_0, and the P97DDR bit. When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ15 input pin. Setting Module Name IIC I/O port IIC_0 Pin Function SDA0_OE I/O Port P97DDR 1 0 SDA0 input/output 1 P97 output P97 input (initial setting) 0 0 Note: To use this pin as SDA0, clear the IIC0AS and IIC0BS bits in PTCNT1 to 0. The output format for SDA0 is NMOS output only and direct bus drive is possible. When this pin is used as the P97 output pin, the output format is NMOS push-pull. Rev. 1.00 Apr. 28, 2008 Page 166 of 994 REJ09B0452-0100 Section 7 I/O Ports (2) P96//EXCL The pin function is switched as shown below according to the combination of the register settings of the EXCLS bit in PTCNT0, EXCLE bit in LPWRCR, and the P96DDR bit. Setting Module Name Clock I/O port I/O Port Pin Function output P96 input (initial setting) P96DDR 1 0 (3) P95/IRQ14, P94/IRQ13, P93/IRQ12, P92/IRQ0, P91/IRQ1, P90/IRQ2 The pin function is switched as shown below according to the state of the P9nDDR bit. When the ISSm bit in ISSR (ISSR16) is cleared to 0 and the IRQmE bit in IER (IER16) of the interrupt controller is set to 1, this pin can be used as the IRQm input pin. Setting Module Name I/O port I/O Port Pin Function P9n output P9n input (initial setting) P9nDDR 1 0 (n = 5 to 0) (m = 14 to 12, 2 to 0) Rev. 1.00 Apr. 28, 2008 Page 167 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.10 (1) Port A PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC, PA3/KIN11/PS2AD, PA2/KIN10/PS2AC, PA1/KIN9/PS2DD, PA0/KIN8/PS2DC The pin function is switched according to the combination of the register setting of PS2 and the PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KINm input pin. Setting Module Name PS2 I/O port PS2 Pin Function PS2 input/output PAn output PAn input (initial setting) PS2_OE 1 0 0 I/O Port PAnDDR 1 0 (n = 7 to 0, m = 15 to 8) Note: When the KBIOE bit is set to 1, this pin functions as an NMOS open-drain output, and direct bus drive is possible. When the IICS bit in STCR is set to 1, the output format for PA7 to PA4 is NMOS opendrain, and direct bus drive is possible. Rev. 1.00 Apr. 28, 2008 Page 168 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.11 (1) Port B PB7/RTS/FSISS The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1 of FSI and the PB7DDR bit. Setting Module Name FSI SCIF I/O port FSI Pin Function FSISS output RTS output PB7 output PB7 input (initial setting) FSISS_OE 1 0 0 0 SCIF RTS_OE 1 0 0 I/O Port PB7DDR 1 0 (2) PB6/CTS/FSICK The pin function is switched as shown below according to the FSIE bit in FSICR1 of FSI and the PB6DDR bit. Setting Module Name FSI I/O port FSI Pin Function FSICK output PB6 output PB6 input (initial setting) FSICK_OE 1 0 0 I/O Port PB6DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 169 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) PB5/DTR/FSIDI The pin function is switched as shown below according to the combination of the SCIFE bit in HICR5 of LPC, the FSIE bit in FSICR1of FSI and the PB5DDR bit. Setting Module Name FSI SCIF I/O port FSI Pin Function FSIDI input DTR output PB5 output PB5 input (initial setting) FSIDI 1 0 0 0 SCIF DTR_OE 1 0 0 I/O Port PB5DDR 1 0 (4) PB4/DSR/FSIDO The pin function is switched as shown below according to the state of the FSIE bit in FSICR1 of FSI and the PB4DDR bit. Setting Module Name FSI I/O port FSI Pin Function FSIDO output PB4 output PB4 input (initial setting) FSIDO_OE 1 0 0 I/O Port PB4DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 170 of 994 REJ09B0452-0100 Section 7 I/O Ports (5) PB3/DCD/PWMU1B The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PB3DDR bit. Setting Module Name PWMU I/O port PWMU Pin Function PWMU1B output PB3 output PB3 input (initial setting) PWMU1B_OE 1 0 I/O Port PB3DDR 1 1 0 (6) PB2/RI/PWMU0B The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PB2DDR bit. Setting Module Name PWMU I/O port PWMU Pin Function PWMU0B output PB2 output PB2 input (initial setting) PWMU0B_OE 1 0 I/O Port PB2DDR 1 1 0 Rev. 1.00 Apr. 28, 2008 Page 171 of 994 REJ09B0452-0100 Section 7 I/O Ports (7) PB1/LSCI The pin function is switched as shown below according to the combination of the register setting of the LPC and the PB1DDR bit. Setting Module Name LPC I/O port LPC Pin Function LSCI output PB1 output PB1 input (initial setting) LSCI_OE 1 0 0 I/O Port PB1DDR 1 0 (8) PB0/LSMI The pin function is switched as shown below according to the combination of the register setting of the LPC and the PB0DDR bit. Setting Module Name LPC I/O port LPC Pin Function LSMI output PB0 output PB0 input (initial setting) LSMI_OE 1 0 0 I/O Port PB0DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 172 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.12 (1) Port C PC7/WUE15/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC7DDR bit. When the WUEMR15 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE15 input pin. This pin functions as the TCLKD input when TPSC2 to TPSC0 in TCR_0 is B'111. Also, when channel 2 is set to phase counting mode, this pin functions as the TCLKD input. This pin functions as TIOCB2 input when TPU channel 2 timer operating mode is set to normal operation or phase counting mode and IOB3 in TIOR_2 is set to 1. Setting Module Name TPU I/O port TPU Pin Function TIOCB2 output PC7 output PC7 input (initial setting) TIOCB2_OE 1 0 0 I/O Port PC7DDR 1 0 (2) PC6/WUE14/TIOCA2 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC6DDR bit. When the WUEMR14 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin. This pin functions as TIOCA2 input when TPU channel 2 timer operating mode is set to normal operation or phase counting mode and IOA3 in TIOR_2 is set to 1. Setting Module Name TPU I/O port TPU Pin Function TIOCA2 output PC6 output PC6 input (initial setting) TIOCA2_OE 1 0 0 I/O Port PC6DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 173 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) PC5/WUE13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC5DDR bit. When the WUEMR13 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE13 input pin. This pin functions as TCLKC input when TPSC2 to TPSC0 in TCR_0 or TCR_2 is set to B'110 or when channel 2 is set to phase counting mode. This pin functions as TIOCB1 input when TPU channel 1 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIOR_1 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCB1 output PC5 output PC5 input (initial setting) TIOCB1_OE 1 0 0 I/O Port PC5DDR 1 0 (4) PC4/WUE12/TIOCA1 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC4DDR bit. When the WUEMR12 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE12 input pin. This pin functions as TIOCA1 input when TPU channel 1 timer operating mode is set to normal operation or phase counting mode and IOA3 to IOA0 in TIOR_1 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCA1 output PC4 output PC4 input (initial setting) TIOCA1_OE 1 0 0 I/O Port PC4DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 174 of 994 REJ09B0452-0100 Section 7 I/O Ports (5) PC3/WUE11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC3DDR bit. When the WUEMR11 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE11 input pin. This pin functions as TCLKB input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to B'101 or when channel 1 is set to phase counting mode. This pin functions as TIOCD1 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOD3 to IOD0 in TIOR_0 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCD0 output PC3 output PC3 input (initial setting) TIOCD0_OE 1 0 0 I/O Port PC3DDR 1 0 (6) PC2/WUE10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC2DDR bit. When the WUEMR10 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE10 input pin. This pin functions as TCLKA input when TPSC2 to TPSC0 in any of TCR_0 to TCR_2 are set to B'100 or when channel 1 is set to phase counting mode. This pin functions as TIOCC0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOC3 to IOC0 in TIOR_0 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCC0 output PC2 output PC2 input (initial setting) TIOCC0_OE 1 0 0 I/O Port PC2DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 175 of 994 REJ09B0452-0100 Section 7 I/O Ports (7) PC1/WUE9/TIOCB0 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC1DDR bit. When the WUEMR9 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE9 input pin. This pin functions as TIOCB0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOB3 to IOB0 in TIORH_0 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCB0 output PC1 output PC1 input (initial setting) TIOCB0_OE 1 0 0 I/O Port PC1DDR 1 0 (8) PC0/WUE8/TIOCA0 The pin function is switched as shown below according to the combination of the register setting of the TPU and the PC0DDR bit. When the WUEMR8 bit in WUEMR of the interrupt controller is cleared to 0, this pin can be used as the WUE8 input pin. This pin functions as TIOCA0 input when TPU channel 0 timer operating mode is set to normal operation or phase counting mode and IOA3 to IOA0 in TIORH_0 are set to B'10xx. (x: Don't care.) Setting Module Name TPU I/O port TPU Pin Function TIOCA0 output PC0 output PC0 input (initial setting) TIOCA0_OE 1 0 0 I/O Port PC0DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 176 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.13 (1) Port D PD7/AN15, PD6/AN14, PD5/AN13, PD4/AN12, PD3/AN11, PD2/AN10, PD1/AN9, PD0/AN8 The pin function is switched as shown below according to the state of the PDnDDR bit. When this pin is used as an analog input pin, do not set the pin as output. Setting Module Name I/O port I/O Port Pin Function PDn output PDn input (initial setting) PDnDDR 1 0 (n = 7 to 0) 7.2.14 (1) Port E PE4/ETMS, PE3/ETDO, PE2/ETDI, PE1/ETCK The pin function is switched as shown below according to the operating mode. Setting Module Name Operating mode On-Chip Emulation Mode Pin Function Emulator Input/Output Single-Chip Mode PEn input 1 On-chip emulation 1 mode Single-chip mode 0 Note: These pins are not supported by the system development tool (emulator). Rev. 1.00 Apr. 28, 2008 Page 177 of 994 REJ09B0452-0100 Section 7 I/O Ports (2) PE0/ExEXCL The pin function is switched as shown below according to the combination of the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR. When the EXCLS bit in PTCNT0 and EXCLE bit in LPWRCR are set to 1, this pin can be used as the ExEXCL input pin. Setting Module Name I/O port I/O Port Pin Function PE0 input (initial setting) ExEXCL 0 7.2.15 (1) Port F PF7/PWMU5, APF6/PWMU4A, PF5/PWMU3A, PF4/PWMU2A The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PFnDDR bit. Setting Module Name PWMU I/O port PWMU Pin Function PWMUmA_OE I/O Port PFnDDR 1 1 0 (n = 5 to 2, m = 7 to 4) PWMUmA output 1 PFn output PFn input (initial setting) 0 Rev. 1.00 Apr. 28, 2008 Page 178 of 994 REJ09B0452-0100 Section 7 I/O Ports (2) PF3/TMOX/IRQ11/TDPCKI0/TDPMCI0 The pin function is switched as shown below according to the combination of the register setting of the TMR and the PF3DDR bit. When the PMMS bit in TDPCR2_0 of TDP0 is set to 1, this pin can be used as the TDPMCI0 input pin. When the external clock is selected by the CKS3 to CKS0 bits in TDPCR1_0 of TDP0, this pin is used as the TDPCKI0 input pin. Do not set input of TDPCKI0 and TDPMCI0 at the same time. When the ISS11 bit in ISSR16 is cleared to 0 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ11 input pin. Setting Module Name TMR I/O port TMR Pin Function TMOX output PF3 output PF3 input (initial setting) TMOX_OE 1 0 0 I/O Port PF3DDR 1 0 (3) PF2/TMOY/IRQ10/TDPCYI0 The pin function is switched as shown below according to the combination of the register setting of the TMR and the PF2DDR bit. When the TDPIPE bit in TDPIER_0 of TDP0 is set to 1, this pin can be used as the TDPCYI0 input pin. When the ISS10 bit in ISSR16 is cleared to 0 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ10 input pin. Setting Module Name TMR I/O port TMR Pin Function TMOY output PF2 output PF2 input (initial setting) TMOY_OE 1 0 0 I/O Port PF2DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 179 of 994 REJ09B0452-0100 Section 7 I/O Ports (4) PF1/IRQ9/PWMU1A The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PF1DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin. Setting Module Name PWMU I/O port PWMU Pin Function PWMU1A output PF1 output PF1 input (initial setting) PWMU1A_OE 1 0 I/O Port PF1DDR 1 1 0 (5) PF0/IRQ8/PWMU0A The pin function is switched as shown below according to the combination of the register setting of the PWMU and the PF1DDR bit. When the ISS8 bit in ISSR16 is cleared to 0 and the IRQ8E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ8 input pin. Setting Module Name PWMU I/O port PWMU Pin Function PWMU0A output PF0 output PF0 input (initial setting) PWMU0A_OE 1 0 I/O Port PF0DDR 1 1 0 Rev. 1.00 Apr. 28, 2008 Page 180 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.16 (1) Port G PG7/ExSCLB/ExIRQ15 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG7DDR bit. When the ISS15 bit in ISSR16 is set to 1 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin. Setting Module Name PTCNT1 I/O port PTCNT1 Pin Function ExSCLB input/output PG7 output PG7 input (initial setting) ExSCLB_OE 1 0 0 I/O Port PG7DDR 1 0 Note: The output format for ExSCLB is NMOS output only, and direct bus drive is possible. When this pin is used as the PG7 output pin, the output format is NMOS push-pull. (2) PG6/ExSDAB/ExIRQ14 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG6DDR bit. When the ISS14 bit in ISSR16 is set to 1 and the IRQ14E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ14 input pin. Setting Module Name PTCNT1 I/O port PTCNT1 Pin Function ExSDAB input/output PG6 output PG6 input (initial setting) ExSDAB_OE 1 0 0 I/O Port PG6DDR 1 0 Note: The output format for ExSDAB is NMOS output only, and direct bus drive is possible. When this pin is used as the PG6 output pin, the output format is NMOS push-pull. Rev. 1.00 Apr. 28, 2008 Page 181 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) PG5/ExSCLA/ExIRQ13 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin. Setting Module Name PTCNT1 I/O port PTCNT1 Pin Function ExSCLA input/output PG5 output PG5 input (initial setting) ExSCLA_OE 1 0 0 I/O Port PG5DDR 1 0 Note: The output format for ExSCLA is NMOS output only, and direct bus drive is possible. When this pin is used as the PG5 output pin, the output format is NMOS push-pull. (4) PG4/ExSDAA/ExIRQ12 The pin function is switched as shown below according to the combination of the register setting of PTCNT1 and the PG4DDR bit. When the ISS12 bit in ISSR16 is set to 1 and the IRQ12E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin. Setting Module Name PTCNT1 I/O port PTCNT1 Pin Function ExSDAA input/output PG4 output PG4 input (initial setting) ExSDAA_OE 1 0 0 I/O Port PG4DDR 1 0 Note: The output format for ExSDAA is NMOS output only, and direct bus drive is possible. When this pin is used as the PG4 output pin, the output format is NMOS push-pull. Rev. 1.00 Apr. 28, 2008 Page 182 of 994 REJ09B0452-0100 Section 7 I/O Ports (5) PG3/SCL2/ExIRQ11 The pin function is switched as shown below according to the combination of the register setting of the IIC and the PG3DDR bit. When the ISS11 bit in ISSR16 is set to 1 and the IRQ11E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin. Setting Module Name IIC I/O port IIC Pin Function SCL2_OE I/O Port PG3DDR 1 0 SCL2 input/output 1 PG3 output PG3 input (initial setting) 0 0 Note: The output format for SCL2 is NMOS output only, and direct bus drive is possible. When this pin is used as the PG3 output pin, the output format is NMOS push-pull. (6) PG2/SDA2/ExIRQ10 The pin function is switched as shown below according to the combination of the register setting of the IIC and the PG2DDR bit. When the ISS10 bit in ISSR16 is set to 1 and the IRQ10E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ10 input pin. Setting Module Name IIC I/O port IIC Pin Function SDA2_OE I/O Port PG2DDR 1 0 SDA2 input/output 1 PG2 output PG2 input (initial setting) 0 0 Note: The output format for SDA2 is NMOS output only, and direct bus drive is possible. When this pin is used as the PG2 output pin, the output format is NMOS push-pull. Rev. 1.00 Apr. 28, 2008 Page 183 of 994 REJ09B0452-0100 Section 7 I/O Ports (7) PG1/ExIRQ9/TMIY/TDPCKI1/TDPMCI1 The pin function is switched as shown below according to the state of the PG1DDR bit. When the PMMS bit in TDPCR2_1 of the TDP is set to 1, this pin is used as the TDPMCI1 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_1 of the TDP, this pin is used as the TDPCKI1 input pin. Do not set input of TDPCKI1 and TDPMCI1 at the same time. When the ISS9 bit in ISSR16 is set to 1 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ9 input pin. Setting Module Name I/O port I/O Port Pin Function PG1 output PG1 input (initial setting) PG1DDR 1 0 (8) PG0/ExIRQ8/TMIX/TDPCYI1 The pin function is switched as shown below according to the state of the PG0DDR bit. When the TDPIPE bit in TDPIER_1 of the TDP is set to 1, this pin is used as the TDPCYI1 input pin. When the ISS8 bit in ISSR16 is set to 1 and the IRQ8E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ8 input pin. Setting Module Name I/O port I/O Port Pin Function PG0 output PG0 input (initial setting) PG0DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 184 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.17 (1) Port H PH5, PH4, PH3 The pin function is switched as shown below according to the state of the PHnDDR bit. Setting Module Name I/O port I/O Port Pin Function PHn output PHn input (initial setting) PHnDDR 1 0 (n = 5 to 3) (2) PH2/CIRI The pin function is switched as shown below according to the combination of the register setting of CIR and the PH2DDR bit. Setting Module Name CIR I/O port CIR Pin Function CIRI input PH2 output PH2 input (initial setting) CIRI 1 0 0 I/O Port PH2DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 185 of 994 REJ09B0452-0100 Section 7 I/O Ports (3) PH1/ExIRQ7/TDPCKI2/TDPMCI2 The pin function is switched as shown below according to the state of the PH1DDR bit. When the PMMS bit in TDPCR2_2 of the TDP is set to 1, this pin is used as the TDPMCI2 input pin. When the external clock is selected by the CKS2 to CKS0 bits in TDPCR1_2 of the TDP, this pin is used as the TDPCKI2 input pin. Do not set input of TDPCKI2 and TDPMCI2 at the same time. When the ISS7 bit in ISSR is set to 1 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the ExIRQ7 input pin. Setting Module Name I/O port I/O Port Pin Function PH1 output PH1 input (initial setting) PH1DDR 1 0 (4) PH0/ExIRQ6/TDPCYI2 The pin function is switched as shown below according to the state of the PH0DDR bit. When the TDPIPE bit in TDPIER_2 of the TDP is set to 1, this pin is used as the TDPCYI2 input pin. When the EIVS bit in SYSCR3 is set to 1 and the IRQ6E bit in IER of the interrupt controller is set to 1, this pin can be used as the ExIRQ6 input pin. Setting Module Name I/O port I/O Port Pin Function PH0 output PH0 input (initial setting) PH0DDR 1 0 Rev. 1.00 Apr. 28, 2008 Page 186 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.2.18 (1) Port I PI7, PI6, PI5, PI4, PI3, PI2, PI1, PI0 The pin function is switched as shown below according to the state of the PInDDR bit. Setting Module Name I/O port I/O Port Pin Function PIn output PIn input (initial setting) PInDDR 1 0 (n = 7 to 0) Note: The output format for PIn is NMOS push-pull. 7.2.19 (1) Port J PJ7, PJ6, PJ5, PJ4, PJ3, PJ2, PJ1, PJ0 The pin function is switched as shown below according to the state of the PJnDDR bit. Setting Module Name I/O port I/O Port Pin Function PJn output PJn input (initial setting) PJnDDR 1 0 (n = 7 to 0) Rev. 1.00 Apr. 28, 2008 Page 187 of 994 REJ09B0452-0100 Section 7 I/O Ports Table 7.4 Available Output Signals and Settings in Each Port Output Specification Signal Name Output Signal Name P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 SERIRQ P36 P35 P34 LAD3 LAD2 LAD1 LAD0 FSI.SLCR.FSILIE, LPC.HICR5.SCIFE, HICR4.LPC4E, HICR0.LPC[3E:1E] LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E Signal Selection Register Settings Port P1 7 6 5 4 3 2 1 0 P2 7 6 5 4 3 2 1 0 P3 7 6 5 4 3 2 1 0 Internal Module Settings P17_OE P16_OE P15_OE P14_OE P13_OE P12_OE P11_OE P10_OE P27_OE P26_OE P25_OE P24_OE P23_OE P22_OE P21_OE P20_OE SERIRQ_OE P36_OE P35_OE P34_OE LAD3_OE LAD2_OE LAD1_OE LAD0_OE Rev. 1.00 Apr. 28, 2008 Page 188 of 994 REJ09B0452-0100 Section 7 I/O Ports Port P4 7 Output Specification Signal Name PWX1_OE PWMU5B_OE 6 PWX0_OE PWMU4B_OE 5 4 PWMU3B_OE TMO1_OE PWMU2B_OE 3 2 SCK2_OE SDA1_OE Output Signal Name PWX1 PWMU5B PWX0 PWMU4B PWMU3B TMO1 PWMU2B SCK2 SDA1 Signal Selection Register Settings Internal Module Settings PWMX.DACR.OEB = 1 PWMU_B.PWMCONB.PWM5E = 1 PWMX.DACR.OEA = 1 PWMU_B.PWMCONB.PWM4E = 1 PWMU_B.PWMCONB.PWM3E = 1 Except TMR_1.TCSR.OS[3:0] = 0000 PWMU_B.PWMCONB.PWM2E = 1 SCI_2.SCR.CKE[1:0] = 01/10/11 + SMR.C/A =1 PTCNT1.IIC1AS PTCNT1.IIC1BS ICE*IIC1AS*IIC1BS = 1 1 0 P5 2 TMO0_OE TxD2_OE SCL0_OE TMO0 TxD2 SCL0 PTCNT1.IIC1AS PTCNT1.IIC1BS Except TMR_0.TCSR.OS[3:0] = 0000 SCI_2.SCR.TE = 1 ICE*IIC0AS*IIC0BS = 1 1 0 P51_OE FTxD_OE P51 FTxD SCIF.SCIFCR.SCIFOE1, LPC.HICR5.SCIFE SCIFENABLE = 1: SCIFOE1 + SCIFE P6 7 6 5 4 3 2 1 0 P67_OE P66_OE P65_OE P64_OE P63_OE P62_OE P61_OE P60_OE P67 P66 P65 P64 P63 P62 P61 P60 Rev. 1.00 Apr. 28, 2008 Page 189 of 994 REJ09B0452-0100 Section 7 I/O Ports Port P8 6 Output Specification Signal Name SCK1_OE SCL1_OE Output Signal Name SCK1 SCL1 Signal Selection Register Settings Internal Module Settings SCI_1.SMR.C/A = 1 or SCI_1.SMR.C/A = 0, SCR.CKE[1:0] = 01/10/11 PTCNT1.IIC1AS PTCNT1.IIC1BS ICE*IIC1AS*IIC1BS = 1 5 4 3 2 P85_OE TxD1_OE P83_OE CLKRUN_OE P85 TxD1 P83 CLKRUN FSI.SLCR.FSILIE, LPC.HICR5.SCIFE, HICR4.LPC4E, HICR0.LPC[3E:1E] LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E SCI_1.SCR.TE = 1 1 0 P9 7 GA20_OE PME_OE SDA0_OE GA20 PME SDA PTCNT1.IIC0AS PTCNT1.IIC0BS LPC.HICR0.FGA20E = 1 LPC.HICR0.PMEE = 1 ICE*IIC0AS*IIC0BS = 1 6 5 4 3 2 1 0 PA 7 6 5 4 3 2 1 0 _OE P95_OE P94_OE P93_OE P92_OE P91_OE P90_OE PS2CD_OE PS2CC_OE PS2BD_OE PS2BC_OE PS2AD_OE PS2AC_OE PS2DD_OE PS2DC_OE P95 P94 P93 P92 P91 P90 PS2CD PS2CC PS2BD PS2BC PS2AD PS2AC PS2DD PS2DC PS2_2.KBCRH.KBIOE = 1 PS2_2.KBCRH.KBIOE = 1 PS2_1.KBCRH.KBIOE = 1 PS2_1.KBCRH.KBIOE = 1 PS2_0.KBCRH.KBIOE = 1 PS2_0.KBCRH.KBIOE = 1 PS2_3.KBCRH.KBIOE = 1 PS2_3.KBCRH.KBIOE = 1 Rev. 1.00 Apr. 28, 2008 Page 190 of 994 REJ09B0452-0100 Section 7 I/O Ports Port PB 7 Output Specification Signal Name RTS_OE Output Signal Name RTS Signal Selection Register Settings Internal Module Settings LPC.HICR5.SCIFE, SCIFCR.SCIFOE1, SCIFOE0 SCIFOE = 1: (SCIFE * SCIFOE1 * SCIFOE0 + SCIFE * SCIFOE0) FSISS_OE 6 5 FSICK_OE DTR_OE FSISS FSICK DTR FSI.FSICR1.FSIE = 1 FSI.FSICR1.FSIE = 1 LPC.HICR5.SCIFE, SCIFCR.SCIFOE1, SCIFOE0 SCIFOE=1: (SCIFE * SCIFOE1 * SCIFOE0 + SCIFE * SCIFOE0) 4 3 2 1 0 PC 7 6 5 4 3 2 1 0 FSIDO_OE PWMU1B_OE PWMU0B_OE LSCI_OE LSMI_OE TIOCB2_OE TIOCA2_OE TIOCB1_OE TIOCA1_OE TIOCD0_OE TIOCC0_OE TIOCB0_OE TIOCA0_OE FSIDO PWMU1B PWMU0B LSCI LSMI TIOCB2 TIOCA2 TIOCB1 TIOCA1 TIOCD0 TIOCC0 TIOCB0 TIOCA0 FSI.FSICR1.FSIE = 1 PWMU_B.PWMCONB.PWM1E = 1 PWMU_B.PWMCONB.PWM0E = 1 LPC.HICR0.LSCIE = 1 LPC.HICR0.LSMIE = 1 TPU.TIOR2.IOB3 = 0, TPU.TIOR2.IOB[1:0] = 01/10/11 TPU.TIOR2.IOA3 = 0, TPU.TIOR2.IOA[1:0] = 01/10/11 TPU.TIOR1.IOB3 = 0, TPU.TIOR1.IOB[1:0] = 01/10/11 TPU.TIOR1.IOA3 = 0, TPU.TIOR1.IOA[1:0] = 01/10/11 TPU.TIOR0.IOD3 = 0, TPU.TIOR0.IOD[1:0] = 01/10/11 TPU.TIOR0.IOC3 = 0, TPU.TIOR0.IOC[1:0] = 01/10/11 TPU.TIOR0.IOB3 = 0, TPU.TIOR0.IOB[1:0] = 01/10/11 TPU.TIOR0.IOA3 = 0, TPU.TIOR0.IOA[1:0] = 01/10/11 Rev. 1.00 Apr. 28, 2008 Page 191 of 994 REJ09B0452-0100 Section 7 I/O Ports Port PD 7 6 5 4 3 2 1 0 PF 7 6 5 4 3 2 1 0 PG 7 6 5 4 3 2 1 0 PH 5 4 3 2 1 0 Output Specification Signal Name PD7_OE PD6_OE PD5_OE PD4_OE PD3_OE PD2_OE PD1_OE PD0_OE PWMU5A_OE PWMU4A_OE PWMU3A_OE PWMU2A_OE TMOX_OE TMOY_OE PWMU1A_OE PWMU0A_OE ExSCLB_OE ExSDAB_OE ExSCLA_OE ExSDAA_OE SCL2_OE SDA2_OE PG1_OE PG0_OE PH5_OE PH4_OE PH3_OE PH2_OE PH1_OE PH0_OE Output Signal Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PWMU5A PWMU4A PWMU3A PWMU2A TMOX TMOY PWMU1A PWMU0A ExSCLB ExSDAB ExSCLA ExSDAA SCL2 SDA2 PG1 PG0 PH5 PH4 PH3 PH2 PH1 PH0 Signal Selection Register Settings Internal Module Settings PWMU_A.PWMCONB.PWM5E = 1 PWMU_A.PWMCONB.PWM4E = 1 PWMU_A.PWMCONB.PWM3E = 1 PWMU_A.PWMCONB.PWM2E = 1 Except TMR_X.TCSR.OS[3:0] = 0000 Except TMR_Y.TCSR.OS[3:0] = 0000 PWMU_A.PWMCONB.PWM1E = 1 PWMU_A.PWMCONB.PWM0E = 1 PTCNT1.IIC1BS or PTCNT1.IIC0BS is 1 PTCNT1.IIC1BS or PTCNT1.IIC0BS is 1 PTCNT1.IIC1AS or PTCNT1.IIC0AS is 1 PTCNT1.IIC1AS or PTCNT1.IIC0AS is 1 IIC_2.ICCR.ICE = 1 IIC_2.ICCR.ICE = 1 Rev. 1.00 Apr. 28, 2008 Page 192 of 994 REJ09B0452-0100 Section 7 I/O Ports Port PI 7 6 5 4 3 2 1 0 PJ 7 6 5 4 3 2 1 0 Output Specification Signal Name PI7_OE PI6_OE PI5_OE PI4_OE PI3_OE PI2_OE PI1_OE PI0_OE PJ7_OE PJ6_OE PJ5_OE PJ4_OE PJ3_OE PJ2_OE PJ1_OE PJ0_OE Output Signal Name PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Signal Selection Register Settings Internal Module Settings Rev. 1.00 Apr. 28, 2008 Page 193 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.3 Change of Peripheral Function Pins For the external sub-clock input and IIC input/output, the multi-function I/O ports can be changed. I/O ports that also function as the external interrupt pins are changed by the setting of ISSR16 and ISSR. I/O ports that also function as the external sub-clock input pin are changed by the setting of PTCNT0. For IIC input/output, change the setting of PTCNT1. The pin name of the peripheral function is indicated by adding `Ex' at the head of the original pin name. In each peripheral function description, the original pin name is used. The following registers are available as the port control register. * Port control register 0 (PTCNT0) * Port control register 1 (PTCNT1) * Port control register 2 (PTCNT2) 7.3.1 Port Control Register 0 (PTCNT0) PTCNT0 selects ports that also function as the external sub-clock input pin. Bit 7 to 1 0 Bit Name EXCLS Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. 0: P96/EXCL is selected 1: PH0/ExEXCL is selected Rev. 1.00 Apr. 28, 2008 Page 194 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.3.2 Port Control Register 1 (PTCNT1) PTCNT1 selects ports that also function as IIC input/output pins. Bit 7 6 Bit Name IIC1BS IIC1AS Initial Value 0 0 R/W R/W R/W Description These bits select input/output pins for IIC_1 IIC1BS 0 0 1 1 4 5 3 2 IIC0BS IIC0AS 0 0 0 0 R/W R/W R/W Reserved The initial value should not be changed. These bits select input/output pins for IIC_0 IIC0BS 0 0 1 1 1 0 0 0 R/W R/W Reserved The initial value should not be changed. IIC0AS 0: 1: 0: 1: Selects P52/SCL0 and P97/SDA0 Selects PG5/ExSCLA and PG4/ExSDAA Selects PG7/ExSCLB and PG6/ExSDAB Setting prohibited IIC1AS 0: 1: 0: 1: Selects P86/SCL1 and P42/SDA1 Selects PG5/ExSCLA and PG4/ExSDAA Selects PG7/ExSCLB and PG6/ExSDAB Setting prohibited Note: Do not set input/output of IIC_0 and IIC_1 for one pin at the same time. Rev. 1.00 Apr. 28, 2008 Page 195 of 994 REJ09B0452-0100 Section 7 I/O Ports 7.3.3 Port Control Register 2 (PTCNT2) PTCNT2 selects ports that also function as SCI input/output pins and controls the port specification. Bit 7 6 5 4 3 2 1 0 Bit Name TxD2RS RxD2RS TxD1RS RxD1RS PORTS Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. 0: TxD2 direct output 1: TxD2 inverted output 0: RxD2 direct input 1: RxD2 inverted input 0: TxD1 direct output 1: TxD1 inverted output 0: RxD1 direct input 1: RxD1 inverted input Reserved The initial value should not be changed. 0: Existing port specification 1: New port specification Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 196 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Section 8 8-Bit PWM Timer (PWMU) This LSI has two channels of 8-bit PWM timers, A and B (PWMU_A and PWMU_B). Each PWMU outputs 6 PWM waveforms. Each of the PWM channels of a PWMU can operate independently. A PWMU allows long-period PWM outputs for six channels in 8-bit single-pulse mode and for three channels in 16-bit single-pulse mode. In addition, PWM outputs at a high carrier frequency are available in 8-bit pulse division mode. Connecting a low-pass filter externally to the LSI allows the PWMU to be used as an 8-bit D/A converter. 8.1 Features * Selectable from four types of counter input clock Selection of four internal clock signals (, /2, /4, and /8) * Independent operation and variable cycle for each channel Cascaded connection of two channels is possible. Operation of channel 1 (higher order) and channel 0 (lower order) as a 16-bit single-pulse PWM timer Operation of channel 3 (higher order) and channel 2 (lower order) as a 16-bit single-pulse PWM timer Operation of channel 5 (higher order) and channel 4 (lower order) as a 16-bit single-pulse PWM timer * 8-bit single pulse mode Operates at a maximum carrier frequency of 78.1 kHz (at 20 MHz operation) Pulse output settable with a duty cycle from 0/255 to 255/255 PWM output enable/disable control, and selection of direct or inverted PWM output * 16-bit single pulse mode Two channels are cascade-connected for operation in this mode. Operates at a maximum carrier frequency of 305.1 Hz (at 20 MHz operation) Pulse output settable with a duty cycle from 0/65535 to 65535/65535 PWM output enable/disable control, and selection of direct or inverted PWM output * 8-bit pulse division mode Operable at a maximum carrier frequency of 1.25 MHz (at 20 MHz operation) Pulse output settable with a duty cycle from 0/16 to 15/16 PWM output enable/disable control, and selection of direct or inverted PWM output Rev. 1.00 Apr. 28, 2008 Page 197 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Figure 8.1 shows a block diagram of the PWMU. /2 /4 /8 Clock generator Clock selection Module data bus PRE LAT Transfer control circuit PWM PRE Controller REG LAT PWM REG PWMCONA PWMCONB PWMCONC PWMCOND PWM counter/comparator PWMUO PWME [Legend] PWMPRE: PWM prescaler register PWMREG: PWM duty setting register PRELAT: Prescaler latch register REGLAT: Duty setting latch register PWMUO: PWM output waveform PWM output enable signal PWME: PWMCONA: PWM control register A for clock control PWMCONB: PWM control register B for output control PWMCONC: PWM control register C for mode control PWMCOND: PWM control register D for phase control Figure 8.1 Block Diagram of PWMU Timer Rev. 1.00 Apr. 28, 2008 Page 198 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.2 Input/Output Pins Table 8.1 shows the PWMU pin configuration. Table 8.1 Channel Channel A 0 1 Pin Configuration Pin Name PWMU0A PWMU1A I/O Output Output Function PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 8-bit pulse division) PWM pulse output (8-bit single pulse, 16-bit single pulse, 8-bit pulse division) 2 3 PWMU2A PWMU3A Output Output 4 5 PWMU4A PWMU5A Output Output Channel B 0 1 PWMU0B PWMU1B Output Output 2 3 PWMU2B PWMU3B Output Output 4 5 PWMU4B PWMU5B Output Output Rev. 1.00 Apr. 28, 2008 Page 199 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3 Register Descriptions The PWMU has the following registers. Table 8.2 Register Configuration Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Data Bus Address Width H'FD0C H'FD0D H'FD0E H'FD0F H'FD01 H'FD03 H'FD05 H'FD07 H'FD09 H'FD0B H'FD00 H'FD02 H'FD04 H'FD06 H'FD08 H'FD0A 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Channel Register Name Abbreviation R/W Channel A PWM control register A_A (for clock control) PWM control register B_A (for output control) PWM control register C_A (for mode control) PWM control register D_A (for phase control) PWM prescaler register 0_A PWM prescaler register 1_A PWM prescaler register 2_A PWM prescaler register 3_A PWM prescaler register 4_A PWM prescaler register 5_A PWM duty setting register 0_A PWM duty setting register 1_A PWM duty setting register 2_A PWM duty setting register 3_A PWM duty setting register 4_A PWM duty setting register 5_A PWMCONA_A R/W PWMCONB_A R/W PWMCONC_A R/W PWMCOND_A R/W PWMPRE0_A PWMPRE1_A PWMPRE2_A PWMPRE3_A PWMPRE4_A PWMPRE5_A PWMREG0_A PWMREG1_A PWMREG2_A PWMREG3_A PWMREG4_A PWMREG5_A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Apr. 28, 2008 Page 200 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Channel Register Name Abbreviation PWMCONA_B PWMCONB_B R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FD1C H'FD1D H'FD1E H'FD1F H'FD11 H'FD13 H'FD15 H'FD17 H'FD19 H'FD1B H'FD10 H'FD12 H'FD14 H'FD16 H'FD18 H'FD1A Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Channel B PWM control register A_B (for clock control) PWM control register B_B (for output control) PWM control register C_B (for mode control) PWM control register D_B (for phase control) PWM prescaler register 0_B PWM prescaler register 1_B PWM prescaler register 2_B PWM prescaler register 3_B PWM prescaler register 4_B PWM prescaler register 5_B PWM duty setting register 0_B PWM duty setting register 1_B PWM duty setting register 2_B PWM duty setting register 3_B PWM duty setting register 4_B PWM duty setting register 5_B PWMCONC_B R/W PWMCOND_B R/W PWMPRE0_B PWMPRE1_B PWMPRE2_B PWMPRE3_B PWMPRE4_B PWMPRE5_B PWMREG0_B PWMREG1_B PWMREG2_B PWMREG3_B PWMREG4_B PWMREG5_B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Apr. 28, 2008 Page 201 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3.1 PWM Control Register A (PWMCONA) PWMCONA selects the PWM clock source. Bit 7, 6 Bit Name Initial Value R/W R/W Description Clock Select 1, 0 These bits select the PWM count clock source. CLK1 CLK0 0 0 1 1 5 to 0 - All 0 R 0: Internal clock is selected 1: Internal clock /2 is selected 0: Internal clock /4 is selected 1: Internal clock /8 is selected CLK1, CLK0 All 0 Reserved These bits are always read as 0 and cannot be modified. 8.3.2 PWM Control Register B (PWMCONB) PWMCONB controls enabling and disabling of the PWM output and counter operation of each channel. Bit 7, 6 5 Bit Name PWM5E Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. PWMU5 Output Enable 0: PWMU5 output and counter operation are disabled. 1: PWMU5 output and counter operation are enabled. Rev. 1.00 Apr. 28, 2008 Page 202 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Bit 4 Bit Name PWM4E Initial Value 0 R/W R/W Description PWMU4 Output Enable * 8-bit single-pulse/pulse-division mode 0: PWMU4 output and counter operation are disabled. 1: PWMU4 output and counter operation are enabled. * 16-bit single-pulse mode 0: PWMU4 output and counter operation are disabled. 1: PWMU4 output and counter operation are enabled. 3 PWM3E 0 R/W PWMU3 Output Enable 0: PWMU3 output and counter operation are disabled. 1: PWMU3 output and counter operation are enabled. 2 PWM2E 0 R/W PWMU2 Output Enable * 8-bit single-pulse/pulse division mode 0: PWMU2 output and counter operation are disabled. 1: PWMU2 output and counter operation are enabled. * 16-bit single-pulse mode 0: PWMU2 output and counter operation are disabled. 1: PWMU2 output and counter operation are enabled. 1 PWM1E 0 R/W PWMU1 Output Enable 0: PWMU1 output and counter operation are disabled. 1: PWMU1 output and counter operation are enabled. Rev. 1.00 Apr. 28, 2008 Page 203 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Bit 0 Bit Name PWM0E Initial Value 0 R/W R/W Description PWMU0 Output Enable * 8-bit single-pulse/pulse division mode 0: PWMU0 output and counter operation are disabled. 1: PWMU0 output and counter operation are enabled. * 16-bit single-pulse mode 0: PWMU0 output and counter operation are disabled. 1: PWMU0 output and counter operation are enabled. Rev. 1.00 Apr. 28, 2008 Page 204 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3.3 PWM Control Register C (PWMCONC) PWMCONC selects the PWM count mode and operating mode for each channel. Bit 7 6 Bit Name CNTMD01 Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Channels 0 and 1 Counter Select 0: Channels 0 and 1 are in 8-bit counter operation. 1: Channels 0 and 1 are in 16-bit counter operation (Upper: channel 1, lower: channel 0). Note: When the 16-bit counter is selected, specify single pulse mode. 5 PWMSL5 0 R/W Channel 5 Operating Mode Select 0: Single-pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 4 PWMSL4 0 R/W Channel 4 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 3 PWMSL3 0 R/W Channel 3 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 2 PWMSL2 0 R/W Channel 2 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 1 PWMSL1 0 R/W Channel 1 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) 0 PWMSL0 0 R/W Channel 0 Operating Mode Select 0: Single pulse mode 1: Pulse division mode (Specify 8-bit counter mode.) Rev. 1.00 Apr. 28, 2008 Page 205 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3.4 PWM Control Register D (PWMCOND) PWMCOND selects the PWM count mode and output phase for each channel. Bit 7 Bit Name PH5S Initial Value 0 R/W R/W Description Channel 5 Output Phase Select 0: PWMU5 direct output 1: PWMU5 inverted output 6 PH4S 0 R/W Channel 4 Output Phase Select 0: PWMU4 direct output 1: PWMU4 inverted output 5 PH3S 0 R/W Channel 3 Output Phase Select 0: PWMU3 direct output 1: PWMU3 inverted output 4 PH2S 0 R/W Channel 2 Output Phase Select 0: PWMU2 direct output 1: PWMU2 inverted output 3 PH1S 0 R/W Channel 1 Output Phase Select 0: PWMU1 direct output 1: PWMU1 inverted output 2 PH0S 0 R/W Channel 0 Output Phase Select 0: PWMU0 direct output 1: PWMU0 inverted output 1 CNTMD45 0 R/W Channels 4 and 5 Counter Select 0: Channels 4 and 5 are in 8-bit counter operation. 1: Channels 4 and 5 are in 16-bit counter operation (Upper: channel 5, lower: channel 4). Note: When the 16-bit counter is selected, specify single pulse mode. 0 CNTMD23 0 R/W Channels 2 and 3 Counter Select 0: Channels 2 and 3 are in 8-bit counter operation. 1: Channels 2 and 3 are in 16-bit counter operation (Upper: channel 2, lower: channel 3). Note: When the 16-bit counter is selected, specify single pulse mode. Rev. 1.00 Apr. 28, 2008 Page 206 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3.5 PWM Prescaler Registers 0 to 5 (PWMPRE0 to PWMPRE5) PWMPRE are 8-bit readable/writable registers used to set the PWM cycle. The initial value is H'00. When the PWMPRE value is n, the PWM cycle is calculated as follows. (1) 8-Bit Single Pulse Mode PWM cycle = [255 x (n + 1)] / internal clock frequency (0 n 255) Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency (8-Bit Counter Operation) when = 20 MHz Carrier Frequency Internal Clock Frequency Resolution /2 /4 /8 50 ns 100 ns 200 ns 400 ns PWM Conversion Period Min. 12.8 s 25.5 s 51.2 s 102 s Max. 3.3 ms 6.5 ms 13.1 ms 26.1 ms Single Pulse Mode Min. 306.4 Hz 153.2 Hz 76.6 Hz 38.3 Hz Max. 78.4 kHz 39.2 kHz 19.6 kHz 9.8 kHz Rev. 1.00 Apr. 28, 2008 Page 207 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) (2) 16-Bit Single Pulse Mode When 16-bit single pulse mode is selected, PWMPRE0, PWMPRE2, and PWMPRE4 are valid. The settings of PWMPRE1, PWMPRE3, and PWMPRE5 are invalid. PWM cycle = [65535 x (n + 1)] / internal clock frequency (0 n 255) Table 8.4 Resolution, PWM Conversion Period, and Carrier Frequency (16-Bit Counter Operation) when = 20 MHz Carrier Frequency Internal Clock Frequency Resolution /2 /4 /8 50 ns 100 ns 200 ns 400 ns PWM Conversion Period Min. 3.3 ms 6.5 ms 13.1 ms 26.2 ms Max. 838.9 ms 1.7 s 3.4 s 6.7 s Single Pulse Mode Min. 1.2 Hz 0.6 Hz 0.3 Hz 0.15 Hz Max. 305.1 Hz 152.6 Hz 76.3 Hz 38.1 Hz (3) 8-Bit Pulse Division Mode PWM cycle = [16 x (n + 1)] / internal clock frequency (0 n 255) PWM conversion cycle = [256 x (n + 1)] / internal clock frequency (0 n 255) Table 8.5 Resolution, PWM Conversion Period, and Carrier Frequency when = 20 MHz (at 8-bit counter operation) PWM Conversion Period Min. 12.8 s 25.6 s 51.2 s 102.4 s Max. 3.3ms 6.6ms 13.1ms 26.2ms Carrier Frequency (1/PWM cycle) Min. 4882.8Hz 2441.4Hz 1220.7Hz 610.4Hz Max. 1250.0 kHz 625.0 kHz 312.5 kHz 156.3 kHz Internal Clock Frequency Resolution /2 /4 /8 50 ns 100 ns 200 ns 400 ns Rev. 1.00 Apr. 28, 2008 Page 208 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.3.6 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5) PWMREG0 to PWMREG5 are 8-bit readable/writable registers used to set the high period (duty) of the PWM output pulse. The initial value is H'00. (1) 8-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty cycle of the PWM output pulse is specified as a value from 0/255 to 255/255 with a resolution of 1/255. When the PWMREG value is m, the high period of the output pulse is calculated as follows: Output pulse high period = (PWM cycle x m) / 255 (0 m 255) (2) 16-Bit Single Pulse Mode Directly set the high period of the pulse for PWM output. With cascade-connected PWMREG registers, the duty cycle of the PWM output pulse is specified as a value from 0/65535 to 65535/65535. When the PWMREG value is m, the high period of the output pulse is calculated as follows: Output pulse high period = (PWM cycle x m) / 65535 (0 m 65535) Set the respective high-level pulse periods by using the following register combinations (cascaded connection): PWMREG1 (higher order) and PWMREG0 (lower order), PWMREG3 (higher order) and PWMREG2 (lower order), and PWMREG5 (higher order) and PWMREG4 (lower order). (3) 8-Bit Pulse Division Mode Specify the basic pulse duty cycle and the number of additional pulses for PWM output. The higher-order four bits of the PWMREG setting specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, and the lower-order four bits specify the number of pulses to be added within the conversion period comprising the basic pulses. Rev. 1.00 Apr. 28, 2008 Page 209 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.4 Operation The PWMU operates in 8-bit single pulse mode, 16-bit single pulse mode, or 8-bit division pulse mode. 8.4.1 Single-Pulse Mode (8 Bits, 16 Bits) Figure 8.2 shows a block diagram of 8-bit single pulse mode. Figure 8.3 shows a block diagram of 16-bit single pulse mode. Clock generator PRELAT0 CNT0 Comparator 0 PWMU00 REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 8.2 Block Diagram of 8-Bit Single Pulse Mode Rev. 1.00 Apr. 28, 2008 Page 210 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Clock generator PRELAT0 CNT0 Comparator 0 PWMU00 (Output disabled) REGLAT0 PRELAT1 CNT1 Comparator 1 PWMU01 REGLAT1 Figure 8.3 Block Diagram of 16-bit Single Pulse Mode Rev. 1.00 Apr. 28, 2008 Page 211 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) When the PWMnE bit (n = 0 to 5) in PWMCONB is set to 1, the PWMU outputs pulses that start with a high level. The updated PWMREG value is written in REGLAT, and the updated PWMPRE value is written in PRELAT. When the REGLAT value is less than the duty counter value, the PWMU outputs a high level (when direct output is selected). At each PWM clock timing, the duty counter is incremented. When the clock generator counter is H'00, the PWM clock is generated by decrementing the PRELAT value. Figure 8.4 shows an example of duty counter and clock generator counter operation. /4 Duty counter Clock generator counter PRELAT REGLAT PWMUO H'01 H'78 H'00 H'01 H'79 H'00 H'01 H'80 H'01 H'80 H'00 H'01 H'81 H'00 Figure 8.4 Example of Duty Counter and Clock Generator Counter Operation (When PWMPRE = H'01 and PWMREG = H'80 with /4 Selected as Count Clock Source) The following shows the duty counter value and PWMU output timing. Duty counter H'FF REGLAT H'00 PWMUO Figure 8.5 Duty Counter Value and PWMU Output Timing Rev. 1.00 Apr. 28, 2008 Page 212 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) If the PWMREG value is changed during PWM output, the PWMREG value is loaded into REGLAT when the duty counter overflows (at the beginning of the next PWM cycle). The following shows the PWMU output waveform when the PWMREG value is changed. Duty counter H'FF REGLAT' (value after write) REGLAT H'00 PWMUO PWMREG write signal Figure 8.6 PWMU Output Waveform When PWMREG Value is Changed When the PWMPRE value is changed during PWM output, the PWM cycle changes from the next cycle. When the clock generator counter underflows, the PWMPRE value is loaded into PRELAT. The following shows the PRELAT update timing when the PWMPRE value is changed. Clock generation counter PRELAT'' PRELAT' PRELAT H'00 PWMPRE write signal PWMPRE'' PWMPRE' Figure 8.7 PRELAT Update Timing When PWMPRE Value is Changed Rev. 1.00 Apr. 28, 2008 Page 213 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.4.2 Pulse Division Mode In pulse division mode, the higher-order four bits in PWMREG specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The following shows the duty cycle of the basic pulse. Table 8.6 Upper 4 bits B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 Basic Pulse Duty Cycle Basic Pulse Waveform (Internal) 0 1 2 3 4 5 6 7 8 9ABCDEF B'1100 B'1101 B'1110 B'1111 Resolution Rev. 1.00 Apr. 28, 2008 Page 214 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) The lower four bits in PWMREG specify the position of pulses added to the 16 basic pulses. The additional pulse adds a high period (when PHnS = 0) at the resolution width before the rising edge of the basic pulse. Although there is no rising edge of the basic pulse when the upper four bits in PWMREG is B'0000, the timing for adding pulses is the same. Table 8.7 shows the additional pulse positions corresponding to the basic pulses, and figure 8.8 shows an example of additional pulse timing. Table 8.7 Lower 4 Bits B'0000 B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Additional Pulse Positions Corresponding to Basic Pulse Basic Pulse Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 No pulse added Resolution width Pulse added Additional pulse Figure 8.8 Example of Additional Pulse Timing (Upper 4 Bits in PWMREG = B'1000) Rev. 1.00 Apr. 28, 2008 Page 215 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) (1) Example of Setting 1 conversion period PWMREG setting example 0 H'7F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 127/256 112 pulses 15 pulses Additional Basic waveform pulses Duty cycle H'80 128/256 128 pulses 0 pulse H'81 129/256 128 pulses 1 pulse H'82 : Position of additional pulse 130/256 128 pulses 2 pulses A duty cycle of 0/256 to 255/256 is output as a low-ripple waveform by combining basic pulses and additional pulses. Figure 8.9 Example of WMU Setting (2) Example of Circuit for Use as D/A Converter The following shows an example of a circuit in which PWMU output pulses are used as a D/A converter. When a low-pass filter is connected externally to the LSI, low-ripple analog output can be generated. If pulse division mode is used, a D/A output with even less ripple is available. Resistor: 120 k Capacitor: 0.1 F This LSI Low-pass filter Reference values Figure 8.10 Example of Circuit for Use as a D/A Converter Rev. 1.00 Apr. 28, 2008 Page 216 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) 8.5 8.5.1 Usage Note Setting Module Stop Mode The module stop control register can be used to enable or disable PWMU operation. The default setting disables PWMU operation. Clearing the module stop mode enables registers to be accessed. For details, see section 26, Power-Down Modes. 8.5.2 Note on Using 16-Bit Single-Pulse PWM Timer When the duty cycle is to be changed in usage of a 16-bit single-pulse PWM timer, the higher- and lower-order eight bits must be individually written to the respective PWMREGn (n = 0 to 5) registers. There will thus be a time lag between the write operations, and this may lead to the output of a pulse waveform with a duty cycle other than the intended one during the corresponding period. Also, care must be taken to ensure that there are no interrupts while writing to PWMREGn is in progress, since interrupt processing can lead to the continued output of pulses with a duty cycle other than the intended one. Rev. 1.00 Apr. 28, 2008 Page 217 of 994 REJ09B0452-0100 Section 8 8-Bit PWM Timer (PWMU) Rev. 1.00 Apr. 28, 2008 Page 218 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) Section 9 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with two output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 9.1 Features * Division of pulse into multiple base cycles to reduce ripple * Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles. * Two base cycle settings The base cycle can be set equal to T x 64 or T x 256, where T is the resolution. * Sixteen operation clocks (by combination of eight resolution settings and two base cycle settings) Figure 9.1 shows a block diagram of the PWM (D/A) module. Internal clock /2, /64, /128, /256, /1024, /4096, /16384 Clock Internal data bus PCSR Select clock Bus interface Base cycle compare match A PWX0 PWX1 Fine-adjustment pulse addition A Base cycle compare match B Fine-adjustment pulse addition B Comparator A Comparator B DADRA DADRB Control logic Base cycle overflow DACNT DACR [Legend] DACR: DADRA: DADRB: DACNT: PCSR: Module data bus PWMX D/A control register (6 bits) PWMX D/A data register A (15 bits) PWMX D/A data register B (15 bits) PWMX D/A counter (14 bits) Peripheral clock select register Figure 9.1 PWMX (D/A) Block Diagram Rev. 1.00 Apr. 28, 2008 Page 219 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.2 Input/Output Pins Table 9.1 lists the PWMX (D/A) module input and output pins. Table 9.1 Pin Name PWMX output pin 0 PWMX output pin 1 Pin Configuration Abbreviation I/O PWX0 PWX1 Output Output Function PWMX output of channel A PWMX output of channel B 9.3 Register Descriptions The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to the same addresses with other registers. The registers are selected by the IICE bit in the serial timer control register (STCR). For details on the module stop control register, see section 26.1.3, Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB). Table 9.2 Register Configuration Abbreviation R/W DACNTH DACNTL DADRAH DADRAL DADRBH DADRBL DACR R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'00 H'03 H'FF H'FF H'FF H'FF H'30 H'00 H'FFA6 H'FEA6* H'FFA7 H'FEA7* H'FFA0 H'FEA0* H'FFA1 H'FEA1* H'FFA6 H'FEA6* H'FFA7 H'FEA7* H'FFA0 H'FEA0* H'FF82 Data Bus Width 8 8 8 8 8 8 8 8 Register Name PWMX (D/A) counter H PWMX (D/A) counter L PWMX (D/A) data register AH PWMX (D/A) data register AL PWMX (D/A) data register BH PWMX (D/A) data register BL PWMX (D/A) control register Peripheral clock select register PCSR Notes: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or DADRB. * Upper address: when RELOCATE = 0 Lower address: when RELOCATE = 1 Rev. 1.00 Apr. 28, 2008 Page 220 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper 2-bit counter. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 9.4, Bus Master Interface. DACNTH Bit (CPU): Bit (counter): 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 7 8 6 9 5 10 DACNTL 4 11 3 12 2 13 1 0 REGS * DACNTH Bit 7 to 0 Bit Name Initial Value R/W R/W Description Upper Up-Counter DACNT7 to All 0 DACNT0 * DACNTL Bit 7 to 2 1 0 Bit Name Initial Value R/W R/W R R/W Description Lower Up-Counter Reserved Always read as 1 and cannot be modified. REGS 1 Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed DACNT 8 to All 0 DACNT 13 1 Rev. 1.00 Apr. 28, 2008 Page 221 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As DACNT is 16 bits, data transfer between the CPU is performed through the temporary register (TEMP). For details, see section 9.4, Bus Master Interface. * DADRA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 The range of DA13 to DA0: H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 The range of DA13 to DA0: H'0040 to H'3FFF 0 1 R Reserved Always read as 1 and cannot be modified. Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT. Rev. 1.00 Apr. 28, 2008 Page 222 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) * DADRB Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit Name DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Carrier Frequency Select 0: Base cycle = resolution (T) x 64 DA13 to DA0 range = H'0100 to H'3FFF 1: Base cycle = resolution (T) x 256 DA13 to DA0 range = H'0040 to H'3FFF 0 REGS 1 R/W Register Select DADRA and DACR, and DADRB and DACNT, are located at the same addresses. The REGS bit specifies which registers can be accessed. 0: DADRA and DADRB can be accessed 1: DACR and DACNT can be accessed Description D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit. If the DADR value is outside this range, the PWM output is held constant. A channel can be operated with 12-bit precision by fixing DA0 and DA1 to 0. The two data bits are not compared with DACNT12 and DACNT13 of DACNT. Rev. 1.00 Apr. 28, 2008 Page 223 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit 7 6 Bit Name PWME Initial Value 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H0003 5 4 3 OEB 1 1 0 R R R/W Reserved Always read as 1 and cannot be modified. Output Enable B Enables or disables output on PWMX (D/A) channel B. 0: PWMX (D/A) channel B output (at the PWX1 output pin) is disabled 1: PWMX (D/A) channel B output (at the PWX1 output pin) is enabled 2 OEA 0 R/W Output Enable A Enables or disables output on PWMX (D/A) channel A. 0: PWMX (D/A) channel A output (at the PWX0 output pin) is disabled 1: PWMX (D/A) channel A output (at the PWX0 output pin) is enabled 1 OS 0 R/W Output Select Selects the phase of the PWMX (D/A) output. 0: Direct PWMX (D/A) output 1: Inverted PWMX (D/A) output 0 CKS 0 R/W Clock Select Selects the PWMX (D/A) resolution. Eight kinds of resolution can be selected. 0: Operates at resolution (T) = system clock cycle time (tcyc) 1: Operates at resolution (T) = system clock cycle time (tcyc) x 2, x 64, x 128, x 256, x 1024, x 4096, and x 16384. Rev. 1.00 Apr. 28, 2008 Page 224 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit 7 6 5 4 Bit Name PWCKXB PWCKXA Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. PWMX clock select These bits select a clock cycle with the CKS bit of DACR of PWMX being 1. See table 9.3. 3 to 1 0 PWCKXC All 0 0 R/W R/W Reserved The initial value should not be changed. PWMX clock select This bit selects a clock cycle with the CKS bit of DACR of PWMX being 1. See table 9.3. Table 9.3 PWCKXC 0 0 0 0 1 1 1 1 Clock Select of PWMX PWCKXB 0 0 1 1 0 0 1 1 PWCKXA 0 1 0 1 0 1 0 1 Resolution (T) Operates on the system clock cycle (tcyc) x 2 Operates on the system clock cycle (tcyc) x 64 Operates on the system clock cycle (tcyc) x 128 Operates on the system clock cycle (tcyc) x 256 Operates on the system clock cycle (tcyc) x 1024 Operates on the system clock cycle (tcyc) x 4096 Operates on the system clock cycle (tcyc) x 16384 Setting prohibited Rev. 1.00 Apr. 28, 2008 Page 225 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. * Write When the upper byte is written to, the upper-byte write data is stored in TEMP. Next, when the lower byte is written to, the lower-byte write data and TEMP value are combined, and the combined 16-bit value is written in the register. * Read When the upper byte is read from, the upper-byte value is transferred to the CPU and the lower-byte value is transferred to TEMP. Next, when the lower byte is read from, the lowerbyte value in TEMP is transferred to the CPU. These registers should always be accessed 16 bits at a time with a MOV instruction, and the upper byte should always be accessed before the lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is accessed. Also note that a bit manipulation instruction cannot be used to access these registers. Example 1: Write to DACNT MOV.W R0, @DACNT ; Write R0 contents to DACNT Example 2: Read DADRA MOV.W @DADRA, R0 ; Copy contents of DADRA to R0 Rev. 1.00 Apr. 28, 2008 Page 226 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) Table 9.4 Reading/Writing to 16-bit Registers Read Write Word O O Byte x x Register DADRA, DADRB DACNT Word O O Byte O x [Legend] O: Enabled access. Word-unit access includes accessing byte sequentially, first upper byte, and then lower byte. x: The result of the access in the unit cannot be guaranteed. (a) Write to upper byte Module data bus Bus interface CPU [H'AA] Upper byte TEMP [H'AA] DACNTH [ ] (b) Write to lower byte DACNTL [ ] CPU [H'57] Lower byte Module data bus Bus interface TEMP [H'AA] DACNTH [H'AA] DACNTL [H'57] Figure 9.2 DACNT Access Operation (1) [CPU DACNT (H'AA57) Writing] Rev. 1.00 Apr. 28, 2008 Page 227 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) (a) Read upper byte Module data bus Bus interface CPU [H'AA] Upper byte TEMP [H'57] DACNTH [H'AA] (b) Read lower byte DACNTL [H'57] CPU [H'57] Lower byte Module data bus Bus interface TEMP [H'57] DACNTH [ ] DACNTL [ ] Figure 9.2 DACNT Access Operation (2) [DACNT CPU (H'AA57) Reading] Rev. 1.00 Apr. 28, 2008 Page 228 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.5 Operation A PWM waveform like the one shown in figure 9.3 is output from the PWMX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 9.4 and 9.5 show the types of waveform output available. 1 conversion cycle (T x 214 (= 16384)) tf Base cycle (T x 64 or T x 256) tL T: Resolution TL = tLn (OS = 0) n=1 m (When CFS = 0, m = 256 When CFS = 1, m = 64) Figure 9.3 PWMX (D/A) Operation Table 9.5 summarizes the relationships between the CKS and CFS bit settings and the resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR contain at least a certain minimum value. The relationship between the OS bit and the output waveform is shown in figures 9.4 and 9.5. Rev. 1.00 Apr. 28, 2008 Page 229 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) Table 9.5 PCSR PWCKX0 PWCKX1 C B A S 0 Settings and Operation (Examples when = 20 MHz) Fixed DADR Bits Resolution CK T (s) 0.05 Base CFS Cycle 0 3.2 (s) /312.5kHz 1 12.8 (s) () /78.1kHz 0 6.4 (s) /156.2kHz 1 25.6 (s) (/2) /39.1kHz 0 204.8 (s) /4.9kHz 1 819.2 (s) (/64) /1.2kHz 0 409.6 (s) /2.4kHz 1 1638.4 (s) (/128) /610.4kHz 104.9 (ms) 52.4 (ms) 1.64 (ms) Conversion Cycle 819.2 (s) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Accuracy DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA0 Bit Data Conversion Cycle* 819.2 s 204.8 s 51.2 s 819.2 s 204.8 s 51.2 s 1638.4 s 409.6 s 102.4 s 1638.4 s 409.6 s 102.4 s 52.4 ms 13.1 ms 3.3 ms 52.4 ms 13.1 ms 3.3 ms 104.9 ms 26.2 ms 6.6 ms 104.9 ms 26.2 ms 6.6 ms 0 0 0 1 0.1 0 0 1 1 3.2 0 1 0 1 6.4 Rev. 1.00 Apr. 28, 2008 Page 230 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) PCSR PWCKX0 PWCKX1 C 0 B 1 A 1 Resolution T CKS (s) 1 12.8 Base CFS Cycle 0 819.2 (s) /1.2kHz 1 3276.8 (s) (/256) /305.2kH z 1 0 0 1 51.2 0 3.3 (ms) /305.2Hz 1 13.1 (ms) (/1024) 1 0 1 1 204.8 0 /76.3Hz 13.1 (ms) /76.3Hz 1 52.4 (ms) (/4096) 1 1 0 1 819.2 0 /19.1Hz 52.4 (ms) /19.1Hz 1 209.7 (ms) (/16384) 1 1 1 1 Setting prohibited /4.8Hz 13.4 (s) 3.4 (s) 838.9 (ms) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 14 12 10 Conversion Cycle 209.7 (ms) TL/TH (OS = 0/OS = 1) Always low/high output DA13 to 0 = H'0000 to H'00FF (Data value) x T DA13 to 0 = H'0100 to H'3FFF Always low/high output DA13 to 0 = H'0000 to H'003F (Data value) x T DA13 to 0 = H'0040 to H'3FFF Fixed DADR Bits Bit Data Accuracy DA3 DA2 DA1 (Bits) 14 12 10 14 12 10 0 0 0 0 0 0 0 0 0 0 0 0 DA0 0 0 0 0 0 0 0 0 0 0 0 0 Conversion Cycle* 209.7 ms 52.4 ms 13.1 ms 209.7 ms 52.4 ms 13.1 ms 838.9 ms 0 0 0 0 209.7 ms 52.4 ms 838.9 ms 0 0 0 0 209.7 ms 52.4 ms 3.4 s 0 0 0 0 838.9 ms 209.7 ms 3.4 s 0 0 0 0 838.9 ms 209.7 ms 13.4 s 0 0 0 0 3.4 s 838.9 ms 13.4 s 0 0 0 0 3.4 s 838.9 ms Note: * Indicates the conversion cycle when specific DA3 to DA0 bits are fixed. Rev. 1.00 Apr. 28, 2008 Page 231 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tL1 tL2 tL3 tL255 tL256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tL1 + tL2 + tL3+ *** + tL255 + tL256 = TL (a) CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tL1 + tL2 + tL3 + *** + tL63 + tL64 = TL (b) CFS = 1 [base cycle = resolution (T) x 256] Figure 9.4 Output Waveform (OS = 0, DADR corresponds to TL) Rev. 1.00 Apr. 28, 2008 Page 232 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 1 conversion cycle tf1 tf2 tf255 tf256 tH1 tH2 tH3 tH255 tH256 tf1 = tf2 = tf3 = *** = tf255 = tf256 = Tx 64 tH1 + tH2 + tH3 + *** + tH255 + tH256 = TH (a) CFS = 0 [base cycle = resolution (T) x 64] 1 conversion cycle tf1 tf2 tf63 tf64 tH1 tH2 tH3 tH63 tH64 tf1 = tf2 = tf3 = *** = tf63 = tf64 = Tx 256 tH1 + tH2 + tH3 + *** + tH63 + tH64 = TH (b) CFS = 1 [base cycle = resolution (T) x 256] Figure 9.5 Output Waveform (OS = 1, DADR corresponds to TH) An example of the additional pulses when CFS = 1 (base cycle = resolution (T) x 256) and OS = 1 (inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0) determine the locations of the additional pulses as shown in figure 9.6. Table 9.6 lists the locations of the additional pulses. DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Duty cycle of base pulse Location of additional pulses Figure 9.6 D/A Data Register Configuration when CFS = 1 Rev. 1.00 Apr. 28, 2008 Page 233 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in figure 9.7. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of the base pulse duty cycle is 2/256 x (T). Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the location of base pulse No. 63 according to table 9.6. Thus, an additional pulse of 1/256 x (T) is to be added to the base pulse. 1 conversion cycle Base cycle No. 0 Base cycle No. 1 Base cycle No. 63 Base pulse High width: 2/256 x (T) Base pulse 2/256 x (T) Additional pulse output location Additional pulse 1/256 x (T) Figure 9.7 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) x 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above. Rev. 1.00 Apr. 28, 2008 Page 234 of 994 REJ09B0452-0100 Base pulse No. Table 9.6 Lower 6 bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Locations of Additional Pulses Added to Base Pulse (When CFS = 1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Section 9 14-Bit PWM Timer (PWMX) Rev. 1.00 Apr. 28, 2008 Page 235 of 994 REJ09B0452-0100 Section 9 14-Bit PWM Timer (PWMX) 9.6 9.6.1 Usage Notes Module Stop Mode Setting PWMX operation can be enabled or disabled by using the module stop control register. In the initial state, PWMX operation is disabled. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 236 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. 10.1 Features * Maximum 8-pulse input/output * Selection of eight counter input clocks for channels 0 and 2, seven counter input clocks for channel 1 * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation Maximum of 7-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channel 0 * Phase counting mode settable independently for each of channels 1 and 2 * Fast access via internal 16-bit bus * 13 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated Rev. 1.00 Apr. 28, 2008 Page 237 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Clock input Internal clock: /1 /4 /16 /64 /256 /1024 External clock: TCLKA TCLKB TCLKC TCLKD TSTR TSYR Control logic Common Bus interface Internal data bus A/D converter convertion start signal TCR TMDR TIOR TIER TSR Channel 2 Input/output pins Module data bus TCNT TGRA TGRB Control logic for channel 0 to 2 TCR TMDR TIORH TIORL TIER TSR Channel 0: TIOCA0 TIOCB0 TIOCC0 TIOCD0 Channel 1: TIOCA1 TIOCB1 Channel 2: TIOCA2 TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TCR TMDR TIOR TIER TSR Channel 1 Channel 0 [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register Timer I/O control registers (H, L) TIOR (H, L): Timer interrupt enable register TIER: Timer status register TSR: TGR (A, B, C, D): TImer general registers (A, B, C, D) Figure 10.1 Block Diagram of TPU Rev. 1.00 Apr. 28, 2008 Page 238 of 994 REJ09B0452-0100 TCNT TGRA TGRB TGRC TGRD TCNT TGRA TGRB Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Count clock Channel 0 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 General registers/buffer TGRC_0 registers TGRC_0 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 Counter clear function Compare match output 0 output 1 output Toggle output Input capture function TIOCA1 TIOCB1 TIOCA2 TIOCB2 TGR compare match TGR compare match TGR compare match or or input capture or input capture input capture O O O O O O O O O O O O O O O O O O Synchronous operation O PWM mode Phase counting mode Buffer operation O O Rev. 1.00 Apr. 28, 2008 Page 239 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Item A/D converter trigger Interrupt sources Channel 0 TGRA_0 compare match or input capture 5 sources * * * * * Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow Channel 1 TGRA_1 compare match or input capture 4 sources * * * * Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow Channel 2 TGRA_2 compare match or input capture 4 sources * * * * Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow [Legend] O: Enable : Disable Rev. 1.00 Apr. 28, 2008 Page 240 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.2 Pin Configuration Channel All Pin Name TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin Rev. 1.00 Apr. 28, 2008 Page 241 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. Table 10.3 Register Configuration Channel Register Name Channel 0 Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Channel 1 Timer control register_1 Timer mode register_1 Timer I/O control register _1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Channel 2 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Abbreviation R/W TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 Data Bus Address Width H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 8 8 8 8 8 8 16 16 16 H'0000 H'FE56 H'FFFF H'FE58 H'FFFF H'FE5A H'FFFF H'FE5C 16 H'FFFF H'FE5E H'00 H'C0 H'00 H'40 H'C0 H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 16 8 8 8 8 8 16 16 H'0000 H'FD46 H'FFFF H'FD48 H'FFFF H'FD4A 16 H'00 H'C0 H'00 H'40 H'C0 H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 8 8 8 8 8 16 H'0000 H'FE76 Rev. 1.00 Apr. 28, 2008 Page 242 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Channel Register Name Channel 2 Timer general register A_2 Timer general register B_2 Common Timer start register Timer synchro register Abbreviation R/W TGRA_2 TGRB_2 TSTR TSYR R/W R/W R/W R/W Initial Value Data Bus Address Width 16 16 8 8 H'FFFF H'FE78 H'FFFF H'FE7A H'00 H'00 H'FEB0 H'FEB1 10.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 10.4 and 10.5 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock cycle is divided in 2 (/4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1 and rising edge count is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 1 0 [Legend] x: Don't care TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.6 to 10.8 for details. Rev. 1.00 Apr. 28, 2008 Page 243 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.4 CCLR2 to CCLR0 (channel 0) Channel 0 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous/clearing synchronous 1 operation* TCNT clearing disabled TCNT cleared by TGRC compare 2 match/input capture* TCNT cleared by TGRD compare 2 match/input capture* TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* 1 0 0 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register. TCNT is not cleared because the buffer register setting has priority, and compare match/input capture dose not occur. Table 10.5 CCLR2 to CCLR0 (channels 1 and 2) Channel 1, 2 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous 1 clearing/synchronous operation* Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 244 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.6 TPSC2 to TPSC0 (channel 0) Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.7 TPSC2 to TPSC0 (channel 1) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Setting prohibited Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 1.00 Apr. 28, 2008 Page 245 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.8 TPSC2 to TPSC0 (channel 2) Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Note: This setting is ignored when channel 2 is in phase counting mode. Rev. 1.00 Apr. 28, 2008 Page 246 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit 7 6 5 Bit Name BFB Initial value 1 1 0 R/W R R R/W Description Reserved These bits are always read as 1 and cannot be modified. Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register. TGRD input capture/output compare is not generation. Because channels 1 and 2 have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. Because channels 1 and 2 have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, the write value should always be 0. See table 10.9 for details. Rev. 1.00 Apr. 28, 2008 Page 247 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.9 MD3 to MD0 Bit 3 1 MD3* 0 Bit2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 x x 0 1 1 x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Setting prohibited [Legend] x: Don't care Notes: 1. MD3 is reserved bit. In a write, it should be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Rev. 1.00 Apr. 28, 2008 Page 248 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two each for channels 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. Description I/O Control B3 to B0 Specify the function of TGRB. * TIORL_0 Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. Description I/O Control D3 to D0 Specify the function of TGRD. Rev. 1.00 Apr. 28, 2008 Page 249 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.10 TIORH_0 (channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match 1 0 Initial output is 0 output 1 output at compare match 1 Initial output is 0 output Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 output 0 output at compare match 1 0 Initial output is 1 output 1 output at compare match 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge Capture input source is TIOCB0 pin Input capture at both edges Setting prohibited Rev. 1.00 Apr. 28, 2008 Page 250 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.11 TIORH_0 (channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited Rev. 1.00 Apr. 28, 2008 Page 251 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 TIORL_0 (channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRD_0 Function Output Compare register* TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge Capture input source is TIOCD0 pin Input capture at both edges Setting prohibited [Legend] x: Don't care Note: When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Apr. 28, 2008 Page 252 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 TIORL_0 (channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 1 IOC0 0 1 1 0 1 TGRC_0 Function Output compare register* TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match 1 0 0 1 1 0 Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match 1 1 0 0 0 1 1 1 x x x Input capture register* Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited [Legend] x: Don't care Note: * When the BFA bit in TMDR_0 is set to 1and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Apr. 28, 2008 Page 253 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 TIOR_1 (channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match 1 0 0 1 1 0 Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register Initial output is 1 output Toggle output at compare match Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges Setting prohibited Rev. 1.00 Apr. 28, 2008 Page 254 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIOR_1 (channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at falling edge Capture input source is TIOCA0 pin Input capture at both edges Setting prohibited Rev. 1.00 Apr. 28, 2008 Page 255 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIOR_2 (channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges Rev. 1.00 Apr. 28, 2008 Page 256 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIOR_2 (channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x Input capture register TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match Initial output is 1 output 1 output at compare match Initial output is 1 output Toggle output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges Rev. 1.00 Apr. 28, 2008 Page 257 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD disabled 1: Interrupt requests (TGID) by TGFD enabled. Rev. 1.00 Apr. 28, 2008 Page 258 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC disabled 1: Interrupt requests (TGIC) by TGFC enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA disabled 1: Interrupt requests (TGIA) by TGFA enabled Rev. 1.00 Apr. 28, 2008 Page 259 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channel 1 and 2. In channel 0, bit 7 is reserved. It is always read as 0 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 TCFU 1 0 R Reserved This bit is always read as 1 and cannot be modified. R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (change from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W) * Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (change from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 1.00 Apr. 28, 2008 Page 260 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing condition] When 0 is written to TGFD after reading TGFD = 1 2 TGFC 0 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When the TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing condition] When 0 is written to TGFC after reading TGFC = 1 Rev. 1.00 Apr. 28, 2008 Page 261 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W Description R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing condition] When 0 is written to TGFB after reading TGFB = 1 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. The write value should always be 0 to clear this flag. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing condition] When 0 is written to TGFA after reading TGFA = 1 Note: * The write value should always be 0 to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 262 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four for channel 0 and two each for channels 1 and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers. The TGR registers are initialized to H'FFFF by a reset. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA-- TGRC and TGRB--TGRD. 10.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. TCNT of a channel performs counting when the corresponding bit in TSTR is set to 1. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 to 3 2 1 0 Bit Name CST2 CST1 CST0 Initial value 0 0 0 0 R/W R R/W R/W R/W Description Reserved The initial value should not be changed. Counter Start 2 to 0 (CST2 to CST0) These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_n count operation is stopped 1: TCNT_n performs count operation (n = 2 to 0) Rev. 1.00 Apr. 28, 2008 Page 263 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7 to 3 2 1 0 Bit Name SYNC2 SYNC 1 SYNC 0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. Timer Synchro 2 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_n operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_n performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 2 to 0) Rev. 1.00 Apr. 28, 2008 Page 264 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 10.4.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 10.2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 10.4.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 10.3, 10.4, and 10.5. Rev. 1.00 Apr. 28, 2008 Page 265 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master Module data bus L Bus interface TCR Figure 10.3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 10.5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] Rev. 1.00 Apr. 28, 2008 Page 266 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 10.5.1 Operation Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of count operation setting procedure Figure 10.6 shows an example of the count operation setting procedure. Operation selection [1] Select the counter clock with bits TPSC2 to TPSC0 inTCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Set period [4] [5] Set the CST bit in TSTR to 1 to start the counter operation. Start count operation Select counter clock [1] Periodic counter Free-running counter Select counter clearing source [2] Select output compare register [3] Start count operation [5] Figure 10.6 Example of Counter Operation Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 267 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.8 illustrates periodic counter operation. Rev. 1.00 Apr. 28, 2008 Page 268 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software activation TGF Figure 10.8 Periodic Counter Operation (2) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of setting procedure for waveform output by compare match Figure 10.9 shows an example of the setting procedure for waveform output by compare match. Output selection Select waveform output mode [1] Set output timing [2] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10.9 Example of Setting Procedure for Waveform Output by Compare Match Rev. 1.00 Apr. 28, 2008 Page 269 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 10.10 Example of 0 Output/1 Output Operation Figure 10.11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 10.11 Example of Toggle Output Operation Rev. 1.00 Apr. 28, 2008 Page 270 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. (a) Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure. Input selection Select input capture input [1] Start count [2] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 10.12 Example of Input Capture Operation Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 271 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.13 Example of Input Capture Operation Rev. 1.00 Apr. 28, 2008 Page 272 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 10.14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source Start count No [3] Set synchronous counter clearing Start count [4] [5] [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.14 Example of Synchronous Operation Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 273 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.5.4, PWM Modes. TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time Synchronous clearing by TGRB_0 compare match TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.15 Example of Synchronous Operation Rev. 1.00 Apr. 28, 2008 Page 274 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.18 shows the register combinations used in buffer operation. Table 10.18 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 Buffer Register TGRC_0 TGRD_0 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.16 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.17. Input capture signal Buffer register Timer general register TCNT Figure 10.17 Input Capture Buffer Operation Rev. 1.00 Apr. 28, 2008 Page 275 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Example of Buffer Operation Setting Procedure Figure 10.18 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function Set buffer operation Start count [1] [2] [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Figure 10.18 Example of Buffer Operation Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 276 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) (a) Examples of Buffer Operation When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.5.4, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.19 Example of Buffer Operation (1) Rev. 1.00 Apr. 28, 2008 Page 277 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.20 Example of Buffer Operation (2) Rev. 1.00 Apr. 28, 2008 Page 278 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.19. Rev. 1.00 Apr. 28, 2008 Page 279 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. (1) Example of PWM Mode Setting Procedure Figure 10.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation. Set PWM mode [5] Start count [6] Figure 10.21 Example of PWM Mode Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 280 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of PWM Mode Operation Figure 10.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 10.22 Example of PWM Mode Operation (1) Figure 10.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty. TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Counter cleared by TGRB_1 compare match Time Figure 10.23 Example of PWM Mode Operation (2) Rev. 1.00 Apr. 28, 2008 Page 281 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty TCNT value TGRB rewritten TGRA Output does not change when cycle register and duty register compare matches occur simultaneously TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA TCNT value TGRB rewritten TGRA Output does not change when cycle register and duty register compare matches occur simultaneously TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10.24 Example of PWM Mode Operation (3) Rev. 1.00 Apr. 28, 2008 Page 282 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10.20 shows the correspondence between external clock pins and channels. Table 10.20 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 10.25 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode [1] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10.25 Example of Phase Counting Mode Setting Procedure Rev. 1.00 Apr. 28, 2008 Page 283 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.21 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 1 Operation Table 10.21 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 1.00 Apr. 28, 2008 Page 284 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.22 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 1.00 Apr. 28, 2008 Page 285 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (c) Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.23 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 1.00 Apr. 28, 2008 Page 286 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.24 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.24 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 1.00 Apr. 28, 2008 Page 287 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 10.6.1 Interrupts Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.25 lists the TPU interrupt sources. Table 10.25 TPU Interrupts Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Note: * Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow Interrupt Flag TGFA TGFB TGFC TGFD TCFV TGFA TGFB TCFV TCFU TGFA TGFB TCFV TCFU Low Priority* High This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 1.00 Apr. 28, 2008 Page 288 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. (3) Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 10.6.2 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev. 1.00 Apr. 28, 2008 Page 289 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 10.7.1 (1) Operation Timing Input/Output Timing TCNT Count Timing Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.30 Count Timing in Internal Clock Operation External clock TCNT input clock TCNT N-1 N N+1 N+2 Falling edge Rising edge Falling edge Figure 10.31 Count Timing in External Clock Operation Rev. 1.00 Apr. 28, 2008 Page 290 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.32 shows output compare output timing. TCNT input clock TCNT TGR Compare match signal TIOC pin N N N+1 Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10.33 Input Capture Input Signal Timing Rev. 1.00 Apr. 28, 2008 Page 291 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) Timing for Counter Clearing by Compare Match/Input Capture Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear signal TCNT TGR N N H'0000 Figure 10.34 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 10.35 Counter Clear Timing (Input Capture) Rev. 1.00 Apr. 28, 2008 Page 292 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Buffer Operation Timing Figures 10.36 and 10.37 show the timing in buffer operation. TCNT Compare match signal TGRA, TGRB TGRC, TGRD n N n n+1 N Figure 10.36 Buffer Operation Timing (Compare Match) Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10.37 Buffer Operation Timing (Input Capture) Rev. 1.00 Apr. 28, 2008 Page 293 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.7.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. TCNT input clock TCNT TGR Compare match signal TGF flag TGI interrupt N N N+1 Figure 10.38 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture Figure 10.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. Input capture signal TCNT N TGR TGF flag TGI interrupt N Figure 10.39 TGI Interrupt Timing (Input Capture) Rev. 1.00 Apr. 28, 2008 Page 294 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (3) TCFV Flag/TCFU Flag Setting Timing Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10.40 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) Underflow signal TCFU flag TCIU interrupt H'0000 H'FFFF Figure 10.41 TCIU Interrupt Setting Timing Rev. 1.00 Apr. 28, 2008 Page 295 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the timing for status flag clearing by the CPU. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 10.42 Timing for Status Flag Clearing by CPU Rev. 1.00 Apr. 28, 2008 Page 296 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 10.8.1 Usage Notes Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.43 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.43 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 10.8.2 Caution on Period Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f = -------- (N + 1) Where f: Counter frequency : Operating frequency N: TGR set value Rev. 1.00 Apr. 28, 2008 Page 297 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.3 Conflict between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case. TCNT write cycle T1 T2 Address Write signal Counter clear signal TCNT N H'0000 TCNT address Figure 10.44 Conflict between TCNT Write and Clear Operations 10.8.4 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.45 shows the timing in this case. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 10.45 Conflict between TCNT Write and Increment Operations Rev. 1.00 Apr. 28, 2008 Page 298 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.5 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.46 shows the timing in this case. TGR write cycle T1 T2 Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M Prohibited TGR address Figure 10.46 Conflict between TGR Write and Compare Match 10.8.6 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.47 shows the timing in this case. Rev. 1.00 Apr. 28, 2008 Page 299 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TGR write cycle T2 T1 Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Buffer register address Figure 10.47 Conflict between Buffer Register Write and Compare Match 10.8.7 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.48 shows the timing in this case. TGR read cycle T1 T2 Address Read signal Input capture signal TGR Internal data bus X M M TGR address Figure 10.48 Conflict between TGR Read and Input Capture Rev. 1.00 Apr. 28, 2008 Page 300 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.8 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing in this case. TGR write cycle T2 T1 Address Write signal Input capture signal TCNT M M TGR address TGR Figure 10.49 Conflict between TGR Write and Input Capture 10.8.9 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.50 shows the timing in this case. Rev. 1.00 Apr. 28, 2008 Page 301 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer register write cycle T1 T2 Address Write signal Input capture signal TCNT M N N M Buffer register address TGR Buffer register Figure 10.50 Conflict between Buffer Register Write and Input Capture 10.8.10 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 10.51 Conflict between Overflow and Counter Clearing Rev. 1.00 Apr. 28, 2008 Page 302 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.11 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.52 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT H'FFFF M TCNT write data TCFV flag Figure 10.52 Conflict between TCNT Write and Overflow 10.8.12 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.8.13 Module Stop Mode Setting TPU operation can be enabled or disabled by the module stop control register. In the initial state, TPU operation is disabled. Access to TPU registers is enabled when module stop mode is cancelled. For details, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 303 of 994 REJ09B0452-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Apr. 28, 2008 Page 304 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Section 11 16-Bit Cycle Measurement Timer (TCM) This LSI has four channels on-chip 16-bit cycle measurement timers (TCM). Each TCM has a 16bit counter that provides the basis for measuring the periods of input waveforms. 11.1 * * * * * Features Capable of measuring the periods of input waveforms Sensed edge is selectable 16-bit compare match 16-bit resolution Selectable counter clock Any of seven internal clocks or an external clock * Five interrupt sources Counter overflow Cycle upper limit overflow Cycle lower limit underflow Compare match Triggering of input capture Rev. 1.00 Apr. 28, 2008 Page 305 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Figure 11.1 is a block diagram of the TCM. External clock TCMCKI Internal clock /2, /8, /16, /32 /64, /128, /256 Clock selection Overflow TCMCNT Control TCMMCI logic Clear Compare matrch Comparator TCMMLCM TCMMINCM Input capture Module data bus Cycle upper limit overflow Cycle lower limit underflow TCMCYI TCMICR TCMICRF TCMCSR TCMIER TCMCR TICI TCMI TOVMI TUDI TOVI [Legend] TCMCNT: TCM timer counter TCMMLCM: TCM cycle upper limit register TCMMINCM:TCM cycle lower limit register TCMICR: TCM input capture register TCMICRF: TCM input capture buffer register TCMCSR: TCM status register TCMIER: TCM interrupt enable register TCMCR: TCM control register Figure 11.1 Block Diagram of the TCM Rev. 1.00 Apr. 28, 2008 Page 306 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.2 Input/Output Pins Table 11.1 lists the input and output pins for the TCMs. Table 11.1 Pin Configuration Channel 0 Pin Name TCMCKI0 (TCMMCI0) TCMCYI0 1 TCMCKI1 (TCMMCI1) TCMCYI1 2 TCMCKI2 (TCMMCI2) TCMCYI2 3 TCMCKI3 (TCMMCI3) TCMCYI3 Input Input Input Input Input Input Input I/O Input Function External counter clock input Cycle measurement control input External event input External counter clock input Cycle measurement control input External event input External counter clock input Cycle measurement control input External event input External counter clock input Cycle measurement control input External event input 11.3 Register Descriptions The TCMs have the following registers. Table 11.2 Register Configuration Channel Register Name Channel 0 TCM timer counter_0 TCM cycle upper limit register_0 TCM cycle lower limit register_0 TCM input capture register_0 Initial Abbreviation R/W Value TCMCNT_0 Data Bus Address Width R/W H'0000 H'FBC0 16 TCMMLCM_0 R/W H'FFFF H'FBC2 16 TCMMINCM_0 R/W H'0000 H'FBCC 16 TCMICR_0 R R H'0000 H'FBC4 16 H'0000 H'FBC6 16 H'FBC8 8 H'FBC9 8 H'FBCA 8 TCM input capture buffer register_0 TCMICRF_0 TCM status register_0 TCM control register_0 TCM interrupt enable register_0 TCMCSR_0 TCMCR_0 TCMIER_0 R/W H'00 R/W H'00 R/W H'00 Rev. 1.00 Apr. 28, 2008 Page 307 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Channel Register Name Channel 1 TCM timer counter_1 TCM cycle upper limit register_1 TCM cycle lower limit register_1 TCM input capture register_1 Abbreviation R/W TCMCNT_1 R/W Initial Value Data Bus Address Width H'0000 H'FBD0 16 H'FFFF H'FBD2 16 H'0000 H'FBDC 16 H'0000 H'FBD4 16 H'0000 H'FBD6 16 H'00 H'00 H'00 H'FBD8 8 H'FBD9 8 H'FBDA 8 16 16 TCMMLCM_1 R/W TCMMINCM_1 R/W TCMICR_1 R R R/W R/W R/W R/W TCM input capture buffer register_1 TCMICRF_1 TCM status register_1 TCM control register_1 TCM interrupt enable register_1 Channel 2 TCM timer counter_2 TCM cycle upper limit register_2 TCM cycle lower limit register_2 TCM input capture register_2 TCMCSR_1 TCMCR_1 TCMIER_1 TCMCNT_2 H'0000 H'FBE0 H'FFFF H'FBE2 TCMMLCM_2 R/W TCMMINCM_2 R/W TCMICR_2 R R R/W R/W R/W R/W H'0000 H'FBEC 16 H'0000 H'FBE4 H'0000 H'FBE6 H'00 H'00 H'00 H'FBE8 H'FBE9 16 16 8 8 TCM input capture buffer register_2 TCMICRF_2 TCM status register_2 TCM control register_2 TCM interrupt enable register_2 Channel 3 TCM timer counter_3 TCM cycle upper limit register_3 TCM cycle lower limit register_3 TCM input capture register_3 TCMCSR_2 TCMCR_2 TCMIER_2 TCMCNT_3 H'FBEA 8 16 16 H'0000 H'FBF0 H'FFFF H'FBF2 TCMMLCM_3 R/W TCMMINCM_3 R/W TCMICR_3 R R R/W R/W R/W H'0000 H'FBFC 16 H'0000 H'FBF4 H'0000 H'FBF6 H'00 H'00 H'00 H'FBF8 H'FBF9 16 16 8 8 TCM input capture buffer register_3 TCMICRF_3 TCM status register_3 TCM control register_3 TCM interrupt enable register_3 TCMCSR_3 TCMCR_3 TCMIER_3 H'FBFA 8 Rev. 1.00 Apr. 28, 2008 Page 308 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.1 TCM Timer Counter (TCMCNT) TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this case, the rising or falling edge is selected by CKSEG in TCMCR. When TCMCNT overflows (counting changes the value from H'FFFF to H'0000), OVF in TCMCSR is set to 1. When the CST bit in TCMCR is cleared in timer mode, TCMCR is initialized to H'0000. In cycle measurement mode, TCMCNT is cleared by detection of the first edge (the edge selected with the IEDG bit in TCMCR) of the measurement period (one period of the input waveform forms one measurement period). In timer mode, TCMCNT is always writable. TCMCNT cannot be modified in cycle measurement mode. TCMCNT should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMCNT is initialized to H'0000. 11.3.2 TCM Cycle Upper Limit Register (TCMMLCM) TCMMLCM is a 16-bit readable/writable register. TCMMLCM is available as a compare match register when the TCMMDS bit in TCMCR is cleared (operation is in timer mode). TCMMLCM is available as a cycle upper limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in cycle measurement mode). In timer mode, the value in TCMMLCM is constantly compared with that in TCMCNT, when the values match, CMF in TCMCSR is set to 1. However, comparison is disabled in the second half of a cycle of writing to TCMMLCM. In cycle measurement mode, a value that sets an upper limit on the measurement period can be set in TCMMLCM. When the second edge (first edge of the following cycle) of the measurement period is detected, the value in TCMCNT is transferred to TCMICR. At this time, the values in TCMICR and TCMMLCM are compared. The MAXOVF flag in TCMCSR is set to 1 if the value in TCMICR is greater than that in TCMMLCM. TCMMLCM should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMMLCM is initialized to H'FFFF. Rev. 1.00 Apr. 28, 2008 Page 309 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) TCMMINCM is a 16-bit readable/writable register. TCMMINCM is available as a cycle lower limit register when the TCMMDS bit in TCMCR is set to 1 (operation is in cycle measurement mode). In cycle measurement mode, a value that sets a lower limit on the measurement period can be set in TCMMINCM. When the second edge (selectable with the IEDG bit in TCMCR) of the measurement period is detected, the value in TCMCNT is transferred to TCMICR. At this time, the values in TCMICR and TCMMINCM are compared. The MINUDF flag in TCMCSR is set to 1 if the value in TCMICR is smaller than that in TCMMINCM. TCMMLCM should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMMINCM is initialized to H'0000. 11.3.4 TCM Input Capture Register (TCMICR) TCMICR is a 16-bit read-only register. In timer mode, the value in TCMCNT is transferred to TCMICR on the edge selected by the IEDG bit in TCMCR. At the same time, the ICPF flag in TCMCSR is set to 1. In cycle measurement mode, the value in TCMCNT is transferred to TCMICR on detection of the second edge of the measurement period. At this time, the ICPF flag in TCMCSR is set to 1. TCMICR should always be accessed in 16-bit units and cannot be accessed in 8-bit units. TCMICR is initialized to H'0000. 11.3.5 TCM Input Capture Buffer Register (TCMICRF) TCMICRF is a 16-bit read only register. TCMICRF can be used as TCMICR buffer register. When input capture is generated, the value in TCMICR is transferred to TCMICRF. TCMICR and TCMICRF should always be accessed in 16-bit units and cannot be accessed in 8bit units. TCMICRF is initialized to H'0000. Rev. 1.00 Apr. 28, 2008 Page 310 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.6 TCM Status Register (TCMCSR) TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources. Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Timer Overflow This flag indicates that the TCMCNT has overflowed. [Setting condition] Overflow of TCMCNT (change in value from H'FFFF to H'0000) [Clearing condition] Reading OVF when OVF = 1 and then writing 0 to OVF. 6 MAXOVF 0 R/(W)* Measurement Period Upper Limit Overflow This flag indicates that the measured number of cycles of the waveform for measurement in cycle measurement mode has reached the upper limit set in TCMMLCM, causing an overflow. [Setting condition] A greater value for TCMICR than TCMMLCM [Clearing condition] Reading MAXOVF when MAXOVF = 1 and then writing 0 to MAXOVF 5 CMF 0 R/(W)* Compare Match Flag (only valid in timer mode) [Setting condition] When the values in TCMCNT and TCMMLCM match. [Clearing condition] Reading CMF when CMF = 1 and then writing 0 to CMF Note: CMF is not set in cycle measurement mode, even when the values in TCMCNT and TCMMLCM match. 4 CKSEG 0 R/W External Clock Edge Select When bits CKS2 to CKS0 in TCMCR are set to B'111, this bit selects the edge for counting of external count clock edge. 0: Count falling edges of the external clock. 1: Count rising edges of the external clock. Rev. 1.00 Apr. 28, 2008 Page 311 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Bit 3 Bit Name ICPF Initial Value 0 R/W Description R/(W)* Input Capture Generation Timer mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on generation of an input capture signal. This flag is set when the input capture signal is generated, i.e. on detection of the edge selected by the IEDGD bit on the TCMCYI input pin. Cycle measurement mode: The flag indicates that the value in TCMCNT has been transferred to TCMICR on detection of the second edge (rising or falling as determined by the IEDG bit in TCMCR) during the measurement period. [Setting condition] Generation of the input capture signal [Clearing condition] Reading ICPF when ICPF = 1 and then writing 0 to ICPF 2 MINUDF 0 R/(W)* Measurement Period Lower Limit Underflow This flag indicates that the measured number of cycles of the waveform for measurement in cycle measurement mode has reached the lower limit set in TCMMINCM, causing an underflow. [Setting condition] A smaller value for TCMICR than TCMMINCM [Clearing condition] Reading MINUDF when MINUDF = 1 and then writing 0 to MINUDF 1 MCICTL 0 R/W TCMMCI Input Polarity Inversion 0: TCMMCI input is inverted for use. 1: TCMMCI input is directly used. Note: Change this bit when CST = 0 and TCMMDS = 0 2 to 0 Note: * All 0 R/W Reserved The initial value should not be changed. Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 312 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.7 TCM Control Register (TCMCR) TCMCR is an 8-bit readable/writable register. TCMCR selects input capture input edge, counter start, and counter clock, and controls operation mode. Bit 7 Bit Name CST Initial Value 0 R/W R/W Description Counter Start In timer mode, setting this bit to 1 starts counting by TCMCNT; clearing this bit stops counting by TCMCNT. Then, the counter is initialized to H'0000, and input-capture operation stops. Clear this bit and thus return TCMCNT to H'0000 in initialization for cycle measurement mode. 6 POCTL 0 R/W TCMCYI Input Polarity Reversal 0: Use the TCMCYI input directly 1: Use the inverted TCMCYI input Note: Modify this bit while CST = 0 and TCMMDS = 0 5 CPSPE 0 R/W Input Capture Stop Enable Controls whether or not counting up by TCMCNT and inputcapture operation stop or continue when either of MAXOVF or MINUDF is set to 1 in cycle measurement mode. The bit does not affect operation in timer mode. 0: Counting up and input-capture operation continue when the flag is set to 1. 1: Counting up and input-capture operation are disabled when the flag is set to 1. Rev. 1.00 Apr. 28, 2008 Page 313 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Bit 4 Bit Name IEDG Initial Value 0 R/W R/W Description Input Edge Select In timer mode, selects the falling or rising edge of the TCMCYI input for use in input capture, in combination with the value of the POCTL bit. In cycle measurement mode, selects the falling or rising edge of the TCMCYI input for use in measurement, in combination with the value of the POCTL bit. POCTL = 0 0: Selects the rising edge of the TCMCYI input 1: Selects the falling edge of the TCMCYI input POCTL = 1 0: Selects the falling edge of the TCMCYI input 1: Selects the rising edge of the TCMCYI input 3 TCMMDS 0 R/W TCM Mode Select Selects the TCM operating mode. 0: Timer mode The TCM provides compare match and input capture facilities. 1: Cycle measurement mode Setting this bit to 1 starts counting by TCMCNT. TCMCNT should be initialized to H'0000. Clear the CST in TCMCR to 0 before setting to cycle measurement mode. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2, 1, 0 Selects the clock signal for input to TCMCNT. Note: Modify this bit when CST = 0 and TCMMDS = 0 000: Count /2 internal clock 001: Count /8 internal clock 010: Count /16 internal clock 011: Count /32 internal clock 100: Count /64 internal clock 101: Count /128 internal clock 110: Count /256 internal clock 111: Count external clock (select the external clock edge with CKSEG in TCMCSR.) Rev. 1.00 Apr. 28, 2008 Page 314 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.3.8 TCM Interrupt Enable Register (TCMIER) TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests. Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Counter Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the OVF flag in TCMCSR to 1. 0: Disable interrupt requests by OVF 1: Enable interrupt requests by OVF 6 MAXOVIE 0 R/W Cycle Upper Limit Overflow Interrupt Enable Enables or disables the issuing of interrupt requests on setting of the MAXOVF flag in TCMCSR to 1. 0: Disable interrupt requests by MAXOVF 1: Enable interrupt requests by MAXOVF 5 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables the issuing of interrupt requests when the CMF bit in TCMCSR is set to 1. 0: Disable interrupt requests by CMF 1: Enable interrupt requests by CMF 4 TCMIPE 0 R/W Input Capture Input Enable Enables or disables input to the pin. When using interrupt capture mode and cycle measurement mode, set this bit to 1. 0: Disable input 1: Enable input Note: Modify this bit when CST = 0 and TCMMDS = 0. 3 ICPIE 0 R/W Input Capture Interrupt Enable Enables or disables interrupt requests when the ICPF flag in TCMCSR is set to 1. 0: Disable interrupt requests by ICPF 1: Enable interrupt requests by ICPF Rev. 1.00 Apr. 28, 2008 Page 315 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Bit 2 Bit Name MINUDIE Initial Value 0 R/W R/W Description Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of the TUDI interrupt requests when the MINUDF flag in TCMCSR is set to 1. 0: Disable interrupt requests by MINUDF 1: Enable interrupt requests by MINUDF 1 CMMS 0 R/W Cycle Measurement Mode Selection Selects use of the TCMMCI signal in cycle measurement mode. 0: The TCMMCI signal is not used (cycle measurement is always performed). 1: The TCMMCI signal is used. When MCICTL in TCMCSR is 0, cycle measurement is performed only while TCMMCI is low. When MCICTL is 1, cycle measurement is performed only while TCMMCI is high. Note: Change this bit when CST = 0 and TCMMDS = 0. 0 0 R Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 316 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.4 Operation The TCM operates in timer mode or cycle measurement mode. TCM is in timer mode after a reset. 11.4.1 Timer Mode When the TCMMDS bit in TCMCR is cleared to 0, TCM operates in timer mode. (1) Counter Operation TCMCNT operates as a free running counter in timer mode. TCMCNT starts counting up when the CST bit in TCMCR is set to 1. When TCMCNT overflows (the value changes from H'FFFF to H'0000), the OVF bit in TCMCSR is set to 1 and an interrupt request is generated if the OVIE bit in TCMIER is 1. Figure 11.2 shows an example of free running counter operation. In addition, figure 11.3 shows TCMCNT count timing of external clock operation. The external clock should have a pulse width of no less than 1.5 cycles. The counter will not operate correctly if the pulses are narrower than this. /4 TCMCNT input clock TCMCNT N-1 N N+1 Figure 11.2 Example of Free Running Counter Operation TCMCKI TCMCNT input clock TCMCNT N-1 N N+1 Figure 11.3 Count Timing of External Clock Operation (Falling Edges) Rev. 1.00 Apr. 28, 2008 Page 317 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) (2) Input Capture The value in TCMCNT is transferred to TCMICR by detecting input edge of TCMCYI pin in timer mode. At this time, the ICPF flag in TCMCSR is set. Detection of rising or falling edges is selectable with the setting of the IEDG bit in TCMCR. Figure 11.4 shows an example of the timing of input capture operations and figure 11.5 shows buffer operation of input capture. TCMCYI Input capture signal TCMCNT TCMICR ICPF N-1 M N N+1 N N+2 N+3 Figure 11.4 Input Capture Operation Timing (Sensing of Rising Edges) TCMCYI Input capture signal TCMCNT TCMICR TCMICRF N-1 M L N N M 0 0+1 0 N Figure 11.5 Buffer Operation of Input Capture Rev. 1.00 Apr. 28, 2008 Page 318 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) (3) CMF Set Timing when a Compare Match occurs The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM match in timer mode. Therefore, a compare match signal is not generated until a further cycle of the TCMCNT input clock is generated after a match between the values in TCMCNT and TCMMLCM. For details, see section 11.6.2, Conflict between TCMMLCM Write and Compare Match. Figure 11.6 shows the timing with which the CMF flag is set. TCMCNT TCMMLC Compare match signal CMF N N N+1 Figure 11.6 Timing of CMF Flag Setting on a Compare Match 11.4.2 Cycle Measurement Mode When the TCMMDS bit in TCMCR is set to 1, the TCM operates in cycle measurement mode. (1) Counter Operation Setting the TCMMDS bit in TCMCR to 1 selects cycle measurement mode, in which counting up proceeds regardless of the setting of the CST bit in TCMCR. TCMCNT is cleared to H'0000 on detection of the first edge in the measurement period and counts up from there. Figure 11.7 shows an example of counter operation in cycle measurement mode. TCMCYI TCMCNT clear signal TCMCNT input clock TCMCNT N H'0000 H'0001 H'0002 H'0003 H'0000 H'0001 Figure 11.7 Example of Counter Operation in Cycle Measurement Mode Rev. 1.00 Apr. 28, 2008 Page 319 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) (2) Measuring a Cycle In cycle measurement mode, one cycle of the input waveform for TCM form one measurement cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000. After that, set an upper or lower limit on the measurement cycle in the TCMMLCM/TCMMINCM register. Finally, place the timer in cycle measurement mode by setting the TCMMDS bit in TCMCR to 1. TCMCNT will count cycles of the selected clock. On detection of the first edge (either rising or falling as selected with the IEDG bit in TCMCR) of the measurement cycle, TCMCNT is automatically cleared to H'0000. On detection of the second edge, the value in TCMCNT is transferred to TCMICR. At this time, the value in TCMICR is compared with the value in TCMMLCM/TCMMINCM. If TCMICR is larger than TCMMLCM, the MAXOVF bit in TCMCSR is set to 1. If TCMICR is smaller than TCMMINCM, the MINUDF bit in TCMCSR is set to 1. If generation of the corresponding interrupt request is enabled by the setting in TCMIER, the request is generated. In addition, on detection of the third edge, TCMCNT is cleared to H'0000, and the next round of measurement starts. When the CPSPE bit in TCMCR has been cleared to 0, the next round of cycle measurement will start, even if the MAXOVF/MINUDF flag is set to 1. If the MAXOVF/MINUDF flag is set to 1 while the CPSPE bit in TCMCR is set to 1, counting up by TCMCNT stops and so does cycle measurement. Subsequently clearing MAXOVF/MINUDF to 0 automatically clears TCMCNT to H'0000, and counting up for cycle measurement is then restarted. Figure 11.8 shows an example of timing in speed measurement. TCMCYI TCMCNT clear signal TCMCNT input clock TCMCNT TCMICR MAXOVF/ MINUDF TCMICRF K L M M L H'0000 H'0001 M N-1 N H'0000 N H'0001 Figure 11.8 Example of Timing in Cycle Measurement Rev. 1.00 Apr. 28, 2008 Page 320 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) When the CMMS bit in TCMIER is set to 1, cycle measurement is performed only while the TCMMCI signal is high (MCICTL in TCMCSR is 0). Figure 11.9 shows an example of timing in cycle measurement when the CMMS bit is set to 1. TCMCYI TCMMCI TCMCNT TCMICR M L 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9AB0 1 2 3 4 5 M H'0007 H'0006 H'000B Figure 11.9 Example of Timing in Cycle Measurement when the CMMS Bit is Set to 1 (3) Determination of External Event (TCMCYI) Stoppage The timer overflow flag can be used to determine the external event (TCMCYI) stopped state. Either of two sets of conditions represents the external event stopped state. The external event can be considered to have stopped when a timer overflow is generated within the period from the start of cycle measurement mode to detection of the first edge (rising or falling as selected with the IEDG bit in TCMCR). Figure 11.10 shows an example of the timing of the external event stopped state (1). TCMCYI TCMMDS TCMCNT OVF MAXOVF/ MINUDF H'0000 H'FFFF H'0000 N H'0000 H'0001 H'0002 Start of measurement Determined as external event stopped state Figure 11.10 Example of Timing in External Event Stopped State (1) Rev. 1.00 Apr. 28, 2008 Page 321 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Cycle measurement stops if MAXOVF/MINUDF is set to 1 while the CPSPE bit in TCMCR is set to 1. Subsequently clearing MAXOVF/MINUDF to 0 restarts cycle measurement. In this case, the external event can be considered to have stopped if a timer overflow is generated before detection of the first edge. Figure 11.11 shows an example of the timing of the external event stopped state (2). TCMCYI CPSPE TCMCNT OVF MAXOVF/ MINUDF Restart of mesurement H'5555 H'0000 H'FFFF H'0000 N H'0000 H'0001 Start of measurement Determined as external event stopped state Figure 11.11 Example of Timing in External Event Stopped State (2) Rev. 1.00 Apr. 28, 2008 Page 322 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) (4) Example of Settings for Cycle Measurement Mode Figure 11.12 shows an example of the flow when cycle measurement mode is to be used. Start Initialization [1] [2] Set CST (TCMCR) to 0 [2] [3] [4] [5] Set TCMIPE = 1 [4] [6] Set OVIE and MAXOVIE to 1 [5] [7] [8] [9] OVF = 1? or MAXOVF = 1? No Set TCMMDS = 0 [9] Yes MAXOVF = 1? End of measurement No Processing for external event stopped state [7] Processing for cycle upper limit over [8] Yes Interrupt is generated Set speed measurement mode to start speed measurement. Processing for the external event stopped state. Processing for cycle upper limit over. Speed measurement is completed. Set timer mode. Stop TCMCNT and initialize to H'0000. Set an upper limit on the measurement period. Pin input enabled. Enable interrupts. Set TCMMDS to 0 [1] Set TCMMLCM [3] Set TCMMDS to 1 [6] End of exception handling Figure 11.12 Example of Cycle Measurement Mode Settings Rev. 1.00 Apr. 28, 2008 Page 323 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.5 Interrupt Sources TCM has five interrupt sources: TICI, TCMI, TOVMI, TUDI, and TOVI. Each interrupt source is either enabled or disabled by the corresponding interrupt enable bit in TCMIER and independently transferred to the interrupt controller. Since a single vector address is allocated for each type of interrupt source from all channels, the flags must be used to discriminate between the sources. Table 11.3 lists the interrupt sources in priority order. Table 11.3 TCM Interrupt Sources Channel TCM_0 Name TICI0 TCMI0 TOVMI0 TUDI0 TOVI0 TCM_1 TICI1 TCMI1 TOVMI1 TUDI1 TOVI1 TCM_2 TICI2 TCMI2 TOVMI2 TUDI2 TOVI2 TCM_3 TICI3 TCMI3 TOVMI3 TUDI3 TOVI3 Interrupt Source TCMICR_0 input capture TCMMLCM_0 compare match TCMMLCM_0 overflow TCMMINCM_0 underflow TCMCNT_0 overflow TCMICR_1 input capture TCMMLCM_1 compare match TCMMLCM_1 overflow TCMMINCM_1 underflow TCMCNT_1 overflow TCMICR_2 input capture TCMMLCM_2 compare match TCMMLCM_2 overflow TCMMINCM_2 underflow TCMCNT_2 overflow TCMICR_3 input capture TCMMLCM_3 compare match TCMMLCM_3 overflow TCMMINCM_3 underflow TCMCNT_3 overflow Interrupt Flag ICPF_0 CMF_0 MAXOVF_0 MINUDF_0 OVF_0 ICPF_1 CMF_1 MAXOVF_1 MINUDF_1 OVF_1 ICPF_2 CMF_2 MAXOVF_2 MINUDF_2 OVF_2 ICPF_3 CMF_3 MAXOVF_3 MINUDF_3 OVF_3 Low Priority High Rev. 1.00 Apr. 28, 2008 Page 324 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6 11.6.1 Usage Notes Conflict between TCMCNT Write and Count-Up Operation When a conflict between TCMCNT write and count-up operation occurs in the second half of the TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority. Figure 11.13 shows the timing of this conflict. T1 Internal write signal Internal clock TCMCNT input clock TCMCNT N-1 N N+1 T2 Figure 11.13 Conflict between TCMCNT Write and Count-Up Operation 11.6.2 Conflict between TCMMLCM Write and Compare Match When a conflict between TCMMLCM write and a compare match should occur in the second half of a cycle of writing to TCMMLCM, writing to TCMMLCM takes priority and the compare match signal is inhibited. Figure 11.14 shows the timing of this conflict. T1 Internal write signal TCMCNT TCMMLCM Compare match signal N N Inhibited N+1 M N+2 T2 Figure 11.14 Conflict between TCMMLCM Write and Compare Match Rev. 1.00 Apr. 28, 2008 Page 325 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.3 Conflict between TCMICR Read and Input Capture When operation is in timer mode and the corresponding input capture signal is detected during reading of TCMICR, the input capture signal is delayed by one system clock (). Figure 11.15 shows the timing of this conflict. TCMCYI TCMICR read signal Input capture signal TCMCNT TCMICR ICPF N-1 M N Capture generated N+1 N N+2 Figure 11.15 Conflict between TCMICR Read and Input Capture 11.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to TCMMLCM or TCMMINCM If the selected edge of TCMCYI is detected in the second half of a cycle of writing to the register (TCMMLCM or TCMMINCM) in cycle measurement mode, the detected edge signal is delayed by one cycle of the system clock (). Figure 11.16 shows the timing of this conflict. TCMCYI Internal write signal Input capture signal TCMCNT TCMICR MAXOVF N M Capture generated H'0000 N TCMICR > TCMCNT (Upper liit over) Figure 11.16 Conflict between Edge Detection and Register Write (Cycle Measurement Mode) Rev. 1.00 Apr. 28, 2008 Page 326 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) 11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and Clearing of TCMMDS Bit in TCMCR If the CST bit in TCMCR is set to 1 in cycle measurement mode, and the TCMMDS bit in TCMCR is cleared, but the selected edge from TCMCYI is detected at the same time, detection of the selected edge will cause the timer to continue to operate in cycle measurement mode. The timer will not make the transition to timer mode until the next detection of the selected edge. Thus, ensure that the CST bit is cleared to 0 in cycle measurement mode. Figure 11.17 shows the timing of this conflict. TCMCYI Internal write signal Input capture signal TCMMDS TCMCNT cleared at the first rising edge TCMCNT not cleared TCMCNT TCMICR M L H'0000 M N N N+1 Figure 11.17 Conflict between Edge Detection and Clearing of TCMMDS (to Switch from Cycle Measurement Mode to Timer Mode) 11.6.6 Settings of TCMCKI and TCMMCI TCMCKI and TCMMCI are multiplexed on the same pin of this LSI. Therefore, the selected external clock and the TCMMCI signal cannot be used at the same time. Do not make the settings CKS2 to CKS0 = B'111 and CMMS = B'1. 11.6.7 Setting for Module Stop Mode The module-stop control register can be used to select either continuation or stoppage of TCM operation in module-stopped mode. The default setting is for TCM operation to stop. TCM registers become accessible on release from module stop mode. For details, see section 26, PowerDown Modes. Rev. 1.00 Apr. 28, 2008 Page 327 of 994 REJ09B0452-0100 Section 11 16-Bit Cycle Measurement Timer (TCM) Rev. 1.00 Apr. 28, 2008 Page 328 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Section 12 16-Bit Duty Period Measurement Timer (TDP) This LSI has a three-channel, 16-bit duty period measurement timer (TDP). The TDP uses a 16-bit counter as the basis for measuring input waveforms and the pulse width. 12.1 * * * * * Features Capable of measuring input-waveform periods and the pulse width Selectable measured edge 16-bit compare match 16-bit resolution Selectable counter clock Any of seven internal clocks or an external clock can be selected. * Seven interrupt sources Counter overflow Cycle upper limit overflow Cycle lower limit underflow Pulse width upper limit overflow Pulse width lower limit underflow Compare match Generation of input capture Rev. 1.00 Apr. 28, 2008 Page 329 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.1 shows a block diagram of the TDP. External clock TDPCKI Clock selection Overflow Clear Compare match Comparator Internal clock , /2, /4, /8, /16, /32, /64 TDPCNT TDPMCI TDPWDMX TDPWDMN TDPPDMX TDPPDMN Control logic TDPCYI Input capture TDPICR TDPICRF TDPCSR TDPCR1 TDPCR2 TDPIER TICI TCMI TWDMXI TWDMNI TPDMXI TPDMNI TOVI [Legend] TDPCNT: Timer counter TDPPDMX: Cycle upper limit register TDPPDMN: Cycle lower limit register TDPWDMX: Pulse width upper limit register TDPWDMN: Pulse width lower limit register TDPICR: Input capture register TDPICRF:Input capture buffer register TDPCSR: Status register TDPCR1: Control register 1 TDPCR2: Control register 2 TDPIER: Interrupt enable register Figure 12.1 Block Diagram of TDP Rev. 1.00 Apr. 28, 2008 Page 330 of 994 REJ09B0452-0100 Module data bus Cycle upper limit overflow Cycle lower limit underflow Pulse width upper limit overflow Pulse width lower limit underflow Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the TDP. Table 12.1 Pin Configuration Channel 0 Pin Name TDPCKI0 (TDPMCI0) TDPCYI0 1 TDPCKI1 (TDPMCI1) TDPCYI1 2 TDPCKI2 (TDPMCI2) TDPCYI2 I/O Input Input Input Input Input Input Function External counter clock input Cycle measurement control input External event input External counter clock input Cycle measurement control input External event input External counter clock input Cycle measurement control input External event input 12.3 Register Descriptions The TDP has the following registers. Table 12.2 Register Configuration Initial Value H'0000 Data Bus Address Width H'FB40 16 16 16 16 16 16 16 8 8 8 8 Channel Channel 0 Register Name TDP timer counter_0 TDP pulse width upper limit register_0 TDP pulse width lower limit register_0 TDP cycle upper limit register_0 TDP cycle lower limit register_0 TDP input capture register_0 TDP input capture buffer register_0 TDP status register_0 TDP control register1_0 TDP control register2_0 TDP interrupt enable register_0 Abbreviation TDPCNT_0 TDPWDMX_0 TDPWDMN_0 TDPPDMX_0 TDPPDMN_0 TDPICR_0 TDPICRF_0 TDPCSR_0 TDPCR1_0 TDPCR2_0 TDPIER_0 R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W H'FFFF H'FB42 H'0000 H'FB44 H'FFFF H'FB46 H'0000 H'0000 H'0000 H'00 H'00 H'00 H'00 H'FB50 H'FB48 H'FB4A H'FB4C H'FB4D H'FB4F H'FB4E Rev. 1.00 Apr. 28, 2008 Page 331 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Channel Channel 1 Register Name TDP timer counter_1 TDP pulse width upper limit register_1 TDP pulse width lower limit register_1 TDP cycle upper limit register_1 TDP cycle lower limit register_1 TDP input capture register_1 TDP input capture buffer register_1 TDP status register_1 TDP control register1_1 TDP control register2_1 TDP interrupt enable register_1 Abbreviation TDPCNT_1 TDPWDMX_1 TDPWDMN_1 TDPPDMX_1 TDPPDMN_1 TDPICR_1 TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPCR2_1 TDPIER_1 R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W Initial Value H'0000 Data Bus Address Width H'FB60 16 16 16 16 16 16 16 8 8 8 8 H'FFFF H'FB62 H'0000 H'FB64 H'FFFF H'FB66 H'0000 H'0000 H'0000 H'00 H'00 H'00 H'00 H'FB70 H'FB68 H'FB6A H'FB6C H'FB6D H'FB6F H'FB6E Channel 2 TDP timer counter_2 TDP pulse width upper limit register_2 TDPCNT_2 R/W H'0000 H'FB80 H'FFFF H'FB82 H'0000 H'FB84 H'FFFF H'FB86 H'0000 H'FB90 H'0000 H'FB88 16 16 16 16 16 16 TDPWDMX_2 R/W TDP pulse width lower limit register_2 TDPWDMN_2 R/W TDP cycle upper limit register_2 TDP cycle lower limit register_2 TDP input capture register_2 TDP input capture buffer register_2 TDP status register_2 TDP control register 1_2 TDP control register 2_2 TDP interrupt enable register_2 TDPPDMX_2 R/W TDPPDMN_2 R/W TDPICR_2 TDPICRF_2 TDPCSR_2 TDPCR1_2 TDPCR2_2 TDPIER_2 R R R/W R/W R/W R/W H'0000 H'FB8A 16 H'00 H'00 H'00 H'00 H'FB8C 8 H'FB8D 8 H'FB8F 8 H'FB8E 8 Rev. 1.00 Apr. 28, 2008 Page 332 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.1 TDP Timer Counter (TDPCNT) TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or falling edge is selected by CKSEG in TDPCSR. When TDPCNT overflows (H'FFFF changes to H'0000), the OVF flag in TDPCSR is set to 1. In timer mode, TDPCNT is initialized to H'0000 when the CST bit in TDPCR1 is cleared. In cycle measurement mode, TDPCNT is cleared when the first edge (the edge selected by the IEDG bit in TDPCR1) of the measurement period (equal to one input waveform period) is detected. In timer mode, TDPCNT is always writable. In cycle measurement mode, TDPCNT cannot be modified. TDPCNT must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPCNT is initialized to H'0000. 12.3.2 TDP Pulse Width Upper Limit Register (TDPWDMX) TDPWDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is cleared (timer mode), TDPWDMX is available as a compare match register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPWDMX is available as a pulse width upper limit register. In timer mode, the TDPWDMX value is continually compared with the TDPCNT value. If the values match, the CMF flag in TDPCSR is set to 1. Note, however, that comparison is disabled in the second half of a write cycle to TDPWDMX. In cycle measurement mode, TDPWDMX can be used to set the upper limit value of the measurement pulse width. When the second edge (the second edge of this period) of the measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPWDMX are compared. If the TDPICR value is greater than the TDPWDMX value, the TWDMXOVF flag in TDPCSR is set to 1. TDPWDMX must always be accessed in 16bit units and cannot be accessed in 8-bit units. TDPWDMX is initialized to H'FFFF. Rev. 1.00 Apr. 28, 2008 Page 333 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.3 TDP Pulse Width Lower Limit Register (TDPWDMN) TDPWDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPWDMN is available as a pulse width lower limit register. In cycle measurement mode, TDPWDMN can be used to set the lower limit value of measurement pulse width. When the second edge (the second edge of this period) of the measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPWDMN are compared. If the TDPICR value is less than the TDPWDMN value, the TWDMNUDF flag in TDPCSR is set to 1. TDPWDMN must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPWDMN is initialized to H'0000. 12.3.4 TDP Cycle Upper Limit Register (TDPPDMX) TDPPDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPPDMX is available as a cycle upper limit register. In cycle measurement mode, TDPPDMX can be used to set the upper limit value of measurement period. When the third edge (the first edge of the next period) of the measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPPDMX are compared. If the TDPICR value is greater than the TDPPDMX value, the TPDMXOVF flag in TDPCSR is set to 1. TDPPDMX must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPPDMX is initialized to H'FFFF. 12.3.5 TDP Cycle Lower Limit Register (TDPPDMN) TDPPDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1 (cycle measurement mode), TDPPDMN is available as a cycle lower limit register. In cycle measurement mode, TDPPDMN can be used to set the lower limit value of measurement period. When the third edge (the first edge of the next period) of the measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPPDMN are compared. If the TDPICR value is less than the TDPPDMN value, the TPDMNUDF flag in TDPCSR is set to 1. TDPPDMN must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPPDMN is initialized to H'0000. Rev. 1.00 Apr. 28, 2008 Page 334 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.6 TDP Input Capture Register (TDPICR) TDPICR is a 16-bit read-only register. In timer mode, the TDPCNT value is transferred to TDPICR on the edge selected by the IEDG bit in TDPCR1, and the ICPF flag in TDPCSR is set to 1. In cycle measurement mode, the TDPCNT value is transferred to TDPICR when the first edge of the measurement period is detected. At the same time, the ICPF flag in TDPCSR is set to 1. TDPICR must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPICR is initialized to H'0000. 12.3.7 TDP Input Capture Buffer Register (TDPICRF) TDPICRF is a 16-bit read-only register. TDPICRF can be used as a TDPICR buffer register. When input capture occurs, the TDPICR value is transferred to TDPICRF. TDPICRF must always be accessed in 16-bit units and cannot be accessed in 8-bit units. TDPICRF is initialized to H'0000. 12.3.8 TDP Status Register (TDPCSR) TDPCSR indicates the status flags and selects the external clock edge. Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Timer Overflow This flag indicates a TDPCNT overflow. [Setting condition] * * TDPCNT overflow (H'FFFF changes to H'0000) Reading OVF when OVF = 1 and then writing 0 to OVF [Clearing condition] 6 TWDMXOVF 0 R/(W)* Pulse Width Upper Limit Overflow This flag indicates that the waveform pulse width measured in cycle measurement mode has exceeded the upper limit specified in TDPWDMX. [Setting condition] * * When TDPICR is greater than TDPWDMX Reading TWDMXOVF when TWDMXOVF = 1 and then writing 0 to TWDMXOVF [Clearing condition] Rev. 1.00 Apr. 28, 2008 Page 335 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit 5 Bit Name TWDMNUDF Initial Value 0 R/W Description R/(W)* Pulse Width Lower Limit Underflow This flag indicates that the waveform pulse width measured in cycle measurement mode is below the lower limit specified in TDPWDMN. [Setting condition] * * When TDPICR is less than TDPWDMN Reading TWDMNUDF when TWDMNUDF = 1 and then writing 0 to TWDMNUDF [Clearing condition] 4 TPDMXOVF 0 R/(W)* Cycle Upper Limit Overflow This flag indicates that the waveform period measured in cycle measurement mode has exceeded the upper limit specified in TDPPDMX. [Setting condition] * * When TDPICR is greater than TDPPDMX Reading TPDMXOVF when TPDMXOVF = 1 and then writing 0 to TPDMXOVF Input Capture Generation In timer mode, this flag indicates that the value in TDPCNT was transferred to TDPICR when an input capture signal was generated. This flag is set when the input capture signal selected by the IEDG bit is generated on the TDPCYI input pin. In cycle measurement mode, this flag indicates that the value in TDPCNT was transferred to TDPICR when the rising or falling edge of the PWM waveform was detected. [Setting condition] * * When an input capture signal is generated Reading ICPF when ICPF = 1 and then writing 0 to ICPF [Clearing condition] [Clearing condition] 3 ICPF 0 R/(W)* Rev. 1.00 Apr. 28, 2008 Page 336 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit 2 Bit Name CMF Initial Value 0 R/W R/(W)* Description Compare Match Flag (valid only in timer mode) [Setting condition] * When the TDPCNT value matches the TDPWDMX value in timer mode Reading CMF when CMF = 1 and then writing 0 to CMF [Clearing condition] * Note: In cycle measurement mode, even though the TDPCNT value matches the TDPWDMX value, CMF is not set to 1. 1 CKSEG 0 R/(W)* External Clock Edge Select When CKS2 to CKS0 in TDPCR1 are set to B'111 (external clock), this bit selects the edge for counting of the external count clock edges. 0: Falling edges of the external clock are counted 1: Rising edges of the external clock are counted 0 TPDMNUDF 0 R/(W)* Cycle Lower Limit Underflow This flag indicates that the waveform period measured in cycle measurement mode is below the lower limit specified in TDPPDMN. [Setting condition] * * When TDPICR is less than TDPPDMN Reading TPDMNUDF when TPDMNUDF = 1 and then writing 0 to TPDMNUDF [Clearing condition] Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 337 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.9 TDP Control Register 1 (TDPCR1) TDPCR1 selects the input capture input edge, starts the TDPCNT counter, selects the counter clock, and controls the operating mode. Bit 7 Bit Name CST Initial Value 0 R/W R/W Description Counter Start In timer mode, setting this bit to 1 starts counting by TDPCNT, and clearing it stops counting. After the bit is cleared, the counter is initialized to H'0000, and the inputcapture operation stops. Clear this bit to initialize TDPCNT to H'0000 before setting to cycle measurement mode. 6 POCTL 0 R/W TDPCYI Input Polarity Inversion 0: TDPCYI input is used directly 1: TDPCYI input is inverted for use Note: Change this bit when CST = 0 and TDPMDS = 0. 5 CPSPE 0 R/W Input Capture Stop Enable Controls whether counting up by TDPCNT and inputcapture operation stop or continue when any of the TPDMXOVF, TPDMNUDF, TWDMXOVF, and TWDMNUDF flags is set to 1 in cycle measurement mode. This bit does not affect operation in timer mode. 0: Counting up and input-capture operation continue when any of the flags is set to 1. 1: Counting up and input-capture operation stop when any of the flags is set to 1. Rev. 1.00 Apr. 28, 2008 Page 338 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Bit 4 Bit Name IEDG Initial Value 0 R/W R/W Description Input Edge Select In timer mode, in combination with the value of the POCTL bit, selects the falling or rising edge of the TDPCYI input for capturing input. In cycle measurement mode, this bit does not affect operation. When POCTL = 0 0: The falling edge of TDPCYI input is selected 1: The rising edge of TDPCYI input is selected When POCTL = 1 0: The rising edge of TDPCYI input is selected 1: The falling edge of TDPCYI input is selected 3 TDPMDS 0 R/W TDP Mode Select Selects the TDP operating mode. 0: Timer mode In timer mode, the operating mode is input capture and compare match. 1: Cycle measurement mode Setting this bit to 1 starts counting by TDPCNT. Clear the CST bit in TDPCR1 to initialize TDPCNT to H'0000 before setting cycle measurement mode. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2, 1, 0 These bits select the clock signal for input to TDPCNT. Do not select the external clock in level control measurement mode. 000: Counts the internal clock 001: Counts the /2 internal clock 010: Counts the /4 internal clock 011: Counts the /8 internal clock 100: Counts the /16 internal clock 101: Counts the /32 internal clock 110: Counts the /64 internal clock 111: Counts the external clock (Select the external clock edge with CKSEG in TDPCSR.) Note: Change this bit when CST = 0 and TDPMDS = 0. Rev. 1.00 Apr. 28, 2008 Page 339 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.10 TDP Control Register 2 (TDPCR2) TDPCR2 selects cycle measurement mode and controls the TDPMCI input polarity. Bit 7 Bit Name PMMS Initial Value 0 R/W R/W Description Cycle Measurement Mode Select Selects whether to use the TDPMCI signal in cycle measurement mode. 0: The TDPMCI signal is not used (cycle measurement is always performed). 1: The TDPMCI signal is used (cycle measurement is performed only while the TDPMCI signal is high). Note: Change this bit when CST = 0 and TDPMDS = 0. 6 MCICTL 0 R/W TDPMCI Input Polarity Inversion 0: TDPMCI input is used directly 1: TDPMCI input is inverted for use Note: Change this bit when CST = 0 and TDPMDS = 0. 5 to 1 0 0 0 R/W R Reserved The initial value should not be changed. Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 340 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.3.11 TDP Interrupt Enable Register (TDPIER) TDPIER enables or disables interrupt requests and controls whether to enable or disable external event input. Bit 7 Bit Name OVIE Initial Value R/W 0 R/W Description Counter Overflow Interrupt Enable Enables or disables the issuing of OVF interrupt requests when the OVF flag in TDPCSR is set to 1. 0: OVF interrupt requests are disabled 1: OVF interrupt requests are enabled 6 TWDMXIE 0 R/W Pulse Width Upper Limit Overflow Interrupt Enable Enables or disables the issuing of TWDMXOVF interrupt requests when the TWDMXOVF flag in TDPCSR is set to 1. 0: TWDMXOVF interrupt requests are disabled 1: TWDMXOVF interrupt requests are enabled 5 TWDMNIE 0 R/W Pulse Width Lower Limit Underflow Interrupt Enable Enables or disables the issuing of TWDMNUDF interrupt requests when the TWDMNUDF flag in TDPCSR is set to 1. 0: TWDMNUDF interrupt requests are disabled 1: TWDMNUDF interrupt requests are enabled 4 TPDMXIE 0 R/W Cycle Upper Limit Overflow Interrupt Enable Enables or disables the issuing of TPDMXOVF interrupt requests when the TPDMXOVF flag in TDPCSR is set to 1. 0: TPDMXOVF interrupt requests are disabled 1: TPDMXOVF interrupt requests are enabled 3 ICPIE 0 R/W Input Capture Interrupt Enable Enables or disables the issuing of ICPF interrupt requests when the ICPF flag in TDPCSR is set to 1. 0: ICPF interrupt requests are disabled 1: ICPF interrupt requests are enabled 2 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables the issuing of CMF interrupt requests when the CMF flag in TDPCSR is set to 1. 0: CMF interrupt requests are disabled 1: CMF interrupt requests are enabled Rev. 1.00 Apr. 28, 2008 Page 341 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 1 TDPIPE 0 R/W Input Capture Input Enable Enables or disables TDPCYI pin input. To use input capture and cycle measurement mode, set this bit to 1. 0: Disabled 1: Enabled Note: Change this bit when CST = 0 and TDPMDS = 0. 0 TPDMNIE 0 R/W Cycle Lower Limit Underflow Interrupt Enable Enables or disables the issuing of TPDMNUDF interrupt requests when the TPDMNUDF flag in TDPCSR is set to 1. 0: TPDMNUDF interrupt requests are disabled 1: TPDMNUDF interrupt requests are enabled Rev. 1.00 Apr. 28, 2008 Page 342 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.4 Operation The TDP operates in timer mode or cycle measurement mode. After a reset, the TDP is in timer mode. 12.4.1 Timer Mode When the TDPMDS bit in TDPCR1 is cleared to 0, the TDP operates in timer mode. (1) Counter Operation The TDP operates as a free-running counter in timer mode. The TDP starts counting up when the CST bit in TDPCR1 is set to 1. When TDPCNT overflows (H'FFFF changes to H'0000), the OVF bit in TDPCSR is set to 1 and an interrupt request is generated if the OVIE bit in TDPIER is 1. Figure 12.2 shows an example of free-running counter operation. In addition, figure 12.3 shows TDPCNT count timing for external clock operation. Note that the external clock requires a pulse width of at least 1.5 cycles. The counter will not operate correctly if the pulses are narrower than this. /4 TDPCNT input clock TDPCNT N-1 N N+1 Figure 12.2 Example of Free-Running Counter Operation TDPCKI TDPCNT input clock TDPCNT N-1 N N+1 Figure 12.3 Count Timing of External Clock Operation (Falling Edges) Rev. 1.00 Apr. 28, 2008 Page 343 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) (2) Input Capture The value in TDPCNT is transferred to TDPICR by detecting the input edge of the TDPCYI pin in timer mode. At the same time, the ICPF flag in TDPCSR is set. Detection of rising or falling edges is selectable by setting the IEDG bit in TDPCR1. Figure 12.4 shows an example of the timing of input capture operations, and figure 12.5 shows an example of buffer operation for input capture. TDPCYI Input capture signal TDPCNT TDPICR ICPF N-1 M N N+1 N N+2 N+3 Figure 12.4 Example of Input Capture Operation Timing (Selection of Rising Edges) TDPCYI Input capture signal TDPCNT TDPICR TDPICRF N-1 M L N N M 0 0+1 0 N Figure 12.5 Example of Buffer Operation for Input Capture Rev. 1.00 Apr. 28, 2008 Page 344 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) (3) CMF Setting Timing when a Compare Match Occurs The CMF flag in TDPCSR is set in the last state in which the values in TDPCNT and TDPWDMX match (timing when TDPCNT updates the matched count value) in timer mode. Accordingly, a compare match signal is not generated until an additional cycle of the TDPCNT input clock is generated after a match between the values in TDPCNT and TDPWDMX. For details, see section 12.6.2, Conflict between TDPPDMX Write and Compare Match. Figure 12.6 shows the timing on which the CMF flag is set. TDPCNT TDPWDMX Compare match signal CMF N N N+1 Figure 12.6 Timing of CMF Flag Setting on Compare Match 12.4.2 Cycle Measurement Mode The TDP operates in cycle measurement mode when the TDPMDS bit in TDPCR1 is set to 1. (1) Counter Operation TDPCNT counts up in cycle measurement mode regardless of the setting of the CST bit in TDPCR1. TDPCNT is cleared to H'0000 when the first edge in the measurement period is detected, from which state it counts up. Figure 12.7 shows an example of counter operation in cycle measurement mode. TDPCYI TDPCNT clear signal TDPCNT input clock TDPCNT N H'0000 H'0001 H'0002 H'0003 H'0000 H'0001 Figure 12.7 Example of Counter Operation in Cycle Measurement Mode Rev. 1.00 Apr. 28, 2008 Page 345 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) (2) Measuring a Cycle In cycle measurement mode, one cycle of the TDP input waveform forms one measurement cycle. Start by setting TDPMDS = 0 and CST = 0, which clears TDPCNT to H'0000. Next, set the upper limit and lower limit values of the measurement pulse width in TDPWDMX and TDPWDMN, and set the upper limit and lower limit values of the measurement cycle in the TDPPDMX and TDPPDMN. Finally, place the TDP in cycle measurement mode by setting the TDPMDS bit in TDPCR1 to 1. TDPCNT will count up cycles of the selected clock. When the first edge (either rising or falling, as selected by the POCTL bit in TDPCR1) of the measurement cycle is detected, TDPCNT is automatically cleared to H'0000. When the second edge is detected, the value in TDPCNT is transferred to TDPICR. At this time, the value in TDPICR is compared with the values in TDPWDMX and TDPWDMN. If TDPIR is greater than TDPWDMX or less than TDPWDMN, the TWDMXOVF or TWDMNUDF flag, respectively, in TDPCSR is set to 1. When the third edge is detected, the value in TDPCNT is transferred to TDPICR. At this time, the value in TDPICR is compared with the values in TDPPDMX and TDPPDMN. If TDPICR is greater than TDPPDMX or less than TDPPDMN, the TPDMXOVF or TPDMNUDF flag, respectively, in TDPCSR is set to 1. Generation of the corresponding interrupt request is enabled by the setting in TDPIER. Also, when the third edge is detected, TDPCNT is cleared to H'0000, and the next round of measurement starts. When the CPSPE bit in TDPCR1 is cleared to 0, the next round of cycle measurement will start regardless of whether any of these flags is set to 1. If any of these flags is set to 1 while the CPSPE bit in TDPCR1 is set to 1, counting up by TDPCNT stops and cycle measurement also stops. Subsequently clearing the corresponding flag to 0 automatically clears TDPCNT to H'0000, and counting up for cycle measurement is restarted. Rev. 1.00 Apr. 28, 2008 Page 346 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Figure 12.8 shows an example of timing in cycle measurement. TDPCYI TDPCNT clear signal TDPCNT input clock TDPCNT TDPICR M L H'0000 M H'0001 N-1 1 N H'0000 N H'0001 TDPWDMX/TDPWDMN/ TDPPDMX/TDPPDMN TDPICRF K L M 1 Figure 12.8 Example of Timing in Cycle Measurement When the PMMS bit in TDPCR2 is set to 1, cycle measurement is performed only while the TDPMCI signal is high. Figure 12.9 shows an example of timing in cycle measurement when the PMMS bit is set to 1. TDPCYI TDPMCI TDPCNT TDPICR M L 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9AB0 1 2 3 4 5 M H'0003 H'0007 H'0005 H'000B H'0006 H'0003 Figure 12.9 Example of Timing in Cycle Measurement (PMMS Bit = 1). Rev. 1.00 Apr. 28, 2008 Page 347 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) (3) Determination of External Event (TDPCYI) Stoppage Stoppage for an external event (TDPCYI) can be determined from the timer overflow flag. There are two types of such stoppage. Stoppage for an external event can be considered to have occurred when the timer overflows within the period from the start of cycle measurement mode to the detection of the first edge (rising or falling, as selected by the POCTL bit in TDPCR1). Figure 12.10 shows an example of the timing of this type of stoppage for an external event. TDPCYI TDPMDS TDPCNT OVF TWDMXOVF/TWDMNUDF/ TPDMXOVF/TPDMNUDF H'0000 H'FFFF H'0000 N H'0000 H'0001 H'0002 Start of measurement Stoppage for an external event can be determined. Figure 12.10 Example of Timing for Stoppage for an External Event (1) When any of the TWDMXOVF, TWDMNUDF, TPDMXOVF, and TPDMNUDF flags is set to 1 while the CPSPE bit in TDPCR1 is 1, cycle measurement stops. Thereafter, when the corresponding flag is cleared, cycle measurement restarts. When the timer overflows before the first edge is detected after the restart of cycle measurement, it is possible to determine stoppage for an external event. Figure 12.11 shows an example of the timing for this type of stoppage for an external event. TDPCYI CPSPE TDPCNT OVF TWDMXOVF/TWDMNUDF/ TPDMXOVF/TPDMNUDF Restart of measurement H'5555 H'0000 H'FFFF H'0000 N H'0000 H'0001 Start of measurement Stoppage for an external event can be determined Figure 12.11 Example of Timing for Stoppage for an External Event (2) Rev. 1.00 Apr. 28, 2008 Page 348 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) (4) Setting Example of Setting Cycle Measurement Mode Figure 12.12 shows an example of a flowchart for using cycle measurement mode. Start Initial setting Set TDPMDS = 0 Set CST = 0 Set TDPWDMX Set TDPIPE = 1 Set OVIE = 1 and TWDMXIE = 1 Set TDPMDS = 1 OVF = 1 or TWDMXOVF = 1? No Set TDPMDS = 0 End of measurement [9] TWDMXOVF = 1? No Processing for external event stopped state [7] Processing for exceeded upper limit of pulse width [8] [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] [6] [7] Set timer mode. Stop TDPCNT and initialize it to H'0000. Set pulse width upper limit value. Pin input enabled. Enable interrupt requests. Set to cycle measurement mode. Start cycle measurement. Processing for external event-stopped state Processing for exceeded pulse width upper limit End of cycle measurement [6] [8] [9] Yes Interrupt occurs Yes End of exception handling Figure 12.12 Example of Cycle Measurement Mode Settings (for Pulse Width Upper-Limit Value) Rev. 1.00 Apr. 28, 2008 Page 349 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.5 Interrupt Sources The TDP has seven interrupt sources; TICI, TCMI, TWDMXI, TWDMNI, TPDMXI, TPDNMI, and TOVI. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TDPIER and is independently transferred to the interrupt controller. Table 12.3 lists the interrupt sources in order of priority. Table 12.3 TDP Interrupt Sources Channel TDP_0 Name TICI0 TCMI0 TWDMXI0 TWDMNI0 TPDMXI0 TPDMNI0 TOVI0 TDP_1 TICI1 TCMI1 TWDMXI1 TWDMNI1 TPDMXI1 TPDMNI1 TOVI1 TDP_2 TICI2 TCMI2 TWDMXI2 TWDMNI2 TPDMXI2 TPDMNI2 TOVI2 Interrupt Source TDPICR_0 input capture Interrupt Flag ICPF_0 Priority High TDPWDMX_0 compare match CMF_0 TDPWDMX_0 overflow TDPWDMN_0 underflow TDPPDMX_0 overflow TDPPDMN_0 underflow TDPCNT_0 overflow TDPICR_1 input capture TWDMXOVF_0 TWDMNUDF_0 TPDMXOVF_0 TPDMNUDF_0 OVF_0 ICPF_1 TDPWDMX_1 compare match CMF_1 TDPWDMX_1 overflow TDPWDMN_1 underflow TDPPDMX_1 overflow TDPPDMN_1 underflow TDPCNT_1 overflow TDPICR_1 input capture TWDMXOVF_1 TWDMNUDF_1 TPDMXOVF_1 TPDMNUDF_1 OVF_1 ICPF_2 TDPWDMX_2 compare match CMF_2 TDPWDMX_2 overflow TDPWDMN_2 underflow TDPPDMX_2 overflow TDPPDMN_2 underflow TDPCNT_2 overflow TWDMXOVF_2 TWDMNUDF_2 TPDMXOVF_2 TPDMNUDF_2 OVF_2 Low Rev. 1.00 Apr. 28, 2008 Page 350 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6 12.6.1 Usage Notes Conflict between TDPCNT Write and Count-Up Operation If a conflict between a TDPCNT write and counting up operation occurs in the second half of the TDPCNT write cycle, writing to TDPCNT takes precedence and TDPCNT is not incremented. Figure 12.13 shows the timing of this conflict. T1 Internal write signal Internal clock TDPCNT input clock TDPCNT N-1 M M+1 Write data M T2 Figure 12.13 Conflict between TDPCNT Write and Counting Up 12.6.2 Conflict between TDPPDMX Write and Compare Match If a conflict between a TDPPDMX write and a compare match occurs in the second half of the TDPPDMX write cycle, writing to TDPPDMX takes precedence and the compare match signal is inhibited. Figure 12.14 shows the timing of this conflict. T1 Internal write signal TDPCNT TDPPDMX Compare match signal N N Inhibited N+1 M N+ 2 T2 Figure 12.14 Conflict between TDPPDMX Write and Compare Match Rev. 1.00 Apr. 28, 2008 Page 351 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.3 Conflict between Input Capture and TDPICR Read When the corresponding input capture signal is detected during reading of TDPICR in timer mode, the input capture signal is delayed by one cycle of the system clock (). Figure 12.15 shows the timing of this conflict. TDPCYI TDPICR read signal Input capture signal TDPCNT TDPICR ICPF N-1 M N Capture occurs N+1 N N+2 Figure 12.15 Conflict between Input Capture and TDPICR Read 12.6.4 Conflict between Edge Detection in Cycle Measurement Mode and Writing to the Upper Limit or Lower Limit Register If the edge of TDPCYI is detected in the second half of a cycle of writing to any of the upper limit/lower limit registers (TDPPDMX, TDPPDMN, TDPWDMX, and TDPWDMN) in cycle measurement mode, the detected edge signal is delayed by one cycle of the system clock (). Figure 12.16 shows the timing of this conflict. TDPCYI Internal write signal Input capture signal TDPCNT TDPICR TPDMXOVF N M Capture occurs H'0000 N TDPICR > TDPPDMX (Cycle upper limit exceeded) Figure 12.16 Conflict between Edge Detection and Register Write (Cycle Measurement Mode) Rev. 1.00 Apr. 28, 2008 Page 352 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) 12.6.5 Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit Clearing When the TDPMDS bit in TDPCR1 is cleared in cycle measurement mode while the CST bit in TDPCR1 is 1 and the edge of TDPCYI is detected at the same time, the detected edge signal will cause the timer to continue to operate in cycle measurement mode. The timer enters timer mode when the next edge is detected. Therefore, ensure that the CST bit is cleared to 0 in cycle measurement mode. Figure 12.17 shows the timing of this conflict. TDPCYI Input capture signal Internal write signal TDPMDS TDPCNT cleared at the first rising edge TDPCNT is not cleared TDPCNT TDPICR M L H'0000 M N N N+1 Figure 12.17 Conflict between Edge Detection and TDPMDS Bit Clearing (In Switching from Cycle Measurement Mode to Timer Mode) 12.6.6 Settings for TDPCKI and TDPMCI TDPCKI and TDPMCI are multiplexed on the same pin of this LSI. Therefore, the selected external clock and the TDPMCI signal cannot be used at the same time. Do not make the settings CKS2 to CKS0 = B'111 and PMMS = B'1. 12.6.7 Setting for Module Stop Mode The module-stop control register can be used to specify whether to continue or stop TDP operation. The default setting is for the TDP operation to stop. The TDP registers become accessible on release from module stop mode. For details, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 353 of 994 REJ09B0452-0100 Section 12 16-Bit Duty Period Measurement Timer (TDP) Rev. 1.00 Apr. 28, 2008 Page 354 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Section 13 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, and TMR_X) with four channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.1 Features Selection of clock sources The counter input clock can be selected from six internal clocks and an external clock * Selection of three ways to clear the counters The counters can be cleared on compare-match A, compare-match B, or by an external reset signal. Timer output controlled by two compare-match signals The timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or PWM output with an arbitrary duty cycle. * Cascading of two channels Cascading of TMR_0 and TMR_1 Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode). TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count mode). Cascading of TMR_Y and TMR_X Operation as a 16-bit timer can be performed using TMR_Y as the upper half and TMR_X as the lower half (16-bit count mode). TMR_X can be used to count TMR_Y compare-match occurrences (compare-match count mode). * Multiple interrupt sources for each channel TMR_0, TMR_1, and TMR_Y: Three types of interrupts: Compare-match A, comparematch B, and overflow TMR_X: Four types of interrupts: Compare-match A, compare match B, overflow, and input capture Rev. 1.00 Apr. 28, 2008 Page 355 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Figures 13.1 and 13.2 show block diagrams of 8-bit timers. An input capture function is added to TMR_X. External clock sources TMI0 (TMCI0) TMI1 (TMCI1) Internal clock sources TMR_0 /2, /8, /32, /64, /256, /1024 TMR_1 /2, /8, /64, /128, /1024, /2048 Clock 1 Clock 0 Clock selection TCORA_0 Compare-match A1 Compare-match A0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare-match B1 Compare-match B0 TMO1 TMI1 (TMRI1) Control logic Comparator B_0 Comparator B_1 TCORA_1 Comparator A_0 Comparator A_1 TMO0 TMI0 (TMRI0) TCNT_0 TCNT_1 TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 [Legend] TCORA_0: TCORB_0: TCNT_0: TCSR_0: TCR_0: Time constant register A_0 Time constant register B_0 Timer counter_0 Timer control/status register_0 Timer control register_0 TCORA_1: TCORB_1: TCNT_1: TCSR_1: TCR_1: TCR_1 Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control/status register_1 Timer control register_1 Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) Rev. 1.00 Apr. 28, 2008 Page 356 of 994 REJ09B0452-0100 Internal bus Section 13 8-Bit Timer (TMR) External clock sources TMIY (TMCIY) TMIX (TMCIX) Internal clock sources TMR_X , /2, /4, /2048, /4096, /8192 TMR_Y /4, /256, /2048, /4096, /8192, /16384 Clock selection Clock X Clock Y TCORA_Y Compare-match AX Compare-match AY Overflow X Overflow Y Clear Y TCORA_X Comparator A_Y TCNT_Y Clear X Comparator A_X TCNT_X TMOY TMIY (TMRIY) Compare- match BX Compare-match BY Comparator B_Y TCORB_Y Comparator B_X TCORB_X TMOX TMIX (TMRIX) Control logic Input capture TICRR TICRF TICR Compare-match C Comparator C + TCORC TCSR_Y TCR_Y Interrupt signals CMIAY CMIBY OVIY ICIX [Legend] TCORA_Y: TCORB_Y: TCNT_Y: TCSR_Y: TCR_Y: TCORA_X: TCORB_X: Time constant register A_Y Time constant register B_Y Timer counter_Y Timer control/status register_Y Timer control register_Y Time constant register A_X Time constant register B_X TCNT_X: TCSR_X: TCR_X: TICR: TCORC: TICRR: TICRF: Timer counter_X Timer control/status register_X Timer control register_X Input capture register Time constant register C Input capture register R Input capture register F TCSR_X TCR_X Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) Rev. 1.00 Apr. 28, 2008 Page 357 of 994 REJ09B0452-0100 Internal bus Section 13 8-Bit Timer (TMR) 13.2 Input/Output Pins Table 13.1 summarizes the input and output pins of the TMR. Table 13.1 Pin Configuration Channel TMR_0 Pin Name TMO0 TMI0 (TMCI0/TMRI0) TMR_1 TMO1 TMI1 (TMCI1/TMRI1) TMR_Y TMIY (TMCIY/TMRIY) TMOY TMR_X TMOX TMIX (TMCIX/TMRIX) I/O Output Input Output Input Input Output Output Input Function Output controlled by compare-match External clock input/external reset input for the counter Output controlled by compare-match External clock input/external reset input for the counter External clock input/external reset input for the counter Output controlled by compare-match Output controlled by compare-match External clock input/external reset input for the counter Rev. 1.00 Apr. 28, 2008 Page 358 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Table 13.2 Register Configuration Initial Value H'00 H'FF H'FF H'00 H'00 H'00 H'FF H'FF H'00 H'10 H'00 H'FF H'FF H'00 H'00 H'00 Data Bus Width 16 16 16 8 8 16 16 16 8 8 8 8 8 8 8 8 Channel Register Name Abbreviation R/W TCNT_0 TCORA_0 TCORB_0 TCR_0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address H'FFD0 H'FFCC H'FFCE H'FFC8 H'FFCA H'FFD1 H'FFCD H'FFCF H'FFC9 H'FFCB H'FFF4 H'FECC* H'FFF2 H'FECA* H'FFF3 H'FECB* H'FFF0 H'FEC8* H'FFF1 H'FEC9* H'FFFE Channel 0 Timer counter_0 Time constant register A_0 Time constant register B_0 Timer control register_0 Timer control/status register_0 TCSR_0 Channel 1 Timer counter_1 Time constant register A_1 Time constant register B_1 Timer control register_1 TCNT_1 TCORA_1 TCORB_1 TCR_1 Timer control/status register_1 TCSR_1 Channel Y Timer counter_Y Time constant register A_Y Time constant register B_Y Timer control register_Y TCNT_Y TCORA_Y TCORB_Y TCR_Y Timer control/status register_Y TCSR_Y Timer connection register S Note: * TCONRS Upper address: when RELOCATE = 0 Lower address: when RELOCATE = 1 Rev. 1.00 Apr. 28, 2008 Page 359 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Channel Register Name Abbreviation R/W TCNT_X TCORA_X TCORB_X TCR_X R/W R/W R/W R/W R/W R/W R R R/W R/W Initial Value H'00 H'FF H'FF H'00 H'00 H'FF H'00 H'00 H'00 H'00 Address H'FFF4 H'FFF6 H'FFF7 H'FFF0 H'FFF1 H'FFF5 H'FFF2 H'FFF3 H'FFFC H'FEC6 Data Bus Width 8 8 8 8 8 8 8 8 8 8 Channel X Timer counter_X Time constant register A_X Time constant register B_X Timer control register_X Timer control/status register_X TCSR_X Time constant register Input capture register R Input capture register F Timer connection register I Common Timer XY control register TCORC TICRR TICRF TCONRI TCRXY Note: Some of the registers of TMR_X and TMR_Y use the same address. The registers can be switched by the TMRX/Y bit in TCONRS. TCNT_Y, TCORA_Y, TCORB_Y, and TCR_Y can be accessed when the RELOCATE bit in SYSCR3 and the KINWUE bit in SYSCR are cleared to 0 and the TMRX/Y bit in TCONRS is set to 1, or when the RELOCATE bit in SYSCR3 is set to 1. TCNT_X, TCORA_X, TCORB_X, and TCR_X can be accessed when the RELOCATE bit in SYSCR3, the KINWUE bit in SYSCR, and the TMRX/Y bit in TCONRS are cleared to 0, or when the RELOCATE bit in SYSCR3 is set to 1. 13.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_X and TCNT_Y) comprise a single 16-bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00. Rev. 1.00 Apr. 28, 2008 Page 360 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_X and TCORA_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by these compare-match A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF. 13.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_X and TCORB_Y) comprise a single 16-bit register, so they can be accessed together by word access. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by these compare-match B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF. Rev. 1.00 Apr. 28, 2008 Page 361 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. Bit 7 Bit Name CMIEB Initial Value 0 R/W R/W Description Compare-Match Interrupt Enable B Selects whether the CMFB interrupt request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt request (CMIB) is disabled 1: CMFB interrupt request (CMIB) is enabled 6 CMIEA 0 R/W Compare-Match Interrupt Enable A Selects whether the CMFA interrupt request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt request (CMIA) is disabled 1: CMFA interrupt request (CMIA) is enabled 5 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request (OVI) is enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt request (OVI) is disabled 1: OVF interrupt request (OVI) is enabled 4 3 CCLR1 CCLR0 0 0 R/W R/W Counter Clear 1 and 0 These bits select the method by which the timer counter is cleared. 00: Clearing is disabled 01: Cleared on compare-match A 10: Cleared on compare-match B 11: Cleared on rising edge of external reset input 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock input to TCNT and count condition, together with the ICKS1 and ICKS0 bits in STCR. For details, see table 13.3. Rev. 1.00 Apr. 28, 2008 Page 362 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Table 13.3 Clock Input to TCNT and Count Condition (1) TCR Channel CKS2 TMR_0 0 0 0 0 0 0 0 1 TMR_1 0 0 0 0 0 0 0 1 CKS1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 CKS0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 STCR ICKS1 -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- ICKS0 -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /32 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /256 Increments at overflow signal from TCNT_1* Disables clock input Increments at falling edge of internal clock /8 Increments at falling edge of internal clock /2 Increments at falling edge of internal clock /64 Increments at falling edge of internal clock /128 Increments at falling edge of internal clock /1024 Increments at falling edge of internal clock /2048 Increments at compare-match A from TCNT_0* Rev. 1.00 Apr. 28, 2008 Page 363 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) TCR Channel CKS2 Common 1 1 1 Note: * CKS1 0 1 1 CKS0 1 0 1 STCR ICKS1 -- -- -- ICKS0 -- -- -- Description Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. Table 13.3 Rev. 1.00 Apr. 28, 2008 Page 364 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Clock Input to TCNT and Count Condition (2) TCR Channel CKS2 TMR_Y 0 0 0 0 1 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 TCRXY CKSX -- -- -- -- -- -- -- -- -- -- -- -- -- CKSY 0 0 0 0 0 1 1 1 1 1 x x x Description Disables clock input Increments at /4 Increments at /256 Increments at /2048 Disables clock input Disables clock input Increments at /4096 Increments at /8192 Increments at /16384 Increments at overflow signal from TCNT_X* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock Rev. 1.00 Apr. 28, 2008 Page 365 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) TCR Channel CKS2 TMR_X 0 0 0 0 1 0 0 0 0 1 1 1 1 Note: * CKS1 0 0 1 1 0 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 0 1 0 1 0 1 0 1 TCRXY CKSX 0 0 0 0 0 1 1 1 1 1 x x x CKSY -- -- -- -- -- -- -- -- -- -- -- -- -- Description Disables clock input Increments at Increments at /2 Increments at /4 Disables clock input Disables clock input Increments at /2048 Increments at /4096 Increments at /8192 Increments at compare-match A from TCNT_Y* Increments at rising edge of external clock Increments at falling edge of external clock Increments at both rising and falling edges of external clock If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock cannot be generated. These settings should not be made. [Legend] x: Don't care : Invalid Rev. 1.00 Apr. 28, 2008 Page 366 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. * TCSR_0 Bit 7 Bit Name CMFB Initial Value 0 R/W Description [Setting condition] When the values of TCNT_0 and TCORB_0 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_0 and TCORA_0 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_0 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ADTE 0 R/W A/D Trigger Enable Enables or disables A/D converter start requests by compare-match A. 0: A/D converter start requests by compare-match A are disabled 1: A/D converter start requests by compare-match A are enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits specify how the TMO0 pin output level is to be changed by compare-match B of TCORB_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) R/(W)* Compare-Match Flag B Rev. 1.00 Apr. 28, 2008 Page 367 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Bit 1 0 Bit Name OS1 OS0 Initial Value 0 0 R/W R/W R/W Description Output Select 1 and 0 These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. * TCSR_1 Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 -- 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 368 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Bit 3 2 Bit Name OS3 OS2 Initial Value 0 0 R/W R/W R/W Description Output Select 3 and 2 These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. * TCSR_X Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA Rev. 1.00 Apr. 28, 2008 Page 369 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Bit 5 Bit Name OVF Initial Value 0 R/W Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICF 0 R/(W)* Input Capture Flag [Setting condition] When a rising edge and falling edge is detected in the external reset signal in that order. [Clearing condition] Read ICF when ICF = 1, then write 0 in ICF 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits specify how the TMOX pin output level is to be changed by compare-match B of TCORB_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Apr. 28, 2008 Page 370 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) * TCSR_Y Bit 7 Bit Name CMFB Initial Value 0 R/W Description R/(W)* Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB 6 CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICIE 0 R/W Input Capture Interrupt Enable Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1. 0: ICF interrupt request (ICIX) is disabled 1: ICF interrupt request (ICIX) is enabled 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits specify how the TMOY pin output level is to be changed by compare-match B of TCORB_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Rev. 1.00 Apr. 28, 2008 Page 371 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Bit 1 0 Bit Name OS1 OS0 Initial Value 0 0 R/W R/W R/W Description Output Select 1 and 0 These bits specify how the TMOY pin output level is to be changed by compare-match A of TCORA_Y and TCNT_Y. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing. 13.3.6 Time Constant Register C (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. 13.3.7 Input Capture Registers R and F (TICRR and TICRF) TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset input (TMRIX) in that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are initialized to H'00. Rev. 1.00 Apr. 28, 2008 Page 372 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.3.8 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit 7 to 5 4 Bit Name -- ICST Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF, respectively, and the ICST bit is cleared to 0. [Clearing condition] When a rising edge followed by a falling edge is detected on TMRIX [Setting condition] When 1 is written in ICST after reading ICST = 0 3 to 0 -- All 0 R/W Reserved The initial values should not be modified. 13.3.9 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit 7 Bit Name TMRX/Y Initial Value 0 R/W R/W Description TMR_X/TMR_Y Access Select For details, see table 13.4. 0: The TMR_X registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 1: The TMR_Y registers are accessed at addresses H'(FF)FFF0 to H'(FF)FFF5 6 to 0 All 0 R/W Reserved The initial values should not be modified. Rev. 1.00 Apr. 28, 2008 Page 373 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Table 13.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 0 1 TMR_X TCR_X TMR_Y TCR_Y H'FFF1 TMR_X TMR_Y H'FFF2 TMR_X TMR_Y H'FFF3 TMR_X TICRF TMR_Y H'FFF4 TMR_X TCNT TMR_Y H'FFF5 TMR_X TCORC TMR_Y H'FFF6 TMR_X H'FFF7 TMR_X TCSR_X TICRR TCORA_X TCORB_X TCSR_Y TCORA_Y TCORB_Y TCNT_Y 13.3.10 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock. Bit 7, 6 5 4 3 to 0 Bit Name CKSX CKSY -- Initial Value All 0 0 0 All 0 R/W R/W R/W R/W R/W Description Reserved The initial value should not be changed. TMR_X Clock Select For details about selection, see table 13.3. TMR_Y Clock Select For details about selection, see table 13.3. Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 374 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.4 13.4.1 Operation Pulse Output Figure 13.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared according to the compare match of TCORA. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB. According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width can be output without the intervention of software. TCNT H'FF TCORA TCORB H'00 Counter clear TMO Figure 13.3 Pulse Output Example Rev. 1.00 Apr. 28, 2008 Page 375 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.5 13.5.1 Operation Timing TCNT Count Timing Figure 13.4 shows the TCNT count timing with an internal clock source. Figure 13.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks () for a single edge and at least 2.5 system clocks () for both edges. The counter will not increment correctly if the pulse width is less than these values. Internal clock TCNT input clock TCNT N-1 N N+1 Figure 13.4 Count Timing for Internal Clock Input External clock input pin TCNT input clock TCNT N-1 N N+1 Figure 13.5 Count Timing for External Clock Input (Both Edges) Rev. 1.00 Apr. 28, 2008 Page 376 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.5.2 Timing of CMFA and CMFB Setting at Compare-Match The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCNT and TCOR values match. The compare-match signal is generated at the last state in which the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR match, the compare-match signal is not generated until the next TCNT input clock. Figure 13.6 shows the timing of CMF flag setting. TCNT N N+1 TCOR Compare-match signal CMF N Figure 13.6 Timing of CMF Setting at Compare-Match 13.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 13.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. Compare-match A signal Timer output pin Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal Rev. 1.00 Apr. 28, 2008 Page 377 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.5.4 Timing of Counter Clear at Compare-Match TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.8 shows the timing of clearing the counter by a compare-match. Compare-match signal TCNT N H'00 Figure 13.8 Timing of Counter Clear by Compare-Match 13.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 13.9 shows the timing of clearing the counter by an external reset input. External reset input pin Clear signal TCNT N-1 N H'00 Figure 13.9 Timing of Counter Clear by External Reset Input Rev. 1.00 Apr. 28, 2008 Page 378 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure 13.10 shows the timing of OVF flag setting. TCNT H'FF H'00 Overflow signal OVF Figure 13.10 Timing of OVF Flag Setting Rev. 1.00 Apr. 28, 2008 Page 379 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 13.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs. The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit comparematch occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear by the TMI0 pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently. * Pin output Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare-match conditions. Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare-match conditions. 13.6.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each or TMR_0 and TMR_1. Rev. 1.00 Apr. 28, 2008 Page 380 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 13.7.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X occupying the lower 8 bits. * Setting of compare-match flags The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs. The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs. * Counter clear specification If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at comparematch, only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y are also cleared when counter clear by the TMRIY pin has been set. The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of TCNT_X can be cleared by the counter. * Pin output Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance with the upper 8-bit compare-match conditions. Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance with the lower 8-bit compare-match conditions. 13.7.2 Compare-Match Count Mode When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1, TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the settings for each channel. Rev. 1.00 Apr. 28, 2008 Page 381 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. (1) Input Capture Signal Input Timing Figure 13.11 shows the timing of the input capture operation. TMRIX Input capture signal TCNT_X TICRR TICRF M m n n n+1 n m N N N+1 Figure 13.11 Timing of Input Capture Operation If the input capture signal is input while TICRR and TICRF are being read, the input capture signal is delayed by one system clock () cycle. Figure 13.12 shows the timing of this operation. TICRR, TICRF read cycle T1 T2 TMRIX Input capture signal Figure 13.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) Rev. 1.00 Apr. 28, 2008 Page 382 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) (2) Selection of Input Capture Signal Input TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 13.5. Table 13.5 Input Capture Signal Selection TCONRI Bit 4 ICST 0 1 Description Input capture function not used TMIX pin input selection Rev. 1.00 Apr. 28, 2008 Page 383 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 13.6 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 13.6 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X Channel TMR_0 Name CMIA0 CMIB0 OVI0 TMR_1 CMIA1 CMIB1 OVI1 TMR_Y CMIAY CMIBY OVIY TMR_X ICIX CMIAX CMIBX OVIX Interrupt Source TCORA_0 compare-match TCORB_0 compare-match TCNT_0 overflow TCORA_1 compare-match TCORB_1 compare-match TCNT_1 overflow TCORA_Y compare-match TCORB_Y compare-match TCNT_Y overflow Input capture TCORA_X compare-match TCORB_X compare-match TCNT_X overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF CMFA CMFB OVF ICF CMFA CMFB OVF Low Interrupt Priority High Rev. 1.00 Apr. 28, 2008 Page 384 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.9 13.9.1 Usage Notes Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 13.13, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU T1 T2 Address Internal write signal Counter clear signal TCNT N H'00 TCNT address Figure 13.13 Conflict between TCNT Write and Clear 13.9.2 Conflict between TCNT Write and Count-Up If a count-up occurs during the T2 state of a TCNT write cycle as shown in figure 13.14, the counter write takes priority and the counter is not incremented. TCNT write cycle by CPU T2 T1 Address Internal write signal TCNT input clock TCNT N Counter write data M TCNT address Figure 13.14 Conflict between TCNT Write and Count-Up Rev. 1.00 Apr. 28, 2008 Page 385 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled. TCOR write cycle by CPU T1 T2 Address Internal write signal TCNT TCOR N N TCOR write data Compare-match signal Disabled N+1 M TCOR address Figure 13.15 Conflict between TCOR Write and Compare-Match 13.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the operation follows the output status that is defined for compare-match A or B, according to the priority of the timer output shown in table 13.7. Table 13.7 Timer Output Priorities Output Setting Toggle output 1 output 0 output No change Low Priority High Rev. 1.00 Apr. 28, 2008 Page 386 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.9.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.8 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 13.8, a TCNT clock pulse is generated on the assumption that the switchover is a falling edge, and TCNT is incremented. Erroneous incrementation can also happen when switching between internal and external clocks. Table 13.8 Switching of Internal Clocks and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from low to low level*1 No. 1 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N CKS bit rewrite N+1 2 Clock switching from low to high level*2 Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Rev. 1.00 Apr. 28, 2008 Page 387 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to low level*3 TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock *4 TCNT N N+1 CKS bit rewrite N+2 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented. Rev. 1.00 Apr. 28, 2008 Page 388 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) 13.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. 13.9.7 Module Stop Mode Setting TMR operation can be enabled or disabled using the module stop control register. The initial setting is for TMR operation to be halted. Register access is enabled by canceling the module stop mode. For details, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 389 of 994 REJ09B0452-0100 Section 13 8-Bit Timer (TMR) Rev. 1.00 Apr. 28, 2008 Page 390 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. A block diagram of the WDT_0 and WDT_1 are shown in figure 14.1. 14.1 Features * Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks. * Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode: * If the counter overflows, whether an internal reset or an internal NMI interrupt is generated can be selected. Interval Timer Mode: * If the counter overflows, an interval timer interrupt (WOVI) is generated. Rev. 1.00 Apr. 28, 2008 Page 391 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) WOVI0 (Interrupt request signal) Internal NMI (Interrupt request signal*2) Interrupt control Reset control Overflow Clock Clock selection Internal reset signal*1 /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock TCNT_0 TCSR_0 Module bus WDT_0 Bus interface WOVI1 (Interrupt request signal) Internal NMI (Interrupt request signal*2) Interrupt control Reset control Overflow Clock Clock selection Internal reset signal*1 /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 TCNT_1 TCSR_1 Module bus WDT_1 [Legend] TCSR_0: TCNT_0: TCSR_1: TCNT_1: Timer control/status register_0 Timer counter_0 Timer control/status register_1 Timer counter_1 Bus interface Notes: 1. The internal reset signal first resets the WDT in which the overflow has occurred first. 2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1. The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from that from WDT_1. Figure 14.1 Block Diagram of WDT Rev. 1.00 Apr. 28, 2008 Page 392 of 994 REJ09B0452-0100 Internal bus Internal bus Section 14 Watchdog Timer (WDT) 14.2 Input/Output Pins The WDT has the pins listed in table 14.1. Table 14.1 Pin Configuration Name External sub-clock input pin Pin Name EXCL I/O Input Function Inputs the clock pulses to the WDT_1 prescaler counter 14.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 14.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). Table 14.2 Register Configuration Channel Channel 0 Register Name Timer counter_0 Abbreviation TCNT_0 R/W R/W Initial Value H'00 Address H'FFA8 H'FFA9* Timer control/status TCSR_0 register_0 Channel 1 Timer counter_1 TCNT_1 R/W H'00 H'FFA8 H'FFA8* R/W H'00 H'FFEA H'FFEB* Timer control/status TCSR_1 register_1 Note: * Address in the upper cell: when writing. Address in the lower cell: when reading R/W H'00 H'FFEA H'FFEA* Data Bus Width 16 8 16 8 16 8 16 8 Rev. 1.00 Apr. 28, 2008 Page 393 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. * TCSR_0 Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] * * When TCSR is read when OVF = 1, then 0 is written to OVF When 0 is written to TME 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H00. 4 0 R/(W) Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 394 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) Bit 3 Bit Name RST/NMI Initial Value 0 R/W R/W Description Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s) Note: * Only 0 can be written, to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 395 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) * TCSR_1 Bit 7 Bit Name OVF Initial Value 0 R/W 1 Description R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing conditions] When TCSR is read when OVF = 1* , then 0 is written to OVF When 0 is written to TME 2 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of -based prescaler (PSM) 1: Counts the divided cycle of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed. 0: An NMI interrupt is requested 1: An internal reset is requested Rev. 1.00 Apr. 28, 2008 Page 396 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle for = 20 MHz and SUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: /2 (frequency: 25.6 s) 001: /64 (frequency: 819.2 s) 010: /128 (frequency: 1.6 ms) 011: /512 (frequency: 6.6 ms) 100: /2048 (frequency: 26.2 ms) 101: /8192 (frequency: 104.9 ms) 110: /32768 (frequency: 419.4 ms) 111: /131072 (frequency: 1.68 s) When PSS = 1: 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s) Notes: 1. Only 0 can be written, to clear the flag. 2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at least twice. Rev. 1.00 Apr. 28, 2008 Page 397 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) 14.4 14.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this LSI is issued for 518 system clocks as shown in figure 14.2. If the RST/NMI bit is cleared to 0, when the TCNT overflows, an NMI interrupt request is generated. An internal reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Internal reset signal 518 System clocks [Legned] WT/IT: Timer mode select bit TME: Timer enable bit Overflow flag OVF: Note * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Write H'00 to TCNT OVF = 1* Time WT/IT = 1 Write H'00 to TME = 1 TCNT Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation Rev. 1.00 Apr. 28, 2008 Page 398 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 14.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF flag of TCSR is set to 1. The timing is shown figure 14.4. TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Time WOVI: Interval timer interrupt request occurrence Figure 14.3 Interval Timer Mode Operation TCNT Overflow signal (internal signal) H'FF H'00 OVF Figure 14.4 OVF Flag Set Timing Rev. 1.00 Apr. 28, 2008 Page 399 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) 14.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 14.3 WDT Interrupt Source Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF 14.6 14.6.1 Usage Notes Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. (1) Writing to TCNT and TCSR (Example of WDT_0) These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 14.5 to write to TCNT or TCSR. To write to TCNT, the higher bytes must contain the value H'5A and the lower bytes must contain the write data before the transfer instruction execution. To write to TCSR, the higher bytes must contain the value H'A5 and the lower bytes must contain the write data. Rev. 1.00 Apr. 28, 2008 Page 400 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) Figure 14.5 Writing to TCNT and TCSR (WDT_0) (2) Reading from TCNT and TCSR (Example of WDT_0) These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT. 14.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.6 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.6 Conflict between TCNT Write and Increment Rev. 1.00 Apr. 28, 2008 Page 401 of 994 REJ09B0452-0100 Section 14 Watchdog Timer (WDT) 14.6.3 Changing Values of CKS2 to CKS0 Bits If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the values of CKS2 to CKS0 bits. 14.6.4 Changing Value of PSS Bit If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of PSS bit. 14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 1.00 Apr. 28, 2008 Page 402 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous communication function. 15.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The External clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. Asynchronous Mode: Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Multiprocessor communication capability * * * * * Rev. 1.00 Apr. 28, 2008 Page 403 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception. * Data can be automatically re-transmitted on detection of an error signal during transmission. * Both direct convention and inverse convention are supported. Figure 15.1 shows a block diagram of SCI. Module data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 Clock External clock TEI TXI RXI ERI RxD1 RSR TSR SMR Transmission/ reception control TxD1 Parity check SCK1 Parity generation [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register Figure 15.1 Block Diagram of SCI Rev. 1.00 Apr. 28, 2008 Page 404 of 994 REJ09B0452-0100 Internal data bus Bus interface Section 15 Serial Communication Interface (SCI) 15.2 Input/Output Pins Table 15.1 shows the input/output pins for each SCI channel. Table 15.1 Pin Configuration Channel 1 Pin Name* SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 Note: * Input/Output Input/Output Input Output Input/Output Input Output Function Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev. 1.00 Apr. 28, 2008 Page 405 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes normal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. Table 15.2 Register Configuration Channel Register Name Channel 0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 Channel 1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 Abbreviation R/W SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Data Bus Address Width H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 406 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 15.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00. 15.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. 15.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 1.00 Apr. 28, 2008 Page 407 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. The CPU can always read SMR. The CPU can write to SMR only at the initial settings; do not have the CPU write to SMR in transmission, reception, and simultaneous data transmission and reception. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. Rev. 1.00 Apr. 28, 2008 Page 408 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). * Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu* from the start and the clock output control function is appended. For details, see section 15.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 15.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 5 PE 0 R/W Rev. 1.00 Apr. 28, 2008 Page 409 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Bit 4 Bit Name O/E Initial Value 0 R/W R/W Description Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 15.7.2, Data Format (Except in Block Transfer Mode). 3 2 BCP1 BCP0 0 0 R/W R/W Basic Clock Pulse 1 and 0 These bits select the number of basic clock cycles in a 1-bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 15.3.9, Bit Rate Register (BRR). 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 15.3.9, Bit Rate Register (BRR)). Note: * etu: Element Time Unit (time taken to transfer one bit) Rev. 1.00 Apr. 28, 2008 Page 410 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 15.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. The CPU can always read SCR. The CPU can write to SCR only at the initial settings; do not have the CPU write to SCR in transmission, reception, and simultaneous data transmission and reception. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 15.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. Rev. 1.00 Apr. 28, 2008 Page 411 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 These bits select the clock source and SCK pin function. * Asynchronous mode 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1x: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) * Clocked synchronous mode 0x: Internal clock (SCK pin functions as clock output.) 1x External clock (SCK pin functions as clock input.) [Legend] x: Don't care Rev. 1.00 Apr. 28, 2008 Page 412 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) * Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Clock Enable 1 and 0 Controls the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 15.7.8, Clock Output Control. * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1x: Reserved * When GM in SMR = 1 00: Output fixed to low 01: Clock output 10: Output fixed to high 11: Clock output [Legend] x: Don't care Rev. 1.00 Apr. 28, 2008 Page 413 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and TDR is ready for data write [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition] When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 Rev. 1.00 Apr. 28, 2008 Page 414 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial Value 0 R/W Description R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit frame. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 415 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) * Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit 7 Bit Name TDRE Initial Value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR, and TDR can be written to. [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that receive data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition] When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)*1 Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 ERS 0 R/(W)*1 Error Signal Status [Setting condition] When a low error signal is sampled [Clearing condition] When 0 is written to ERS after reading ERS = 1 1 Rev. 1.00 Apr. 28, 2008 Page 416 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W 1 Description R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both TE and EPS in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after the start of 1-byte data transfer. The set timing depends on the register setting as follows. 2 When GM = 0 and BLK = 0, 2.5 etu* after transmission start * * * * When GM = 0 and BLK = 1, 1.5 etu*2 after transmission start When GM = 1 and BLK = 0, 1.0 etu*2 after transmission start 2 When GM = 1 and BLK = 1, 1.0 etu* after transmission start [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 0 MPB MPBT 0 0 R R/W Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Notes: 1. Only 0 can be written to clear the flag. 2. etu: Element Time Unit (time taken to transfer one bit) Rev. 1.00 Apr. 28, 2008 Page 417 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit 7 to 4 Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR. The SDIR bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. When the parity bit is inverted, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 1 R Reserved This bit is always read as 1 and cannot be modified. 0 SMIF 0 R/W Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode Rev. 1.00 Apr. 28, 2008 Page 418 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.3 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF. The CPU can always read BRR. The CPU can write to BRR only at the initial settings; do not have the CPU write to BRR in transmission, reception, and simultaneous data transmission and reception. Table 15.3 Relationships between N Setting in BRR and Bit Rate B Mode Asynchronous mode B= 64 x 2 Bit Rate x 106 2n - 1 Error Error (%) = { x 106 B x 64 x 2 2n - 1 - 1 } x 100 x (N + 1) x (N + 1) Clocked synchronous mode B= x 106 8x2 2n - 1 x (N + 1) x 106 BxSx2 2n + 1 Smart card interface mode B= Sx2 x 106 2n + 1 Error (%) = { -1 } x 100 x (N + 1) x (N + 1) [Legend] B: N: : n and S: SMR Setting CKS1 0 0 1 1 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following table SMR Setting CKS0 0 1 0 1 n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256 Table 15.4 shows sample N settings in BRR in normal asynchronous mode. Table 15.5 shows the maximum bit rate settable for each frequency. Table 15.7 and 15.9 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.6 and 15.8 show the maximum bit rates with external clock input. Rev. 1.00 Apr. 28, 2008 Page 419 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) 8 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 Operating Frequency (MHz) 12.288 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 [Legend] : Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Rev. 1.00 Apr. 28, 2008 Page 420 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 17.2032 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 16 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 [Legend] : Can be set, but there will be a degree of error. Note: * Make the settings so that the error does not exceed 1%. Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 Maximum Bit Rate (bit/s) 460800 500000 537600 562500 614400 625000 (MHz) 8 9.8304 10 12 12.288 14 n 0 0 0 0 0 0 N 0 0 0 0 0 0 (MHz) 14.7456 16 17.2032 18 19.6608 20 n 0 0 0 0 0 0 N 0 0 0 0 0 0 Rev. 1.00 Apr. 28, 2008 Page 421 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 8 9.8304 10 12 12.288 14 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 (MHz) 14.7456 16 17.2032 18 19.6608 20 External Input Maximum Bit Clock (MHz) Rate (bit/s) 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 230400 250000 268800 281250 307200 312500 Table 15.7 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) 8 Bit Rate (bit/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M [Legend] Blank: Setting prohibited. : Can be set, but there will be a degree of error. *: Continuous transfer or reception is not possible. 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* N n 10 N n 16 N n 20 N Rev. 1.00 Apr. 28, 2008 Page 422 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Table 15.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 8 10 12 14 External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 (MHz) 16 18 20 External Input Clock (MHz) 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2666666.7 3000000.0 3333333.3 Table 15.9 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) Operating Frequency (MHz) 10.00 Bit Rate (bit/s) 9600 0 1 n N Error (%) 30 n 0 13.00 N 1 Error (%) -8.99 n 0 14.2848 N 1 Error (%) n 0.00 0 N 1 16.00 Error (%) 12.01 Operating Frequency (MHz) 18.00 Bit Rate (bit/s) 9600 0 2 n N Error (%) -15.99 n 0 N 2 20.00 Error (%) -6.65 Table 15.10 Maximum Bit Rate for Each Frequency (Smart Card Interface Mode, S = 372) Maximum Bit Rate (bit/s) 13441 17473 19200 Maximum Bit Rate (bit/s) n 21505 24194 26882 0 0 0 (MHz) 10.00 13.00 14.2848 n 0 0 0 N 0 0 0 (MHz) 16.00 18.00 20.00 N 0 0 0 Rev. 1.00 Apr. 28, 2008 Page 423 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) 1 or 2 bits Figure 15.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00 Apr. 28, 2008 Page 424 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.1 Data Transfer Format Table 15.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 15.5, Multiprocessor Communication Function. Table 15.11 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR PE MP STOP 1 S 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 0 0 0 0 8-bit data 0 0 0 1 S 8-bit data STOPSTOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOPSTOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOPSTOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOPSTOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 1.00 Apr. 28, 2008 Page 425 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 - M: N: D: L: F: 1 D - 0.5 )- (1 + F) - (L - 0.5) F } x 100 2N N [%] ... Formula (1) Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Apr. 28, 2008 Page 426 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 1.00 Apr. 28, 2008 Page 427 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set data transfer format in SMR and SCMR Set value in BRR Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [2] Set the data transfer format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] [3] [3] [4] [4] Figure 15.5 Sample SCI Initialization Flowchart Rev. 1.00 Apr. 28, 2008 Page 428 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.5 Serial Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 15.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine 1 frame TEI interrupt request generated Figure 15.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Apr. 28, 2008 Page 429 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission Read TDRE flag in SSR No [1] [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1 No [4] Note: Do not write to SMR, SCR, BRR, and SDCR from the start to the end of transmission except the process of [5]. Clear TE bit in SCR to 0 End transmission [5] Figure 15.7 Sample Serial Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 430 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated 1 frame RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error Figure 15.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Apr. 28, 2008 Page 431 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Table 15.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.12 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev. 1.00 Apr. 28, 2008 Page 432 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Initialization Start reception Read ORER, PER, and FER flags in SSR [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags [3] are all cleared to 0. Reception cannot No Error processing be resumed if any of these flags are (Continued on next page) set to 1. In the case of a framing error, a break can be detected by reading the value of the input port [4] Read RDRF flag in SSR corresponding to the RxD pin. No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. Note: End reception [6] Do not write to SMR, SCR, BRR, and SDCR from the start to the end of transmission except the process of [6]. All data received? Yes Clear RE bit in SCR to 0 [5] [Legend] : Logical add (OR) Figure 15.9 Sample Serial Reception Flowchart (1) Rev. 1.00 Apr. 28, 2008 Page 433 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 [6] Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Flowchart (2) Rev. 1.00 Apr. 28, 2008 Page 434 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the RDRF, FER, and ORER status flags in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 1.00 Apr. 28, 2008 Page 435 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Transmitting station Serial communication line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 15.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 1.00 Apr. 28, 2008 Page 436 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set port DDR to 1, clear DR to 0, and then clear the TE bit in SCR to 0. [4] Note: Do not write to SMR, SCR, BRR, and SDCR from the start to the end of transmission except the process of [5]. Initialization Start transmission Read TDRE flag in SSR No [1] [2] TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1 No No Clear TE bit in SCR to 0 End transmission [5] Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 437 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 Data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Data (Data 2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data 2 MPIE bit set to 1 again (b) Data matches station's ID Figure 15.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00 Apr. 28, 2008 Page 438 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. [4] In the case of a framing error, a break can be detected by reading the RxD pin value. Note: Do not write to SMR, SCR, BRR, and SDCR from the start to the end of reception except the process of [6]. [2] FER ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes [3] FER ORER = 1 No Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 End reception Yes No [5] Error processing (Continued on next page) [6] [Legend] : Logical add (OR) Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 1.00 Apr. 28, 2008 Page 439 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 [6] Yes Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00 Apr. 28, 2008 Page 440 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling fullduplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 15.14 Data Format in Synchronous Communication (LSB-First) 15.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 1.00 Apr. 28, 2008 Page 441 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags in SSR, or RDR. [1] Set the data transfer format in SMR and SCMR. [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, MPIE, TE, and RE to 0. [1] [3] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Start initialization Clear TE and RE bits in SCR to 0 Set data transfer format in SMR and SCMR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set value in BRR Wait [3] 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, andset RIE, TIE, TEIE, and MPIE bits No [4] Figure 15.15 Sample SCI Initialization Flowchart Rev. 1.00 Apr. 28, 2008 Page 442 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 1.00 Apr. 28, 2008 Page 443 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Initialization Start transmission Read TDRE flag in SSR No [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Note: Do not write to SMR, SCR, BRR, and SDCR from the start to the end of transmission except the process of [4]. [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 End transmission No [4] Figure 15.17 Sample Serial Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 444 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart for serial data reception. Rev. 1.00 Apr. 28, 2008 Page 445 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. Note: Do not write to SMR, SCR, BRR, and SDCR from the start to the end of reception except the process of [6]. Read ORER flag in SSR Yes [2] ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR No [4] RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 End reception [5] [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 15.19 Sample Serial Reception Flowchart Rev. 1.00 Apr. 28, 2008 Page 446 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1, clear the TE bit in SCR to 0. Then simultaneously set the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set the TE and RE bits to 1 with a single instruction. Rev. 1.00 Apr. 28, 2008 Page 447 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear TE and RE bits in SCR to 0 [5] End transmission/reception [6] Notes: 1. When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. 2. Do not write to SMR, SCR, BRR, and SDCR from the start to the end of transmission/reception except the process of [6]. Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 1.00 Apr. 28, 2008 Page 448 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 15.7.1 Sample Connection Figure 15.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits in SCR to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card Figure 15.21 Pin Connection for Smart Card Interface Rev. 1.00 Apr. 28, 2008 Page 449 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7.2 Data Format (Except in Block Transfer Mode) Figure 15.22 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after two or more etu. In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Output from the transmitting station Output from the receiving station Start bit Data bits Parity bit Error signal [Legend] Ds: D0 to D7 : Dp: DE: Figure 15.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) Rev. 1.00 Apr. 28, 2008 Page 450 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 15.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 15.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 15.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. * If a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. Rev. 1.00 Apr. 28, 2008 Page 451 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the internal baud rate generator can be used as a communication clock in smart card interface mode. In this mode, the SCI can operate using a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the internal basic clock in order to perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in figure 15.25. The reception margin here is determined by the following formula. M = (0.5 - 1 ) - (L - 0.5) F - D - 0.5 (1 + F) x 100 [%] 2N N ... Formula (1) M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock rate deviation Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is determined by the formula below. M = (0.5 - 1 / 2 x 372) x 100 [%] = 49.866% 372 clock cycles 186 clock cycles 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 185 371 0 185 371 0 Start bit D0 D1 Figure 15.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) Rev. 1.00 Apr. 28, 2008 Page 452 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ORER, ERS, and PER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the SMIF bit is set to 1, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. 7. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least 1 bit interval. Setting prohibited the TE and RE bits to 1 simultaneously except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, and initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF flag or PER and ORER flags. To switch from transmission to reception, first verify that transmission has completed, and initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. 15.7.6 Serial Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted. Figure 15.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. Rev. 1.00 Apr. 28, 2008 Page 453 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 15.28 shows a sample flowchart for transmission. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR is set. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, TEND remains 0. Therefore, the SCI automatically transmit the specified number of bytes, including re-transmission in the case of error. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. (n + 1) th transfer frame Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer from TDR to TSR Retransfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer from TDR to TSR Transfer from TDR to TSR TEND [2] FER/ERS [1] [3] [3] Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 15.27. I/O data TXI (TEND interrupt) GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu 11.0 etu GM = 1 [Legend] Ds: Start bit D0 to D7: Data bits Dp: Parity bit DE: etu: Error signal Element Time Unit (time taken to transfer one bit) Figure 15.27 TEND Flag Set Timings during Transmission Rev. 1.00 Apr. 28, 2008 Page 454 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 15.28 Sample Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 455 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 15.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set. Figure 15.30 shows a sample flowchart for reception. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. Even if a parity error occurs and PER is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 15.4, Operation in Asynchronous Mode. (n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 n th transfer frame Retransfer frame RDRF [2] PER [3] [1] [3] Figure 15.29 Data Re-transfer Operation in SCI Reception Mode Rev. 1.00 Apr. 28, 2008 Page 456 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? No Yes Error processing No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 15.30 Sample Reception Flowchart Rev. 1.00 Apr. 28, 2008 Page 457 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 15.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Specified pulse width Specified pulse width Figure 15.31 Clock Output Fixing Timing At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. (1) At Power-On To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. 4. Set the CKE0 bit in SCR to 1 to start clock output. Rev. 1.00 Apr. 28, 2008 Page 458 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) (2) At Transition from Smart Card Interface Mode to Software Standby Mode 1. Set the port data register (DR) and data direction register (DDR) corresponding to the SCK pins to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty ratio retained. 5. Make the transition to software standby mode. (3) At Transition from Software Standby Mode to Smart Card Interface Mode 1. Cancel software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty ratio is then generated. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [1] [2] Figure 15.32 Clock Stop and Restart Procedure Rev. 1.00 Apr. 28, 2008 Page 459 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.8 15.8.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 15.13 SCI Interrupt Sources Channel 1 Name ERI1 RXI1 TXI1 TEI1 2 ERI2 RXI2 TXI2 TEI2 Interrupt Source Receive error Receive data full Transmit data empty Transmit end Receive error Receive data full Transmit data empty Transmit end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND Low Priority High Rev. 1.00 Apr. 28, 2008 Page 460 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.8.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 15.14 SCI Interrupt Sources Channel 1 Name ERI1 RXI1 TXI1 2 ERI2 RXI2 TXI2 Interrupt Source Receive error, error signal detection Receive data full Transmit data empty Receive error, error signal detection Receive data full Transmit data empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND Low Priority High In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, the TEND flag remains 0. Therefore, the SCI automatically transmits the specified number of bytes, including re-transmission in the case of error. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. Rev. 1.00 Apr. 28, 2008 Page 461 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.9 15.9.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 26, Power-Down Modes. 15.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 15.9.3 Mark State and Break Sending When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR of the port. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 15.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1, even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit in SCR is cleared to 0. 15.9.5 Relation between Writing to TDR and TDRE Flag Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. Rev. 1.00 Apr. 28, 2008 Page 462 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.9.6 (1) SCI Operations during Mode Transitions Transmission Before making the transition to module stop or software standby, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 15.33 shows a sample flowchart for mode transition during transmission. Figures 15.34 and 15.35 show the pin states during transmission. Transmission No [1] All data transmitted? Yes Read TEND flag in SSR [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation. [2] Also clear TIE and TEIE to 0 when they are 1. [3] Module stop mode and watch mode are included. TEND = 1 Yes TE = 0 [2] No Make transition to software standby mode etc. Cancel software standby mode etc. [3] Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 15.33 Sample Flowchart for Mode Transition during Transmission Rev. 1.00 Apr. 28, 2008 Page 463 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Transmission start Transmission end Transition to software standby mode Software standby mode cancelled TE bit SCK output pin TxD Port output pin input/output Port High output Start SCI TxD output Stop Port input/output Port input/output Port High output SCI TxD output Figure 15.34 Pin States during Transmission in Asynchronous Mode (Internal Clock) Transition to software standby mode Transmission start Transmission end Software standby mode cancelled TE bit SCK output pin TxD Port output pin input/output Port Note: Initialized in software standby mode Marking output SCI TxD output Port input/output Last TxD bit retained Port input/output Port High output* SCI TxD output Figure 15.35 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Rev. 1.00 Apr. 28, 2008 Page 464 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) (2) Reception Before making the transition to module stop, software standby or watch mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 15.36 shows a sample flowchart for mode transition during reception. Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop mode and watch mode are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 15.36 Sample Flowchart for Mode Transition during Reception Rev. 1.00 Apr. 28, 2008 Page 465 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.9.7 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 15.40. Low pulse of half a cycle SCK/Port 1. Transmission end Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 3. C/A = 0 4. Low pulse output Figure 15.37 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins, specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1. 1. 2. 3. 4. 5. End serial data transmission TE bit = 0 CKE1 bit = 1 C/A bit = 0 (switch to port output) CKE1 bit = 0 High output SCK/Port Data TE C/A 3. CKE1 = 1 CKE1 CKE0 Bit 6 1. Transmission end Bit 7 2. TE = 0 4. C/A = 0 5. CKE1 = 0 Figure 15.38 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins Rev. 1.00 Apr. 28, 2008 Page 466 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) 15.9.8 Note on Writing to Registers in Transmission, Reception, and Simultaneous Transmission and Reception After 1 is set to the TE and RE bits in SCR to start transmission, reception, and simultaneous transmission and reception, do not write to SMR, SCR, BRR, and SDCR. Also, do not overwrite the same value as the register value. However, this does not apply when a register is written to clear the TE and RE bits in SCR to 0 after transmission, reception, or simultaneous transmission and reception is completed. Reading is always allowed. Rev. 1.00 Apr. 28, 2008 Page 467 of 994 REJ09B0452-0100 Section 15 Serial Communication Interface (SCI) Rev. 1.00 Apr. 28, 2008 Page 468 of 994 REJ09B0452-0100 Section 16 CIR Interface Section 16 CIR Interface This LSI incorporates a custom infra-red interface (CIR). The CIR has various functions for receiving the IR signal in NEC format. 16.1 Features * Supports reception of the IR signal in NEC format * Sampling clock selectable Selectable from internal clocks , /2, and /4, and subclock (SUB) * Noise canceling function Input noise can be filtered out by using a maximum of four stages of filters. * Polarity inversion of the input signal supported * 18-byte FIFO incorporated * Six interrupt sources: receive end, framing error, overrun error, repeat detection, abort generation, and header detection Interrupt sources can be specified by checking each flag. Figure 16.1 is a block diagram of the CIR. Rev. 1.00 Apr. 28, 2008 Page 469 of 994 REJ09B0452-0100 Section 16 CIR Interface Module data bus HHMAX HHMIN CIRRDR 0 to 17 (18-byte FIFO) HLMAX HLMIN DT0MAX DT0MIN DT1MAX DT1MIN CIRI RMAX RMIN CCR1 CCR2 CSTR BRR /2 Baud rate generator CEIR /4 SUB 4-stage filter SFR Reception control Sampling clock RENDI OVEI REPI FREI ABI HEADFI [Legend] SFR: Receive shift register CCR1: Receive control register 1 CCR2: Receive control register 2 CSTR: Receive status register CEIR: Interrupt enable register BRR: Bit rate register CIRRDR0 to 17: Receive data register 0 to 17 HHMIN: Header minimum high-level period register HHMAX: Header maximum high-level period register HLMIN: Header minimum low-level period register HLMAX: Header maximum low-level period register DT1MIN: Data level 1 minimum period register DT1MAX: Data level 1 maximum period register DT0MIN: Data level 0 minimum period register DT0MAX: Data level 0 maximum period register RMIN: Repeat header minimum low-level period register RMAX: Repeat header maximum low-level period register Figure 16.1 CIR Block Diagram Rev. 1.00 Apr. 28, 2008 Page 470 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.2 Input Pins Table 16.1 shows the input pin of the CIR. Table 16.1 Pin Configuration Pin Name CIR input pin Symbol CIRI I/O Input Function CIR receive data input pin 16.3 Register Description Table 16.2 shows the CIR register configuration. Table 16.2 List of Register Addresses Register Name Receive control register 1 Receive control register 2 Receive status register Interrupt enable register Bit rate register Receive data register 0 to 17 Header minimum high-level period register Abbreviation CCR1 CCR2 CSTR CEIR BRR CIRRDR0 to CIRRDR17 HHMIN R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'00 H'0000 H'0000 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA48 H'FA4A H'FA4B H'FA4C H'FA4D H'FA4E H'FA4F Header maximum high-level period register HHMAX Header minimum low-level period register Header maximum low-level period register Data level 0 minimum period register Data level 0 maximum period register Data level 1 minimum period register Data level 1 maximum period register HLMIN HLMAX DT0MIN DT0MAX DT1MIN DT1MAX Rev. 1.00 Apr. 28, 2008 Page 471 of 994 REJ09B0452-0100 Section 16 CIR Interface Register Name Repeat header minimum low-level period register Repeat header maximum low-level period register Abbreviation RMIN RMAX R/W R/W R/W Initial Value H'00 H'00 Address H'FA50 H'FA51 Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0. 2. See the description of each register for details on R/W. 16.3.1 Receive Control Register 1 (CCR1) CCR1 enable/disable the CIR reception, controls a software reset of the CIR, select the polarity of the CIR input signals, and select the reference clock for CIR reception. Bit 7 Bit Name CIRE Initial Value 0 R/W R/W Description CIR Receive Enable 0: The CIR reception is disabled. 1: The CIR reception is enabled (Port is CIRI input pin). 6 SRES 0 R/W CIR Software Reset Controls initialization of the internal sequencer of the CIR. 0: Normal operation 1: The internal sequencer is cleared. Writing 1 to this bit generates a clear signal for the internal sequencer in the corresponding module, resulting in the initialization of the CIR's internal state. 5 CPHS 0 R/W Input Signal Polarity Select 0: CIR input signal is used as is. 1: CIR input signal is inverted before use. 4 MLS 0 R/W Receive Data Format Select 0: LSB-first data is received. 1: MSB-first data is received. Rev. 1.00 Apr. 28, 2008 Page 472 of 994 REJ09B0452-0100 Section 16 CIR Interface Bit 3 Bit Name REPRCVE Initial Value 0 R/W R/W Description Receive Enable after Repeat Detection Enables/disables the CIR reception after a repeat detection. 0: The CIR reception is disabled by a repeat detection. 1: The CIR reception is enabled by a repeat detection 2 1 0 CLK1 CLK0 0 0 0 R/W R/W R/W Reserved The initial value should not be changed. Reference Clock 00: Internal clock 01: Internal clock /2 10: Internal clock /4 11: subclock sub 16.3.2 Receive Control Register 2 (CCR2) CCR2 consists of the bits that select the CIR communication format. Bit 7 6 Bit Name TFM1 TFM0 Initial Value 0 0 R/W R/W R/W Description Reception Signal Format Select 00: NEC format (4 bytes are used) (Address, address, command, and command are stored in CIRRDR.) 01: NEC format (2 bytes are used) (Address and command are stored in CIRRDR.) 10: Setting prohibited 11: Setting prohibited 5 to 0 All 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 473 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.3 Receive Status Register (CSTR) CSTR indicates the data reception state of the CIR. Bit 7 Bit Name CIRBUSY Initial Value 0 R/W R Description CIR Busy Flag Indicates the data receive state of the CIR. [Setting condition] When the CIR starts data reception. [Clearing condition] When the CIR has finished data reception. 6 CIRRDRF 0 R Receive Data Register Full Indicates whether CIRRDR contains a receive data or not. This bit cannot be modified. [Setting condition] When a receive data is stored into CIRRDR. [Clearing condition] When a receive data has been read from CIRRDR. 5 REPF 0 R/W* Repeat Detection Flag Indicates a repeat is generated. [Setting condition] When a repeat is detected. [Clearing condition] When writing 0 after reading REPF = 1. 4 OVRF 0 R/W* Overrun Error Flag Indicates CIRRDR overflows. [Setting condition] When the next data is stored in CIRRDR while CIRRDR is full. [Clearing condition] When writing 0 after reading OVRF = 1. Rev. 1.00 Apr. 28, 2008 Page 474 of 994 REJ09B0452-0100 Section 16 CIR Interface Bit 3 Bit Name REND Initial Value 0 R/W R/W* Description Reception End Flag [Setting condition] When the CIR has finished data reception. (When a stop is detected.) [Clearing condition] When writing 0 after reading REND = 1. 2 ABF 0 R/W* Abort Flag An internal reset is generated when an abort (transfer format) is detected. [Setting condition] When data other than logic 0 or 1 is detected. [Clearing condition] When writing 0 after reading ABF = 1. 1 FRF 0 R/W* Framing Error Flag [Setting condition] * * When a stop is detected during data reception. When the time period of a stop is too short. [Clearing condition] When writing 0 after reading FRF = 1. 0 HEADF 0 R/W* Header Detection Flag [Setting condition] When a header is detected. [Clearing condition] When writing 0 after reading HEADF = 1. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 475 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.4 Interrupt Enable Register (CEIR) CEIR consists of the bits that enable/disable various interrupts. Bit 7, 6 5 Bit Name REPIE Initial Value All 0 0 R/W R/W R/W Description Reserved The initial value should not be changed. Repeat Detection Interrupt Enable 0: REPI interrupt request is disabled. 1: REPI interrupt request is enabled. 4 OVEIE 0 R/W Overrun Error Interrupt Enable 0: OVEI interrupt request is disabled. 1: OVEI interrupt request is enabled. 3 RENDIE 0 R/W Receive End Interrupt Enable 0: RENDI interrupt request is disabled. 1: RENDI interrupt request is enabled. 2 ABIE 0 R/W Abort Interrupt Enable 0: ABI interrupt request is disabled. 1: ABI interrupt request is enabled. 1 FREIE 0 R/W Framing Error Interrupt Enable 0: FREI interrupt request is disabled. 1: FREI interrupt request is enabled. 0 HEADFIE 0 R/W Header Detection Interrupt Enable 0: HEADFI interrupt request is disabled. 1: HEADFI interrupt request is enabled. Rev. 1.00 Apr. 28, 2008 Page 476 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.5 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate for the CIR reception is determined by a combination of the setting value in BRR and the CLK1 and CLK0 bits in CCR1. Initial Value All 1 Bit 7 to 0 Bit Name BRR7 to BRR1 R/W R/W Description Sets the value of the sampling clock. The following formula is used for calculating the bit rate, and the following table shows BRR setting examples to obtain a target bit rate. B = T / (N + 1) B: Bit rate (bits/s) T: Frequency of the reference clock (Hz) set by the CLK1 and CLK0 bits in CCR1 (, /2, /4, or sub) N: Set value in BRR (0 N 255) Table 16.3 Setting Example of BRR Carrier Frequency 38kHz CLK1 and CLK0 Setting /2 /4 10 MHz /2 /4 8 MHz /2 /4 sub BRR Setting Value H'FF H'FF H'83 H'FF H'83 H'41 H'D2 H'69 H'34 H'00 Bit Rate (Kbit/s) 78.1 39.1 37.9 39.1 37.9 37.9 37.9 37.7 37.7 32.8 Deviation from Target Carrier Frequency 51.36% 2.72% -0.32% 2.72% -0.32% -0.32% -0.23% -0.70% -0.70% 2.34% 20 MHz Rev. 1.00 Apr. 28, 2008 Page 477 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17) CIRRDR0 to CIRRDR17 are an 18-byte register that stores receive data, totaling to 18 bytes. CIRRDR0 to CIRRDR17 share one byte of the register address. A receive data in CIRRDR should be read after the CIR has finished data reception (CIRBUSY = 0). If CIRRDR is read during the CIR reception (CIRBUSY = 1), an undefined value is read. Bit 7 to 0 Bit Name CIRRDR7 to CIRRDR0 Initial Value H'00 R/W R Description Stores the CIR receive data. 16.3.7 Header Minimum/Maximum High-Level Period Register (HHMIN and HHMAX) HHMIN and HHMAX control the noise canceler circuit, and specify the minimum and maximum high-level period for a header or repeat header, and low-level period for a stop. * HHMIN Bit Bit Name Initial Value All 0 R/W R Description Receive Byte Counter The RFMBN value is incremented by 1 (+1) each time a byte is received. However, when RFMBN reaches B'10011, an overrun error occurs. At this time, a receive data is not stored in CIRRDR. When CIRRDR is read after the CIR has finished receiving (CIRBUSY = 0), RFMBN is decremented by 1 (-1). When CIRRDR is read while RFMBN = B'00000, an undefined value is read. When CIRRDR is read during the CIR reception, an undefined value is read and RFMBN is not decremented. 10 9 to 0 HHMIN9 to HHMIN0 0 All 0 R/W R/W Reserved The initial value should not be changed. Specifies the minimum high-level period for a header or repeat header and the minimum low-level period for a stop. 15 to 11 RFMBN4 to RFMBN0 Rev. 1.00 Apr. 28, 2008 Page 478 of 994 REJ09B0452-0100 Section 16 CIR Interface * HHMAX Bit 15 14 Bit Name FLT1 FLT0 Initial Value 0 0 R/W R/W R/W Description Number of Stages of Noise Canceler Circuit Select 00: The noise canceler circuit consists of one stage 01: The noise canceler circuit consists of two stages 10: The noise canceler circuit consists of three stages 11: The noise canceler circuit consists of four stages 13 FLTE 0 R/W Noise Canceler Circuit Enable 0: Disables the noise canceler circuit 1: Enables the noise canceler circuit 12 11 FLTCK1 FLTCK0 0 0 R/W R/W Division Ratio Select for Noise Canceler Circuit Clock Divides the frequency of the sampling clock for CIR reception selected by BRR. 00: Not divided 01: Divided by 2 10: Divided by 4 11: Divided by 8 10 9 to 0 HHMAX9 to HHMAX0 0 All 0 R/W R/W Reserved The initial value should not be changed. Specifies the maximum high-level period for a header or repeat header and the maximum low-level period for a stop. Rev. 1.00 Apr. 28, 2008 Page 479 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX) HLMIN and HLMAX specify the minimum and maximum low-level period for a header. * HLMIN Bit 7 to 0 Bit Name HLMIN7 to HLMIN0 Initial Value H'00 R/W R/W Description Specifies the minimum low-level period for a header. * HLMAX Bit 7 to 0 Bit Name HLMAX7 to HLMAX0 Initial Value H'00 R/W R/W Description Specifies the maximum low-level period for a header. 16.3.9 Data Level 1 Minimum/Maximum Period Register (DT1MIN/DT1MAX) DT1MIN and DT1MAX specify the minimum and maximum low-level period for logic 1. * DT1MIN Bit 7 to 0 Bit Name DT1MIN7 to DT1MIN0 Initial Value H'00 R/W R/W Description Specifies the minimum low-level period for logic 1. * DT1MAX Bit 7 to 0 Bit Name DT1MAX7 to DT1MAX0 Initial Value H'00 R/W R/W Description Specifies the maximum low-level period for logic 1. Rev. 1.00 Apr. 28, 2008 Page 480 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) DT0MIN and DT0MAX specify the minimum and maximum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. * DT0MIN Bit 7 to 0 Bit Name DT0MIN7 to DT0MIN0 Initial Value H'00 R/W R/W Description Specifies the minimum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. * DT0MAX Bit 7 to 0 Bit Name DT0MAX7 to DT0MAX0 Initial Value H'00 R/W R/W Description Specifies the maximum low/high-level period for logic 0, high-level period for logic 1, and high-level period for a stop/repeat. 16.3.11 Repeat Header Minimum/Maximum Low-Level Period Register (RMIN/RMAX) RMIN and RMAX specify the minimum and maximum low-level period for a repeat header. * RMIN Bit 7 to 0 Bit Name RMIN7 to RMIN0 Initial Value H'00 R/W R/W Description Specifies the minimum low-level period for a repeat header. * RMAX Bit 7 to 0 Bit Name RMAX7 to RMAX0 Initial Value H'00 R/W R/W Description Specifies the maximum low-level period for a repeat header. Rev. 1.00 Apr. 28, 2008 Page 481 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.4 Operation The communication protocol of the NEC format is shown in figure 16.2. In the NEC format, data consists of a header part, an address part, a command part, and a stop part. The TFM bits in CCR2 can select which data bytes to be stored in CIRRDR: four bytes of the address, address, command, and command, or two bytes of the address and command. The carrier frequency is 38kHz. CIRI Header Address Address Command Command Stop Figure 16.2 NEC Format (1) Header, Address, and Command When a 9-ms high level and the following 4.5-ms low level are detected, they are recognized as a header. For addresses and commands, when both of a high-level period and the following lowlevel period are 0.56 ms, they are recognized as logic 0. When a high-level period is 0.56 ms and the following low-level period is 1.78 ms, they are recognized as logic 1. Header Logic 1 Logic 0 CIRI A = 9.0 ms [Legend] A: High-level period for a header B: Low-level period for a header C: High-level period for logic 0/1 and low-level period for logic 0 D: Low-level period for logic 1 B = 4.5 ms D = 1.78 ms C = 0.56 ms C C Figure 16.3 Header, Address, and Command Rev. 1.00 Apr. 28, 2008 Page 482 of 994 REJ09B0452-0100 Section 16 CIR Interface (2) Stop When a low-level period of 9 ms or more is detected after the reception of a command, the CIR stops data reception. This is not defined in the NEC format. Command Stop CIRI C = 0.56 ms D = 1.78 ms C A = 9.0 ms [Legend] A: Low-level period for a stop C: High-level period for logic 0/1, low-level period for logic 0, and high-level period for a stop D: Low-level period for logic 1 Figure 16.4 Stop (3) Repeat When a key of the remote controller remains pressed, the command is sent only once, followed by a repeat signal. When a 9-ms high level and the following 2.25-ms low level are detected, they are recognized as a repeat header. Repeat Repeat - Header CIRI A = 9.0 ms E = 2.25 ms C = 0.56 ms [Legend] A: High-level period for a repeat header E: Low-level period for a repeat header C: High-level period for a repeat Figure 16.5 Repeat Rev. 1.00 Apr. 28, 2008 Page 483 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.4.1 Determination of Signal Type by Low/High-Level Period The signal type is determined by low/high-level period that is specified in the HHMIN, HHMAX, HLMIN, HLMAX, DT1MIN, DT1MAX, DT0MIN, DT0MAX, RMIN, and RMAX registers. Calculating formula for specified time, setting examples of each maximum/minimum value register during the specified time, and use for each register are described as follows. The symbols in table 16.4 correspond to the ones used in the figure 16.3 to figure 16.5. S.E = M (N + 1)/T S: Specified time of the NEC format E: Error from the NEC format T: Frequency of the reference clock (Hz) set by the CLK1 and CLK0 bits in CCR1 (, /2, /4, or sub) N: Setting value in BRR (0 N 255) M: Value in the maximum/minimum value setting register Rev. 1.00 Apr. 28, 2008 Page 484 of 994 REJ09B0452-0100 Section 16 CIR Interface Table 16.4 An Example of Signal Type Determination Register Setting Register Setting Name Symbol Value HHMIN A H'079 Setting Time Prescribed Time (Error: 30%) Notes HHMIN9 to HHMIN0 Description Minimum high-level period for a header or repeat header and minimum lowlevel period for a stop Maximum high-level period for a header or repeat header and maximum lowlevel period for a stop Minimum low-level period for a header Maximum low-level period for a header 6.34 ms 6.3 ms HHMAX A H'0DF 11.7 ms 11.7 ms HHMAX9 to HHMAX0 HLMIN HLMAX B B C H'3D H'6F H'07 3.20 ms 3.15 ms 5.82 ms 5.85 ms 0.37 ms 0.39 ms Minimum value of low/high- DT0MIN level period for logic 0, highlevel period for logic 1, and high-level period for a burst Maximum value of low/high- DT0MAX C level period for logic 0, highlevel period for logic 1, and high-level period for a burst Minimum low-level period for logic 1 Maximum low-level period for logic 1 Minimum low-level period for a repeat header Maximum low-level period for a repeat header DT1MIN D H'0D 0.68 ms 0.73 ms H'0F H'1B H'1F H'37 0.78 ms 0.78 ms 1.42 ms 1.46 ms 1.62 ms 1.58 ms 2.88 ms 2.92 ms DT1MAX D RMIN RMAX E E Note: The above table shows the values when the system clock is 10MHz, CLK1, CLK0 = B'10, and BRR = H'82 (when the error is 30%). Rev. 1.00 Apr. 28, 2008 Page 485 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.4.2 Operation of FIFO Register A FIFO structure provides first-in first-out operation. Operation of the FIFO when it receives data three times (byte 0, byte 1, and byte 2 in order) and is then read three times is as shown below. Operation for first reception of data Number of bytes FIFO contents Operation for data reception three times Number of bytes FIFO contents 1 2 3 4 . . . 18 Byte 0 H'00 H'00 H'00 . . . H'00 1 2 3 4 . . . 18 Byte 0 Byte 1 Byte 2 H'00 . . . H'00 Figure 16.6 Operation when FIFO Data is Received First read Number of bytes FIFO Contents Second read Number of bytes 1 2 3 4 . . . 18 H'00 FIFO Contents Third read Number of bytes FIFO contents 1 2 3 4 . . . 18 Byte 1 Byte 2 H'00 H'00 . . . H'00 Byte 2 H'00 H'00 H'00 . . . 1 2 3 4 . . . 18 H'00 H'00 H'00 H'00 . . . H'00 Figure 16.7 Operation when FIFO Data is Read Rev. 1.00 Apr. 28, 2008 Page 486 of 994 REJ09B0452-0100 Section 16 CIR Interface In case of reading more bytes than the number that has been received, (number of received bytes + 1) of data are always read out from the FIFO. Reception of more than 18 bytes by the FIFO structure for this CIR module leads to an overrun. When an overrun occurs, only values up to the 18th byte to have been received are read out in response to the reading of more than 18 bytes. 16.4.3 Operation in Watch Mode Initiate the transition to watch mode after making the below settings for the mode transition. * Select the subclock (sub) as the operating clock for the CIR module. * Enable the CIR header-detected interrupt. For a transition from watch mode to high-speed mode, the CIR module generates an interrupt on detection of a received header, in accord with the settings before the transition. The module is released from watch mode when the interrupt is generated, and makes the transition to the high- or medium-speed mode. 16.4.4 Switching between System Clock and Sub Clock If the operating clock is switched from the system clock to the subclock (sub) while the CIR module is operating, operation may not proceed correctly. To switch the operating clock, be sure to stop the CIR module (by clearing the CIRE bit) beforehand. Rev. 1.00 Apr. 28, 2008 Page 487 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.5 Noise Canceler Circuit The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise canceler circuit, and select the division ratio for generating the noise canceler circuit clock, respectively. Figure 16.6 shows a block diagram of the noise canceler circuit. CIR DATA FLTE = 0 F. F CIRI F. F F. F F. F F. F Noise canceler circuit F. F F. F F. F FLTCK1, FLTCK0 Clock generation circuit for noise canceler circuit /2 /4 sub CIR sampling clock Sampling clock generation circuit Figure 16.8 Noise Canceler Circuit Rev. 1.00 Apr. 28, 2008 Page 488 of 994 REJ09B0452-0100 Section 16 CIR Interface Table 16.5 shows sample settings for the noise canceler circuit. Table 16.5 Sample Settings for Noise Canceler Circuit CLK1 and CLK0 BRR Setting Setting H'80 FLTCK1 and FLTCK0 Setting Not divided CIR Number of Stages Width of Sampling of Noise Canceler Noise Clock Circuit Cancellation 12.9 s 0 1 2 3 4 Divided by 2 25.8 s 0 2 4 Divided by 4 51.6 s 0 2 4 Divided by 8 103.2 s 0 2 4 sub H'00 Not divided 31.3 s 0 1 2 3 4 Divided by 2 62.5 s 0 2 4 Divided by 4 125 s 0 2 4 Divided by 8 250 s 0 2 4 12.9 s 25.8 s 38.7 s 51.6 s 64.5 s 25.8 s 77.4 s 129 s 51.6 s 154.8 s 258 s 103.2 s 309.6 s 516 s 31.3 s 62.5 s 93.8 s 125 s 156 s 62.5 s 187.5 s 312.5 s 125 s 375 s 625 s 250 s 750 s 1.25 ms 10 MHz Rev. 1.00 Apr. 28, 2008 Page 489 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.6 Reset Conditions The range of initialization caused by a system reset, a software reset controlled by the SRES bit in CCR1, or an abort is shown in table 16.6. Table 16.6 Range of Initialization of CIR HHMIN, HHMAX, HLMIN, HLMAX, DT0MIN, DT0MAX, DT1MIN, DT1MAX, CCR1, CCR2, RFMBN bit CEIR in HHMIN CIRRDR System reset Initialized Initialized Initialized Retained Initialized Initialized Retained CSTR Initialized Initialized Sequence Block BRR Initialized Initialized Initialized Initialized Retained SRES software Retained reset Abort Retained Retained * Initialized (CIRBUSY is initialized.) 16.7 Interrupt Sources The CIR has six interrupt source flags for this LSI. Setting the corresponding enable bit to 1 enables the relevant interrupt request to be issued. Since the six interrupt requests are allocated to one vector address, it is necessary for the CPU to check the interrupt request flags in order to determine which interrupt source has caused the interrupt to be requested. Table 16.7 Interrupt Sources Interrupt Name RENDI OVEI REPI FREI ABI HEADFI Interrupt Source Flags REND OVRF REPF FRF ABF HEADF Receive end Overrun error Repeat detection Framing error Abort Header detection Interrupt Enable Bit RENDIE OVEIE REPIE FREIE ABIE HEADFIE Rev. 1.00 Apr. 28, 2008 Page 490 of 994 REJ09B0452-0100 Section 16 CIR Interface 16.8 (1) Usage Note CIR Register Setting Before starting the CIR reception, set the CIR by following the flow shown in figure 16.7. Start of setting Clear MSTPA3 bit in MSTPCRA to 0. Set CPHS bit in CCR1. Set each register. Clear CSTR flag. Set CEIR. Set CIRE bit in CCR1 to 1. End of setting Figure 16.9 CIR Setting Flow The CPHS bit in CCR1 should be set before starting reception. When the CIRI pin is high in the idle state, set the CPHS bit to 1. When it is low in the idle state, clear the bit to 0. The BRR register is initialized to H'FF by setting the SRES bit in CCR1 to 1. After setting each register in the CIR, set the CIRE bit in CCR1 to 1 to enable the CIR reception. (2) Switching between System Clock and Sub Clock The CIR is capable of remote-control reception by using the sub clock in watch mode. Before switching between the system clock and the sub clock, the CIR must be stopped by clearing the CIRE bit to 0. Rev. 1.00 Apr. 28, 2008 Page 491 of 994 REJ09B0452-0100 Section 16 CIR Interface (3) Overrun Operation with the NEC format (2 Bytes are Used) When the reception signal format select bits (bits TFM1 and TFM0 in CCR2) are set to the NEC format (2 bytes are used), the OVRF bit in CSTR is set to indicate the overrun on the reception of the 18th byte by the receive data register. However, this does not affect the contents of the 18th- byte data. Rev. 1.00 Apr. 28, 2008 Page 492 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Section 17 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO buffers (SCIF) that supports asynchronous serial communication. The SCIF enables asynchronous serial communication with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART). The SCIF also has independent 16-stage FIFO buffers for transmission and reception to provide efficient high-speed continuous communication. In addition, the SCIF can be connected to the LPC interface for direct control from the LPC host. 17.1 Features * Full-duplex communication: The transmitter and receiver are independent, enabling transmission and reception to be executed simultaneously. Both the transmitter and receiver use 16-stage FIFO buffering, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * Modem control function * Data length: Selectable from 5, 6, 7, and 8 bits * Parity: Selectable from even parity, odd parity, and no parity * Stop bit length: Selectable from 1, 1.5, and 2 bits * Receive error detection: Parity, overrun, and framing errors * Break detection Rev. 1.00 Apr. 28, 2008 Page 493 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Figure 17.1 shows a block diagram of the SCIF. Internal data bus Bus interface LPC interface FIER FIIR FFCR FLCR FMCR FLSR FMSR FSCR Modem controller PB2/RI PB3/DCD PB4/DSR PB5/DTR PB6/CTS PB7/RTS FTHR Transmit FIFO (16 bytes) Register transmission/ reception control Transmission (1 byte) FRBR FTSR P50/FTxD SCIFCR SCIF interrupt request Receive FIFO (16 bytes) Reception (1 byte) FRSR P51/FRxD FDLH FDLL System clock LCLK Clock selection/ divider circuit SCLK Transfer clock Baud rate generator [Legend] FRSR: Receive shift register FTSR: Transmitter shift register FRBR: Receive buffer register FTHR: Transmitter holding register FDLH, FDLL: Divisor latch H, L FIER: Interrupt enable register FIIR: Interrupt identification register FFCR: FLCR: FMCR: FLSR: FMSR: FSCR: SCIFCR: FIFO control register Line control register Modem control register Line status register Modem status register Scratch pad register SCIF control register Figure 17.1 Block Diagram of SCIF Rev. 1.00 Apr. 28, 2008 Page 494 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.2 Input/Output Pins Table 17.1 lists the SCIF input/output pins. Table 17.1 Pin Configuration Pin Name FTxD FRxD RI DCD DSR DTR CTS RTS Port P50 P51 PB2 PB3 PB4 PB5 PB6 PB7 Input/Output Output Input Input Input Input Output Input Output Function Transmit data output Receive data input Ring indicator input Data carrier detect input Data set ready input Data terminal ready output Transmission permission input Transmission request output Rev. 1.00 Apr. 28, 2008 Page 495 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3 Register Descriptions The SCIF has the following registers. The register configuration of the SCIF is shown below. Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details, see table 17.3. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and serial IRQ control register 4 (SIRQCR4), see section 20, LPC Interface (LPC). Table 17.2 Register Configuration Data Bus Width 8 8 8 Register Name Host interface control register 5 Module stop control register B Receive buffer register Transmitter holding register Divisor latch L Interrupt enable register Divisor latch H Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register Scratch pad register SCIF control register SCIF address register H SCIF address register L Serial IRQ control register 4 Abbreviation HICR5 MSTPCRB FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR SCIFADRH SCIFADRL SIRQCR4 R/W R/W R/W R W R/W R/W R/W R W R/W R/W R R R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'01 H'00 H'00 H'00 H'60 H'00 H'00 H'03 H'F8 H'00 Address H'FFFE33 H'FFFE7F H'FFFC20 H'FFFC21 8 H'FFFC22 8 H'FFFC23 H'FFFC24 H'FFFC25 H'FFFC26 H'FFFC27 H'FFFC28 H'FFFDC4 H'FFFDC5 H'FFFE3B 8 8 8 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 496 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.3 Register Access SCIFE Bit in HICR5 Bit 3 in MSTPCRB SCIFCR Other than SCIFCR 0 H8S CPU access*2 H8S CPU 2 access* 0 1 Access disabled Access disabled 0 H8S CPU access*2 LPC access*1 1 1 Access disabled LPC access*1 Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF. 2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00. 17.3.1 Receive Shift Register (FRSR) FRSR is a register that receives data and converts serial data input from the FRxD pin to parallel data. It stores the data in the order received from the LSB (bit 0). When one frame of serial data has been received, the data is transferred to FRBR. FRSR cannot be read from the CPU/LPC interface. 17.3.2 Receive Buffer Register (FRBR) FRBR is an 8-bit read-only register that stores received serial data. It can read data correctly when the DR bit in FLSR is set. When the FIFO is disabled, the data in FRBR must be read before the next data is received. If new data is received before the remaining data is read, the data is overwritten, resulting in an overrun error. When this register is read with the FIFO enabled, the first buffer of the receive FIFO is read. When the receive FIFO becomes full, the subsequent receive data is lost, resulting in an overrun error. Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R Description Stores received serial data. The data is 16 bytes when the FIFO is enabled. Rev. 1.00 Apr. 28, 2008 Page 497 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.3 Transmitter Shift Register (FTSR) FTSR is a register that converts parallel data from the FTxD pin to serial data and then transmits the serial data. When one frame transmission of serial data is completed, the next data is transferred from FTHR. The serial data is transmitted from the LSB (bit 0). FTSR cannot be written from the H8S CPU/LPC interface. 17.3.4 Transmitter Holding Register (FTHR) FTHR is an 8-bit write-only register that stores serial transmit data. It is accessible when the DLAB bit in FLCR is 0. Write transmit data while the THRE bit in FLCR is set to 1. Data can be written to FTHR when the THRE bit is set with the FIFO disabled. If data is written to FTHR when the THRE bit is not set, the data is overwritten. While the THRE bit is set with the FIFO enabled, up to 16 bytes of data can be written. If data is written with the FIFO full, the written data is lost. Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value R/W W Description Stores serial data to be transmitted. The data is 16 bytes when the FIFO is enabled. 17.3.5 Divisor Latch H, L (FDLH, FDLL) The FDLH and FDLL are registers used to set the baud rate. They are accessible when the DLAB bit in FLCR is 1. Frequency division ranging from 1 to (216 - 1) can be set with these registers. The frequency divider circuit stops when both of FDLH and FDLL are 0 (initial value). * FDLH Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R/W Description Upper 8 bits of divisor latch Rev. 1.00 Apr. 28, 2008 Page 498 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) * FDLL Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value All 0 R/W R/W Description Lower 8 bits of divisor latch Baud rate = (Clock frequency input to baud rate generator) / (16 x divisor value) 17.3.6 Interrupt Enable Register (FIER) FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR is 0. Bit 7 to 4 3 Bit Name EDSSI Initial Value All 0 0 R/W R R/W Description Reserved This bit is always read as 0 and cannot be modified. Modem Status Interrupt Enable 0: Modem status interrupt disabled 1: Modem status interrupt enabled 2 ELSI 0 R/W Receive Line Status Interrupt Enable 0: Receive line status interrupt disabled 1: Receive line status interrupt enabled 1 ETBEI 0 R/W FTHR Empty Interrupt Enable 0: FTHR empty interrupt disabled 1: FTHR empty interrupt enabled 0 ERBFI 0 R/W Receive Data Ready Interrupt Enable A character timeout interrupt is included when the FIFO is enabled. 0: Receive data ready interrupt disabled 1: Receive data ready interrupt enabled Rev. 1.00 Apr. 28, 2008 Page 499 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.7 Interrupt Identification Register (FIIR) FIIR consists of bits that identify interrupt sources. For details, see table 17.4. Bit 7 6 Bit Name FIFOE1 FIFOE0 Initial Value 0 0 R/W R R Description FIFO Enable 1, 0 These bits indicate the transmit/receive FIFO setting. 00: Transmit/receive FIFOs disabled 11: Transmit/receive FIFOs enabled 5, 4 All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 2 1 INTID2 INTID1 INTID0 0 0 0 R R R Interrupt ID2, ID1, ID0 These bits Indicate the interrupt of the highest priority among the pending interrupts. 000: Modem status 001: FTHR empty 010: Receive data ready 011: Receive line status 110: Character timeout (when the FIFO is enabled) 0 INTPEND 1 R Interrupt Pending Indicates whether one or more interrupts are pending. 0: Interrupt pending 1: No interrupt pending Rev. 1.00 Apr. 28, 2008 Page 500 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.4 Interrupt Control Function FIIR INTID 2 0 0 1 0 1 0 0 1 INTPEND Priority Type of Interrupt 1 0 1 (high) No interrupt Receive line status Interrupt Source None Setting/Clearing of Interrupt Clearing of Interrupt - Overrun error, FLSR read parity error, framing error, break interrupt FRBR read or receive FIFO is below trigger level. 0 1 0 0 2 Receive data ready Receive data remaining, FIFO trigger level 1 1 0 0 2 Character timeout No data is input to FRBR read (with FIFO enabled) or output from the receive FIFO for the 4-character time period while one or more characters remain in the receive FIFO. FTHR empty Modem status FTHR empty FIIR read or FTHR write 0 0 0 0 1 0 0 0 3 4 (low) CTS, DSR, RI, DCD FMSR read Rev. 1.00 Apr. 28, 2008 Page 501 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.8 FIFO Control Register (FFCR) FFCR is a write-only register that controls transmit/receive FIFOs. Bit 7 6 Bit Name RCVRTRIG1 RCVRTRIG0 Initial Value R/W 0 0 W W Description Receive FIFO Interrupt Trigger Level 1, 0 These bits set the trigger level of the receive FIFO interrupt. 00: 1 byte 01: 4 bytes 10: 8 bytes 11: 14 bytes 5, 4 3 2 - DMAMODE XMITFRST 0 0 W Reserved These bits cannot be modified. DMA Mode This bit is not supported and cannot be modified. Transmit FIFO Reset The transmit FIFO data is cleared when 1 is written. However, FRSR data is not cleared. This bit is automatically cleared. 1 RCVRFRST 0 W Receive FIFO Reset The receive FIFO data is cleared when 1 is written. However, FTSR data is not cleared. This bit is automatically cleared. 0 FIFOE 0 W FIFO Enable 0: Transmit/receive FIFOs disabled All bytes of these FIFOs are cleared. 1: Transmit/receive FIFOs enabled Rev. 1.00 Apr. 28, 2008 Page 502 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.9 Line Control Register (FLCR) FLCR sets formats of the transmit/receive data. Bit 7 Bit Name DLAB Initial Value 0 R/W R/W Description Divisor Latch Address FDLL and FDLH are placed at the same addresses as the FRBR/FTHR and FIER addresses. This bit selects which register is to be accessed. 0: FRBR/FTHR and FIER access enabled 1: FDLL and FDLH access enabled 6 BREAK 0 R/W Break Control Generates a break by driving the serial output signal FTxD low. The break state is released by clearing this bit. 0: Break released 1: Break generated 5 STICK PARITY 0 R Stick Parity These bits are not supported in this LSI. These bits are always read as 0 and cannot be modified. 4 EPS 0 R/W Parity Select Selects even or odd parity when the PEN bit is 1. 0: Odd parity 1: Even parity 3 PEN 0 R/W Parity Enable Selects whether to add a parity bit for data transmission and whether to perform a parity check for data reception. 0: No parity bit added/parity check disabled 1: Parity bit added/parity check enabled Rev. 1.00 Apr. 28, 2008 Page 503 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 2 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Specifies the stop bit length for data transmission. For data reception, only the first stop bit is checked regardless of the setting. 0: 1 stop bit 1: 1.5 stop bits (data length: 5 bits) or 2 stop bits (data length: 6 to 8 bits) 1 0 CLS1 CLS0 0 0 R/W R/W Character Length Select 1, 0 These bits specify transmit/receive character data length. 00: Data length is 5 bits 01: Data length is 6 bits 10: Data length is 7 bits 11: Data length is 8 bits 17.3.10 Modem Control Register (FMCR) FMCR controls output signals. Bit 7 to 5 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 1 and cannot be modified. 4 LOOP BACK 0 R/W Loopback Test The transmit data output is internally connected to the receive data input, and the transmit data output pin (FRxD) becomes 1. The receive data input pin is disconnected from external sources. The four modem control input pins (DSR, CTS, RI, and DCD) are disconnected from external sources, and the pins are internally connected to the four modem control output signals (DTR, RTS, OUT1, and OUT2), respectively. The transmit data is received immediately in loopback mode. Enabling/disabling of interrupts is set by the OUT2LOOP bit in SCIFCR and FIER. 0: Loopback function disabled 1: Loopback function enabled Rev. 1.00 Apr. 28, 2008 Page 504 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name OUT2 Initial Value 0 R/W R/W Description OUT2 * Normal operation Enables or disables the SCIF interrupt. 0: Interrupt disabled 1: Interrupt enabled * Loopback test Internally connected to the DCD input pin. 2 OUT1 0 R/W OUT1 * * Normal operation Loopback test No effect on operation Internally connected to the RI input pin. 1 RTS 0 R/W Request to Send Controls the RTS output. 0: RTS output is high level 1: RTS output is low level 0 DTR 0 R/W Data Terminal Ready Controls the DTR output. 0: DTR output is high level 1: DTR output is low level Rev. 1.00 Apr. 28, 2008 Page 505 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.11 Line Status Register (FLSR) FLSR is a read-only register that indicates the status information of data transmission. Bit 7 Bit Name Initial Value R/W R Description Receive FIFO Error Indicates that at least one data error (parity error, framing error, or break interrupt) has occurred when the FIFO is enabled. 0: No receive FIFO error [Clearing condition] When FRBR is read or FLSR is read while there is no remaining data that could cause an error after an FIFO clear. 1: A receive FIFO error [Setting condition] When at least one data error (parity error, framing error, or break interrupt) has occurred in the FIFO 6 TEMT 1 R Transmitter Empty Indicates whether transmit data remains. * When the FIFO is disabled 0: Transmit data remains in FTHR or FTSR. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in FTHR and FTSR. [Setting condition] When no transmit data remains in FTHR and FTSR. * When the FIFO is enabled 0: Transmit data remains in the transmit FIFO or FTSR. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in the transmit FIFO and FTSR. [Setting condition] When no transmit data remains in the transmit FIFO and FTSR RXFIFOERR 0 Rev. 1.00 Apr. 28, 2008 Page 506 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 5 Bit Name THRE Initial Value R/W 1 R Description FTHR Empty Indicates that FTHR is ready to accept new data for transmission. * When the FIFO is enabled 0: Transmit data of one or more bytes remains in the transmit FIFO. [Clearing condition] Transmit data is written to FTHR. 1: No transmit data remains in the transmit FIFO. [Setting condition] When the transmit FIFO becomes empty * When the FIFO is disabled 0: Transmit data remains in FTHR. [Clearing condition] Transmit data is written to FTHR 1: No transmit data in FTHR [Setting condition] When data transfer from FTHR to FTSR is completed 4 BI 0 R Break Interrupt Indicates detection of the receive data break signal. When the FIFO is enabled, a break interrupt occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. Reception of the next data starts after the input receive data becomes mark and a valid start bit is received. 0: Break signal not detected [Clearing condition] FLSR read 1: Break signal detected [Setting condition] When input receive data stays at space (low level) for a reception time exceeding the length of one frame Rev. 1.00 Apr. 28, 2008 Page 507 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 3 Bit Name FE Initial Value R/W 0 R Description Framing Error Indicates that the stop bit of the receive data is invalid. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. The UART attempts resynchronization after a framing error occurs. The UART, which assumes that the framing error is due to the next start bit, samples the start bit and treats it as a start bit. 0: No framing error [Clearing condition] FLSR read 1: A framing error [Setting condition] Invalid stop bit in the receive data 2 PE 0 R Parity Error This bit indicates a parity error in the receive data when the PEN bit in FLCR is 1. When the FIFO is enabled, this error occurs in any receive data in the FIFO, and this bit is set when the receive data is in the first FIFO buffer. 0: No parity error [Clearing condition] FLSR read If this bit is set during an overrun error, read FLSR twice. 1: A parity error [Setting condition] Detection of parity error in receive data Rev. 1.00 Apr. 28, 2008 Page 508 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name OE Initial Value R/W 0 R Description Overrun Error Indicates occurrence of an overrun error. * When the FIFO is disabled When reception of the next data has been completed without the receive data in FRBR having been read, an overrun error occurs and the previous data is lost. * When the FIFO is enabled When the FIFO is full and reception of the next data has been completed, an overrun error occurs. The FIFO data is retained, but the last received data is lost. 0: No overrun error [Clearing condition] FLSR read 1: An overrun error [Setting condition] Occurrence of an overrun error 0 DR 0 R Data Ready Indicates that receive data is stored in FRBR or the FIFO. 0: No receive data [Clearing condition] FRBR is read or all of the FIFO data is read. 1: Receive data remains. [Setting condition] Reception of data Rev. 1.00 Apr. 28, 2008 Page 509 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.12 Modem Status Register (FMSR) FMSR is a read-only register that indicates the status of or a change in the modem control pins. Bit 7 6 5 4 3 Bit Name DCD RI DSR CTS DDCD Initial Value R/W Undefined Undefined Undefined Undefined 0 R R R R R Description Data Carrier Detect Indicates the inverted state of the DCD input pin. Ring Indicator Indicates the inverted state of the RI input pin. Data Set Ready Indicates the inverted state of the DSR input pin. Clear to Send Indicates the inverted state of the CTS input pin. Delta Data Carrier Indicator Indicates a change in the DCD input signal after the DDCD bit is read. 0: No change in the DCD input signal after FMSR read [Clearing condition] FMSR read 1: A change in the DCD input signal after FMSR read [Setting condition] A change in the DCD input signal 2 TERI 0 R Trailing Edge Ring Indicator Indicates a rise in the RI input signal after the TERI bit is read. 0: No change in the RI input signal after FMSR read [Clearing condition] FMSR read 1: A rise in the RI input signal after FMSR read [Setting condition] A rise in the RI input pin Rev. 1.00 Apr. 28, 2008 Page 510 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Bit 1 Bit Name DDSR Initial Value R/W 0 R Description Delta Data Set Ready Indicator Indicates a change in the DSR input signal after the DDSR bit is read. 0: No change in the DSR input signal after FMSR read [Clearing condition] FMSR read 1: A change in the DSR input signal after FMSR read [Setting condition] A change in the DSR input signal 0 DCTS 0 R Delta Clear to Send Indicator Indicates a change in the CTS input signal after the DCTS bit is read. 0: No change in the CTS input signal after FMSR read [Clearing condition] FMSR read 1: A change in the CTS input signal after FMSR read [Setting condition] A change in the CTS input signal 17.3.13 Scratch Pad Register (FSCR) FSCR is not used for SCIF control, but is used to temporarily store program data. Bit 7 to 0 Bit Name Bit 7 to bit 0 Initial Value R/W All 0 R/W Description Temporarily stores program data. Rev. 1.00 Apr. 28, 2008 Page 511 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.3.14 SCIF Control Register (SCIFCR) SCIFCR controls SCIF operations, and is accessible only from the CPU. Bit 7 6 5 4 Bit Name SCIFOE1 SCIFOE0 OUT2LOOP Initial Value R/W 0 0 0 0 R/W R/W R/W R/W Description These bits enable or disable PORT output of the SCIF. For details, see table 17.5. Reserved Do not change the initial value. Enables or disables interrupts during a loopback test. 0: Interrupt enabled 1: Interrupt disabled 3 2 CKSEL1 CKSEL0 0 0 R/W R/W These bits select the clock (SCLK) to be input to the baud rate generator. 00: LCLK divided by 18 01: System clock divided by 11 10: Reserved for LCLK (not selectable) 11: Reserved for system clock (not selectable) 1 SCIFRST 0 R/W Resets the baud rate generator, FRSR, and FTSR. 0: Normal operation 1: Reset 0 REGRST 0 R/W Resets registers (except SCIFCR) accessible from the H8S CPU or LPC interface. 0: Normal operation 1: Reset Rev. 1.00 Apr. 28, 2008 Page 512 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.5 SCIF Output Setting Bit 3 in HICR5 0 Bit 7 in SCIFCR Bit 6 in SCIFCR PB7 and PB5 pins P50 pin 0 0 PORT PORT 0 0 1 PORT PORT 0 1 0 SCIF SCIF 0 1 1 PORT SCIF 1 0 0 SCIF SCIF 1 0 1 PORT SCIF 1 1 0 SCIF SCIF 1 1 1 PORT SCIF Note: P51, PB2 to PB4, and PB6 are input to the SCIF even when the outputs on the PB7, PB5, and P50 pins are set to PORT. Rev. 1.00 Apr. 28, 2008 Page 513 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.4 17.4.1 Operation Baud Rate The SCIF includes a baud rate generator and can set the desired baud rate using registers FDLH, FDLL, and the CKSEL bit in SCIFCR. Table 17.6 shows an example of baud rate settings. Table 17.6 Example of Baud Rate Settings 00 CKSEL1, CKSEL0 Baud rate 50 75 110 300 600 1200 1800 2400 4800 9600 14400 19200 38400 57600 115200 LCLK (33 MHz) divided by 18 FDLH, FDLL (Hex) 0900 0600 0417 0180 00C0 0060 0040 0030 0018 000C 0008 0006 0003 0002 0001 Error (%) 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 0.54 % 01 System Clock (20 MHz) divided by 11 FDLH, FDLL (Hex) 0900 0600 0417 0180 00C0 0060 0040 0030 0018 000C 0008 0006 0003 0002 0001 01 System Clock (10 MHz) divided by 11 Error (%) 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % FDLH, FDLL Error (%) (Hex) 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 1.36 % 0480 0300 00C0 0060 0030 0020 0018 000C 0006 0004 0003 0001 Rev. 1.00 Apr. 28, 2008 Page 514 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.2 Operation in Asynchronous Communication Figure 17.2 illustrates the typical format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the transmission line is usually held high in the mark state (high level). The SCIF monitors the transmission line, and when it detects the space state (low level), recognizes a start bit and starts serial communication. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage FIFO buffered structure so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Idle state (mark state) 1 Serial data 1 0 Start bit 1 bit D0 D1 D2 D3 D4 D5 D6 D7 0/1 Parity bit 1 bit or none 1 1 Stop bit Transmit/receive data 5, 6, 7, or 8 bits 1, 1.5, or 2 bits One unit of transfer data (character or frame) Figure 17.2 Data Format in Serial Transmission/Reception (Example with 8-Bit Data, Parity and 2 Stop Bits) Rev. 1.00 Apr. 28, 2008 Page 515 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.3 (1) Initialization of the SCIF Initialization of the SCIF Use an example of the flowchart in figure 17.3 to initialize the SCIF before transmitting or receiving data. Start initialization Clear module stop [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/ output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR. [1] [2] Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH. [3] The initial value of FDLL and FDLH is 0. Set a value within the range from 1 to 65535. [4] Clear the DLAB bit in FLCR to 0 to disable access to FDLL and FDLH. [5] Select parity with the EPS and PEN bits in FLCR, and set the stop bit with the STOP bit in FLCR. Then, set the data length with the CLS1 and CLS0 bits in FLCR. Set SCIFCR Set DLAB bit in FLCR to 1 [2] Set FDLH and FDLL [3] [4] Clear DLAB bit in FLCR to 0 Set data transfer format in FLCR [5] FIFOs used? Yes Set FIFOE bit in FFCR to 1 [6] [7] No Set receive FIFO trigger level in FFCR Set XMITFRST and RCVRFRST bits in FFCR to 1 to reset FIFOs [8] [6] When FIFOs are used, set the FIFOE bit in FFCR to 1. Set interrupt enable bits in FIER [9] [7] Set the receive FIFO trigger level with the RCVRTRIG1 and RCVRTRIG0 bits in FFCR. [8] Set the XMITFRST and RCVRFRST bits in FFCR to 1 to reset the FIFOs. [9] Enable or disable an interrupt with the EDSSI, ELSI, ETBEI, and ERBFI bits in FIER and the OUT2 bit in FMCR. End of Initialization Figure 17.3 Example of Initialization Flowchart Rev. 1.00 Apr. 28, 2008 Page 516 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (2) Serial Data Transmission Figure 17.4 shows an example of the data transmission flowchart. Initialization Start transmission Read THRE flag in FLSR [1] [1] Confirm that the THRE flag in FLSR is 1, and write transmit data to FTHR. When FIFOs are used, write 1-byte to 16-byte transmit data. When the OUT2 bit in FMCR and the ETBEI bit in FIER are set to 1, an FTHR empty interrupt occurs. When data is written to FTHR, it is transferred automatically to FTSR. The data is then transmitted from the FTxD pin in the order of the start bit, transmit data, parity bit, and stop bit. [2] Read the TEMT flag in FLSR, and confirm that TEMT is set to 1 to ensure that all transmit data has been transmitted. [3] To output a break at the end of serial transmission, set the BREAK bit in FLCR to 1. After completion of the break time, clear the BREAK bit in FLCR to 0 to clear the break. THRE = 1? No Yes Write transmit data to FTHR No All data written Yes Read TEMT flag in FLSR [2] TEMT = 1 No Yes Break output No [3] Yes Set BREAK bit in FLCR to 1 Break time completed Yes Clear BREAK bit in FLCR to 0 (End of transmission or transmission standby) Figure 17.4 Example of Data Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 517 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (3) Serial Data Reception Figure 17.5 shows an example of the data reception flowchart. Initialization [1] Confirm that the DR flag in FLSR is 1 to ensure that receive data is in the buffer. When the OUT2 bit in FMCR and the ERBFI bit in FIER are set to 1, a Start reception [2] Read DR flag in FLSR [1] receive data ready interrupt occurs. Read the RXFIFOERR, BI, FE, PE, and OE flags in FLSR to ensure that no error has occurred. If an error has occurred, perform error processing. When the OUT2 bit in FMCR and the ELSI bit in FIER are No DR = 1 [3] Yes [4] Read FLSR [2] set to 1, a receive line status interrupt occurs. Read the receive data in FRBR. Check the DR flag in FLSR. When the DR flag is cleared to 0 and all data has been read, data reception is complete. RXFIFOERR = 1, BI = 1, FE = 1, PE = 1, or OE = 1 No Read FRBR Yes Error processing [3] Read FLSR [4] No DR = 0 Yes No All data read Yes (End of reception or reception standby) Figure 17.5 Example of Data Reception Flowchart Rev. 1.00 Apr. 28, 2008 Page 518 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.4 Data Transmission/Reception with Flow Control The following shows examples of data transmission/reception for flow control using CTS and RTS. (1) Initialization Figure 17.6 shows an example of the initialization flowchart. Start initialization Clear module stop [1] Select an input clock with the CKSEL1 and CKSEL0 bits in SCIFCR. Set the SCIF input/output pins with the SCIFOE1 and SCIFOE0 bits in SCIFCR. [2] Set the DLAB bit in FLCR to 1 to enable access to FDLL and FDLH. [3] The initial value of FDLL and FDLH is 0. Set a value within the range from 1 to 65535. [4] Clear the DLAB bit in FLCR to 0 to disable access to FDLL and FDLH. [5] Select parity with the EPS and PEN bits in FLCR, and set the stop bit with the STOP bit in FLCR. Then, set the data length with the CLS1 and CLS0 bits in FLCR. Set the FIFOE bit in FFCR to 1 to enable the FIFO. [6] Set the receive FIFO trigger level with the RCVRTRIG1 and RCVRTRIG0 bits in FFCR. Select the best trigger level to prevent an overflow of the receive FIFO. [7] Set the EDSSI and ERBFI bits in FIER to 1 to enable a modem status interrupt and receive data ready interrupt. [8] Set the RTS bit in FMCR to 1. Set SCIFCR [1] Set DLAB bit in FLCR to 1 [2] Set FDLH and FDLL [3] [4] Clear DLAB bit in FLCR to 0 Set data transfer format in FLCR [5] Set FIFO with FFCR [6] Set interrupt enable bits in FIER [7] Set RTS bit in FMCR to 1 [8] (Transmission/reception standby flow) Figure 17.6 Example of Initialization Flowchart Rev. 1.00 Apr. 28, 2008 Page 519 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (2) Data Transmission/Reception Standby Figure 17.7 shows an example of the data transmission/reception standby flowchart. Initialization [1] When a receive data ready interrupt occurs, go to the reception flow. [2] When transmit data exists, go to the transmission flow. Receive data ready interrupt? No Yes [1] (Reception flow) Yes Transmit data exists? [2] No (Transmission flow) Figure 17.7 Example of Data Transmission/Reception Standby Flowchart Rev. 1.00 Apr. 28, 2008 Page 520 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (3) Data Transmission Figure 17.8 shows an example of the data transmission flowchart. [1] Confirm that the CTS flag in FMSR is 1. Transmission/reception standby [2] Confirm that the THRE flag in FLSR is 1 to ensure that the transmit FIFO is empty. [1] [3] Write up to 16 bytes of transmit data in the transmit FIFO. If the transmit data is 17 bytes or more, return to step [2] to write transmit data in the transmit FIFO again. [4] When all of the data has been written, go to the transmission/reception standby flow. Read CTS flag in FMSR CTS = 1 Yes No Read THRE flag in FLSR [2] THRE = 1 Yes i0 No Write transmit data to transmit FIFO [3] ii+1 Yes All data written Yes (End of transmission or transmission standby) No i < 16? [4] No Figure 17.8 Example of Data Transmission Flowchart Rev. 1.00 Apr. 28, 2008 Page 521 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (4) Suspension of Data Transmission Figure 17.9 shows an example of the data transmission suspension flowchart. [1] Read the DCTS flag in FMSR in the modem status change interrupt processing routine. If the DCTS flag is set to 1, the transmission suspension processing starts. [2] Suspend data write to the transmit FIFO. DCTS = 1 Yes No Modem status change interrupt Read DCTS flag in FMSR [1] [3] Set the XMITFRST bit in FFCR to 1. (Other processing) [2] [4] Prepare for retransmission of data and go to the transmission flow. Suspend data write to transmit FIFO Set XMITFRST bit in FFCR to 1 [3] Prepare for retransmission [4] (Transmission flow) Figure 17.9 Example of Data Transmission Suspension Flowchart Rev. 1.00 Apr. 28, 2008 Page 522 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (5) Data Reception Figure 17.10 shows an example of the data reception flowchart. Receive data ready interrupt [1] When data is received, a receive data ready interrupt occurs. Go to the data reception flow by using this interrupt trigger. [1] [2] Confirm that the BI, FE, PE, and OE flags in FLSR are all cleared. If any one of these flags is set to 1, perform error processing. [3] Read the receive FIFO. [4] Check the DR flag in FLSR. When the DR flag is cleared and all of the data has been read, data reception is complete. Read FLSR BI = 1, FE = 1, PE = 1, or OE = 1 No Read receive FIFO Yes Error processing [2] Read FLSR [3] DR = 0 [4] (Transmission/reception standby flow) Figure 17.10 Example of Data Reception Flowchart Rev. 1.00 Apr. 28, 2008 Page 523 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) (6) Suspension of Data Reception Figure 17.11 shows an example of the data reception suspension flowchart. [1] When data is received at a trigger level higher than the receive FIFO trigger level specified in the initialization flow, a receive FIFO trigger level interrupt occurs. [2] Clear the RTS bit in FMCR to 0. Read receive FIFO [3] [3] Read the receive FIFO until the DR flag is cleared to 0. [4] Set the RTS bit in FMCR to 1, and then go to the transmission/reception standby flow. No Receive FIFO trigger level interrupt [1] Clear RTS bit in FMCR to 0 [2] Read FLSR DR = 0 Yes Set RTS bit in FMCR to 1 [4] (Transmission/reception standby flow) Figure 17.11 Example of Data Reception Suspension Flowchart Rev. 1.00 Apr. 28, 2008 Page 524 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.4.5 Data Transmission/Reception Through the LPC Interface As shown in table 17.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception shown in figures 17.3 to 17.5 to be made from the LPC interface. Table 17.7 shows the correspondence between LPC interface I/O address and access to the SCIF registers. For details of the LPC interface settings, see section 20, LPC interface (LPC). Table 17.7 Correspondence Between LPC Interface I/O Address and the SCIF Registers LPC Interface I/O Address Bits 15 to 3 SCIFADR (bits 15 to 3) Bit 2 0 Bit 1 0 Bit 0 0 R/W R W R/W SCIFADR (bits 15 to 3) 0 0 1 R/W R/W SCIFADR (bits 15 to 3) 0 1 0 R W SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) SCIFADR (bits 15 to 3) 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 R/W R/W R R R/W Condition FLCR[7] = 0 FLCR[7] = 0 FLCR[7] = 1 FLCR[7] = 0 FLCR[7] = 1 SCIF Register FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR Rev. 1.00 Apr. 28, 2008 Page 525 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.8 shows the range of initialization of the registers related to data transmission/reception through the LPC interface, making a classification by each mode. Table 17.8 Register States Register SCIFADRH Bits 15 to 8 SCIFADRL HICR5 SIRQCR4 SCIFCR Bits 7 to 0 SCIFE Bits 7 to 4, SCSIRQ3 to 0 SCIFOE1, SCIFOE0, OUT2LOOP, CKSEL1, CKSEL0, SCIFRST, REGRST Bits 7 to 0 Bits 7 to 0 Bits 7 to 0 Bits 7 to 0 System Reset LPC SCIFRST REGRST Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained LPC LPC Shutdown Abort Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Retained Initialized Retained Initialized Retained Initialized Retained Initialized Retained FRBR FTHR FDLL FDLH FIIR Initialized Retained Initialized Retained Initialized Retained Initialized Retained Initialized Initialized Retained Initialized Initialized Retained Initialized Initialized Retained Initialized Initialized Retained Initialized Initialized Retained Retained Retained Retained Retained Retained FIFOE1, Initialized Retained FIFOE0, INTID2 to INTID0, INTPEND RCVRTRIG1, RCVRTRIG0, XMITFRST, RCVRFRST, FIFOE DLAB, TREAK, EPS, PEN, STOP, CLS1, CLS0 Initialized Retained FFCR Initialized Initialized Retained Retained FLCR Initialized Retained Initialized Initialized Retained Retained Rev. 1.00 Apr. 28, 2008 Page 526 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) Register FMCR LOOP BACK, OUT2, OUT1, RTS, DTR RXFEFOERR, TEMT, THRE, BI, FE, PE, OE, DR DDCD, TERI, DDSR, DCTS Bits 7 to 0 System Reset LPC SCIFRST REGRST Reset LPC LPC Shutdown Abort Retained Initialized Retained Initialized Initialized Retained FLSR Initialized Retained Initialized Initialized Retained Retained FMSR FSCR Initialized Retained Initialized Retained Initialized Initialized Retained Initialized Initialized Retained Retained Retained Retained SCIF transmissio n sequencer (inner state) Initialized Initialized Retained Initialized Retained Rev. 1.00 Apr. 28, 2008 Page 527 of 994 REJ09B0452-0100 Section 17 Serial Communication Interface with FIFO (SCIF) 17.5 Interrupt Sources Table 17.9 lists the interrupt sources. A common interrupt vector is assigned to each interrupt source. When the LPC uses the SCIF, the LPC does not request any interrupts to be sent to the H8S CPU. The SERIRQ signal of the LPC interface transmits an interrupt request to the host. Table 17.9 Interrupt Sources Interrupt Name Receive line status Receive data ready Character timeout (when FIFO is enabled) FTHR empty Modem status Interrupt Source Overrun error, parity error, framing error, break interrupt Acceptance of receive data, FIFO trigger level No data is input to or output from the receive FIFO for the 4character time period while one or more characters remain in the receive FIFO. FTHR empty CTS, DSR, RI, DCD Low Priority High Table 17.10 shows the interrupt source, vector address, and interrupt priority. Table 17.10 Interrupt Source, Vector Address, and Interrupt Priority Interrupt Origin of Interrupt Source SCIF Interrupt Name SCIF (SCIF interrupt) Vector Number 82 Vector Address H'000148 ICR ICRC7 17.6 17.6.1 Usage Note Power-Down Mode When LCLK is Selected for SCLK To switch to watch mode or software standby mode when LCLK divided by 18 has been selected for SCLK, use the shutdown function of the LPC interface to stop LCLK. Rev. 1.00 Apr. 28, 2008 Page 528 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Section 18 I2C Bus Interface (IIC) This LSI has a three-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. 18.1 Features * Selection of addressing format or non-addressing format I2C bus format: addressing format with an acknowledge bit, for master/slave operation Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of the acknowledge output level in reception (I2C bus format) * Automatic loading of an acknowledge bit in transmission (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer. The wait request is cleared when the next transfer becomes possible. * Interrupt sources Data transfer end (including when a transition to transmit mode with I2C bus format occurs, when ICDR data is transferred from ICDRT to ICDRS or from ICDRS to ICDRR, or during a wait state) Address match: When any slave address matches or the general call address is received in slave receive mode with I2C bus format (including address reception after loss of master arbitration) Arbitration lost Start condition detection (in master mode) Stop condition detection (in slave mode) Rev. 1.00 Apr. 28, 2008 Page 529 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 * Selection of 16 internal clocks (in master mode) * Direct bus drive (SCL/SDA pin) Ten pins--P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG2/SDA2, PG3/SCL2, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB --(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Note: When using this IIC module, make sure to set bits HNDS, FNC1, and FNC0 in ICXR to 1 in the initial settings. If other settings are made, restrictions on operation that are not covered in this manual will apply. Figure 18.1 shows a block diagram of the I2C bus interface. Figure 18.2 shows an example of I/O pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 28, Electrical Characteristics. Rev. 1.00 Apr. 28, 2008 Page 530 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 ICXR * SCL ExSCLA ExSCLB PS Clock control ICCR Noise canceler ICMR Bus state decision circuit Arbitration decision circuit ICDRT ICDRS ICDRR * SDA ExSDAA ExSDAB Output data control circuit Noise canceler [Legend] ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register ICXR: I2C bus extended control register SAR: Slave address register SARX: Slave address register X PS: Prescaler Address comparator SAR, SARX Interrupt generator Note : * An input/output pin can be selected among three pins (IIC_0 and IIC_1). Figure 18.1 Block Diagram of I2C Bus Interface Rev. 1.00 Apr. 28, 2008 Page 531 of 994 REJ09B0452-0100 Internal data bus Interrupt request ICSR Section 18 I C Bus Interface (IIC) 2 VDD VCC VCC SCL SCL in SCL out SDA SCL SDA SDA in SDA out (Master) This LSI SCL SDA SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 18.2 I2C Bus Interface Connections (Example: This LSI as Master) Rev. 1.00 Apr. 28, 2008 Page 532 of 994 REJ09B0452-0100 SCL SDA Section 18 I C Bus Interface (IIC) 2 18.2 Input/Output Pins Table 18.1 summarizes the input/output pins used by the I2C bus interface. One of three pins can be specified as SCL and SDA input/output pin for IIC_0 and IIC_1. Two or more input/output pins should not be specified for one channel. For the method of setting pins, see section 7.3.2, Port Control Register 1 (PTCNT1). Table 18.1 Pin Configuration Channel 0 Symbol* SCL0 SDA0 1 SCL1 SDA1 2 SCL2 SDA2 ExSCLA ExSDAA ExSCLB ExSDAB Note: * Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Function Serial clock input/output pin of IIC_0 Serial data input/output pin of IIC_0 Serial clock input/output pin of IIC_1 Serial data input/output pin of IIC_1 Serial clock input/output pin of IIC_2 Serial data input/output pin of IIC_2 Serial clock input/output pin of IIC_0 or IIC_1 Serial data input/output pin of IIC_0 or IIC_1 Serial clock input/output pin of IIC_0 or IIC_1 Serial data input/output pin of IIC_0 or IIC_1 In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 1.00 Apr. 28, 2008 Page 533 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR). Table 18.2 Register Configuration Channel Register Name 2 Initial Data Bus Abbreviation R/W Value Address Width ICXR_0 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 ICRES_0 ICXR_1 ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 R/W H'00 R/W H'01 R/W H'00 R/W R/W H'01 R/W H'00 R/W H'00 R/W H'0F R/W H'00 R/W H'01 R/W H'00 R/W R/W H'01 R/W H'00 R/W H'00 H'FED4 H'FFD8 H'FFD9 8 8 8 Channel 0 I2C bus extended control register_0 I C bus control register_0 I C bus status register_0 I C bus data register_0 Second slave address register_0 I C bus mode register_0 Slave address register_0 I2C bus control initialization register_0 Channel 1 I2C bus extended control register_1 I C bus control register_1 I2C bus status register_1 I2C bus data register_1 Second slave address register_1 I2C bus mode register_1 Slave address register_1 2 2 2 2 H'FFDE 8 H'FFDE 8 H'FFDF H'FFDF H'FEE6 H'FED5 8 8 8 8 H'FF88 8 H'FED0* H'FF89 8 H'FED1* H'FF8E 8 H'FECE* H'FF8E 8 H'FECE* H'FF8F 8 H'FECF* H'FF8F 8 H'FECF* Rev. 1.00 Apr. 28, 2008 Page 534 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Channel Register Name I2C bus control register_2 I2C bus status register_2 I C bus data register_2 Second slave address register_2 I C bus mode register_2 Slave address register_2 I C bus control initialization register_2 2 2 2 Initial Data Bus Abbreviation R/W Value Address Width ICXR_2 ICCR_2 ICSR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 ICRES_2 R/W H'00 R/W H'01 R/W H'00 R/W R/W H'01 R/W H'00 R/W H'00 R/W H'0F H'FE8C H'FE88 H'FE89 H'FE8E H'FE8E H'FE8F H'FE8F H'FE8A 8 8 8 8 8 8 8 8 Channel 2 I2C bus extended control register_2 Note: * Upper address: when RELOCATE = 0 Lower address: when RELOCATE = 1 Rev. 1.00 Apr. 28, 2008 Page 535 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF. In master transmit mode with the I2C bus format, writing transmit data to ICDR should be performed after start condition detection. When the start condition is detected, previous write data is ignored. In slave transmit mode, writing should be performed after the slave addresses match and the TRS bit is automatically changed to 1. In transmit mode (TRS = 1), transmit data can be written to ICDRT when the ICDRE flag is 1. After the transmit data has been written to ICDRT, the ICDRE flag is cleared to 0. Then, when ICDRS becomes empty on completion of the previous transmission, the data are automatically transferred from ICDRT to ICDRS and the ICDRE flag is set to 1. As long as ICDRS contains data to be transmitted or data being transmitted, data written to ICDRT are retained there. In receive mode (TRS = 0), data is not transferred from ICDRT to ICDRS. Thus, do not write to ICDRT when in this mode. In receive mode (TRS = 0), data received in ICDRR can be read when the ICDRF flag is 1. After the data has been read from ICDRR, the ICDRF flag is cleared to 0. Each time ICDRS contains data on completion of one round of reception, the data is automatically transferred from ICDRS to ICDRR and the ICDRF flag is set to 1. If ICDRR contains receive data that hasn't been read out, any further receive data is retained in ICDRS. Since data are not transferred from ICDRS to ICDRR in transmit mode (TRS = 1), do not read ICDRR in transmit mode (excluding the case where final receive data is read out in the recommended operation flow of master receive mode). If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1. ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value of ICDR is undefined. Rev. 1.00 Apr. 28, 2008 Page 536 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Format Select Selects the communication format together with the FSX bit in SARX. See table 18.3. This bit should be set to 0 when general call address recognition is performed. Description Slave Address 6 to 0 Set a slave address. Rev. 1.00 Apr. 28, 2008 Page 537 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX Initial Value 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Format Select X Selects the communication format together with the FS bit in SAR. See table 18.3. Description Second Slave Address 6 to 0 Set the second slave address. Rev. 1.00 Apr. 28, 2008 Page 538 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Table 18.3 Communication Format SAR FS 0 SARX FSX 0 Operating Mode I2C bus format * * 1 2 SAR and SARX slave addresses recognized General call address recognized SAR slave address recognized SARX slave address ignored General call address recognized SAR slave address ignored SARX slave address recognized General call address ignored I C bus format * * * 1 0 I C bus format * * * 2 1 Clocked synchronous serial format * * SAR and SARX slave addresses ignored General call address ignored * I2C bus format: addressing format with an acknowledge bit * Clocked synchronous serial format: non-addressing format without an acknowledge bit, for master mode only Rev. 1.00 Apr. 28, 2008 Page 539 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8 clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, see section 18.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX2 (IIC_2), IICX1 (IIC_1), and IICX0 (IIC_0) bits in STCR. See table 18.4. th 2 2 Rev. 1.00 Apr. 28, 2008 Page 540 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected. The value returns to B'000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 1.00 Apr. 28, 2008 Page 541 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Table 18.4 I2C Transfer Rate STCR Bits 5, 6, and 7 Bit 5 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICMR Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz 571 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz Notes: n = 0, 1, or 2 * Correct operation cannot be guaranteed since the transfer rate is beyond the I2C bus interface specification (normal mode: maximum 100 kHz, high-speed mode: maximum 400 kHz). Rev. 1.00 Apr. 28, 2008 Page 542 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.5 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation. Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I2C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 5 4 MST TRS 0 0 R/W R/W Master/Slave Select Transmit/Receive Select MST TRS 0 0 1 1 0: 1: 0: 1: Slave receive mode Slave transmit mode Master receive mode Master transmit mode 2 2 2 2 2 Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode with the I C 2 bus format. In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer (at the rising edge of the 9th clock). Rev. 1.00 Apr. 28, 2008 Page 543 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 5 4 Bit Name MST TRS Initial Value 0 0 R/W R/W R/W Description [MST clearing conditions] 1. When 0 is written by software 2. When lost in bus contention in I2C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3. When lost in bus contention in I2C bus format master mode [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing condition 3) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing condition 3) 3. When 1 is received as the R/W bit after the first frame address matching in I2C bus format slave mode 3 ACKE 0 R/W Acknowledge Bit Decision and Selection 0: The value of the acknowledge bit is ignored, and continuous transfer is performed. The value of the received acknowledge bit is not indicated by the ACKB bit in ICSR, which is always 0. 1: If the received acknowledge bit is 1, continuous transfer is halted. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Rev. 1.00 Apr. 28, 2008 Page 544 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 2 0 Bit Name BBSY SCP Initial Value 0 1 R/W R/W* W Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled. In slave mode: * [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 0 is written, the data is not stored. Note: * The value in BBSY flag does not change even if written. 2 2 Rev. 1.00 Apr. 28, 2008 Page 545 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 1 Bit Name IRIC Initial Value 0 R/W Description 2 R/(W)* I2C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 18.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] All operating modes: 1. When a start condition is detected in transmit mode and the ICDRE flag is set to 1 2. When data is transferred from ICDRT to ICDRS in transmit mode and the ICDRE flag is set to 1 3. When data is transferred from ICDRS to ICDRR in receive mode and the ICDRF flag is set to 1 4. If 1 is received as the acknowledge bit (when the ACKE bit is 1 in transmit mode) at the completion of data transmission I C bus format master mode: 1. When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 2. When the AL flag is set to 1 after bus arbitration is lost while the ALIE bit is 1 I C bus format slave mode: 1. When the slave address (SVA or SVAX) matches after the reception of the first frame following the start condition and the AAS flag or AASX flag is set to 1 2. When the general call address is detected after the reception of the first frame following the start condition and the ADZ flag is set to 1 (the FS bit in SAR is 0) 3. When a stop condition is detected (when the STOP or ESTP flag is set to 1) while the STOPIM bit is 0 2 2 Rev. 1.00 Apr. 28, 2008 Page 546 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 1 Bit Name IRIC Initial Value 0 R/W Description R/(W)* Note: When the slave address does not match and the general call address is not detected (with all flags of AAS, AASX, and ADZ cleared to 0), transmission and reception do not proceed. Thus, the ICDRE and ICDRF flags will not be set. Nor will the IRIC flag. However, even in this case, if STOPIM is 0, the IRIC flag is set by condition 3 above. If detection of a stop condition is not necessary, set STOPIM to 1 to disable setting of the IRIC flag. [Clearing condition] * When 0 is written in IRIC after reading IRIC = 1 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 547 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call address match in I2C bus format slave mode. Tables 18.5 and 18.6 show the relationship between the flags and the transfer states. Table 18.5 Flags and Transfer States (Master Mode) MST 1 1 1 1 1 1 1 1 TRS 1 1 -- 1 1 1 1 1 BBSY ESTP STOP IRTR 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- -- 1 -- -- -- AASX AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAS 0 0 0 0 0 0 0 0 ADZ 0 0 0 0 0 0 0 0 ACKB ICDRF ICDRE State 0 0 -- 1 0 0 0 0 -- -- -- -- -- -- -- -- 0 1 -- -- 1 0 1 0 Idle state (flag clearing required) Start condition detected Wait state Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state or after start condition detected Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state 1 1 1 0 0 1 0 0 0 0 0 -- 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 -- -- -- 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- 1 0 1 0 1 -- -- -- -- -- Rev. 1.00 Apr. 28, 2008 Page 548 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) MST 0 1 TRS 0 -- BBSY ESTP STOP IRTR 1 0 0 0 0 0 -- -- AASX AL 0 0 1 0 AAS 0 0 ADZ 0 0 ACKB ICDRF ICDRE State -- -- -- -- -- 0 Arbitration lost Stop condition detected 2 [Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained Cleared to 0 0: Set to 1 1: Rev. 1.00 Apr. 28, 2008 Page 549 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Table 18.6 Flags and Transfer States (Slave Mode) MST 0 0 0 0 0 0 0 0 0 0 0 TRS 0 0 1/0 *1 0 1/0 *1 1 1 1 1 1 1 BBSY ESTP STOP IRTR AASX AL 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -- 1/0 *2 -- -- -- 1/0 *2 1/0 *2 -- -- -- 1/0 *2 -- 0 0 0 0 1 -- -- -- -- -- -- 0 0 -- -- -- -- -- 0 -- 0 0 AAS 0 0 1 1 0 -- -- 0 -- 0 0 ADZ 0 0 0 1 0 0 0 0 1 0 0 ACKB ICDRF ICDRE State 0 0 0 0 0 1 0 0 0 0 0 -- -- 1 1 1 -- -- -- 0 1 1 1 1 -- 1 0 1 0 1 Idle state (flag clearing required) Start condition detected SAR match in first frame (SARXSAR) General call address match in first frame (SARXH'00) SAR match in first frame (SARSARX) Transmission end (ACKE=1 and ACKB=1) Transmission end with ICDRE=0 ICDR write with the above state Transmission end with ICDRE=1 ICDR write with the above state Automatic data transfer from ICDRT to ICDRS with the above state Reception end with ICDRF=0 ICDR read with the above state Reception end with ICDRF=1 ICDR read with the above state Automatic data transfer from ICDRS to ICDRR with the above state Stop condition detected 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- 0 -- 0 0 -- 0 -- 0 0 -- 0 -- 0 0 -- -- -- -- -- 1 0 1 0 1 -- -- -- -- -- 0 -- 0 1/0 *3 0/1 *3 -- -- -- -- -- -- 0 [Legend] 0: 0-state retained 1: 1-state retained --: Previous state retained 0: Cleared to 0 1: Set to 1 Notes: 1. Set to 1 when 1 is received as a R/W bit following an address. 2. Set to 1 when the AASX bit is set to 1. 3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0. Rev. 1.00 Apr. 28, 2008 Page 550 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 18.5 and 18.6. Bit 7 Bit Name ESTP Initial Value 0 R/W Description 6 STOP 0 5 IRTR 0 R/(W)* Error Stop Condition Detection Flag This bit is valid in I2C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * When 0 is written in ESTP after reading ESTP = 1 * When the IRIC flag in ICCR is cleared to 0 R/(W)* Normal Stop Condition Detection Flag 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] * When 0 is written in STOP after reading STOP = 1 * When the IRIC flag is cleared to 0 R/(W)* I2C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. [Setting conditions] I2C bus format slave mode: * When the ICDRE or ICDRF flag in ICDR is set to 1 when AASX = 1 Master mode or clocked synchronous serial format 2 mode with I C bus format: * When the ICDRE or ICDRF flag is set to 1 [Clearing conditions] * When 0 is written after reading IRTR = 1 * When the IRIC flag is cleared to 0 while ICE is 1 Rev. 1.00 Apr. 28, 2008 Page 551 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 4 Bit Name AASX Initial Value 0 R/W Description 2 R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] When the second slave address is detected in slave receive mode and FSX = 0 in SARX [Clearing conditions] * * * When 0 is written in AASX after reading AASX = 1 When a start condition is detected In master mode 3 AL 0 R/(W)* Arbitration Lost Flag Indicates that arbitration was lost in master mode. [Setting conditions] When ALSL=0 * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master mode If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the SDA pin is driven low by another device 2 before the I C bus interface drives the SDA pin low, after the start condition instruction was executed in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1 When ALSL=1 * * [Clearing conditions] * * Rev. 1.00 Apr. 28, 2008 Page 552 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 2 Bit Name AAS Initial Value 0 R/W Description 2 R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode 2 1 ADZ 0 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). [Setting condition] When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 or FSX = 0 [Clearing conditions] * * * When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1 In master mode If a general call address is detected while FS=1 and FSX=0, the ADZ flag is set to 1; however, the general call address is not recognized (AAS flag is not set to 1). Rev. 1.00 Apr. 28, 2008 Page 553 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 0 Bit Name ACKB Initial Value 0 R/W R/W Description Acknowledge Bit Stores acknowledge data. The bit function varies depending on transmit mode and receive mode. Transmit mode: Holds the acknowledge data returned by the receiving device. [Setting condition] When 1 is received as the acknowledge bit when ACKE = 1 in transmit mode [Clearing conditions] * When 0 is received as the acknowledge bit when ACKE = 1 in transmit mode * When 0 is written to the ACKE bit Receive mode: Sets the acknowledge data to be returned to the transmitting device. 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. Note: When, in transmit mode, this bit has been overwritten by a bit manipulation instruction with a value other than that of the ACKB flag in ICSR, the value of the ACKB bit as the acknowledge data setting for receive mode is overwritten by this value. Thus, always reset the acknowledge data when switching to receive mode. Write 0 to the ACKE bit to clear the ACKB flag to 0 in the following cases: in master mode--before transmission is ended and a stop condition is generated; and in slave mode--before transmission is ended and SDA is released to allow a master device to issue a stop condition. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 554 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.7 I2C Bus Control Initialization Register (ICRES) ICRES controls IIC internal latch clearance. Bit 7 to 5 4 3 2 1 0 Bit Name -- -- CLR3 CLR2 CLR1 CLR0 Initial Value All 0 0 1 1 1 1 R/W R/W R W* W* W* W* Description Reserved The initial value should not be changed. Reserved IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. (ICRES_0) 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting Controls initialization of the internal state of IIC_2. (ICRES_2) 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_2 internal latch cleared 0110: Setting prohibited 0111: IIC_2 internal latch cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. Note: * This bit is always read as 1. Rev. 1.00 Apr. 28, 2008 Page 555 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.3.8 I2C Bus Extended Control Register (ICXR) ICXR enables or disables the I2C bus interface interrupt generation and handshake control, and indicates the status of receive/transmit operations. Bit 7 Bit Name STOPIM Initial Value 0 R/W R/W Description Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode. 0: Enables IRIC flag setting and interrupt generation when the stop condition is detected (STOP = 1 or ESTP = 1) in slave mode. 1: Disables IRIC flag setting and interrupt generation when the stop condition is detected. 6 HNDS 0 R/W Enables or disables handshake control in receive mode for the selection of reception with handshaking. 0: Disables handshake control 1: Enables handshake control Note: When the IIC module is in use, be sure to set this bit to 1. When the HNDS bit is cleared to 0 and a round of reception is completed with ICDRR empty (the ICDRF flag is 0), successive reception will proceed with the next round of reception. At the same time, a clock is continuously supplied over the SCL line. In this case, the sequence of operations should be such that unnecessary clock cycles are not output to the bus after reception of the last of the data. When the HNDS bit is set to 1, SCL is fixed low and clock output stops on completion of reception. SCL is released and reception of the next frame is enabled by reading the receive data from ICDR. Rev. 1.00 Apr. 28, 2008 Page 556 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 5 Bit Name ICDRF Initial Value 0 R/W R Description Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] * When data is received successfully and transferred from ICDRS to ICDRR. (1) When data is received successfully while ICDRF = 0 (at the rise of the 9th clock pulse). (2) When ICDR is read successfully in receive mode after data was received while ICDRF = 1. [Clearing conditions] * * * When ICDR (ICDRR) is read. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. When ICDRF is set due to the condition (2) above, ICDRF is temporarily cleared to 0 when ICDR (ICDRR) is read; however, since data is transferred from ICDRS to ICDRR immediately, ICDRF is set to 1 again. Note that ICDR cannot be read successfully in transmit mode (TRS = 1) because data is not transferred from ICDRS to ICDRR. Be sure to read data from ICDR in receive mode (TRS = 0). Rev. 1.00 Apr. 28, 2008 Page 557 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 4 Bit Name ICDRE Initial Value 0 R/W R Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to. [Setting conditions] * * When the start condition is detected from the bus 2 line state with I C bus format or serial format. When data is transferred from ICDRT to ICDRS. 1. When data transmission completed while ICDRE = 0 (at the rise of the 9th clock pulse). 2. When data is written to ICDR in transmit mode after data transmission was completed while ICDRE = 1. [Clearing conditions] * * * * When data is written to ICDR (ICDRT). When the stop condition is detected with I C bus format or serial format. When 0 is written to the ICE bit. When the IIC is internally initialized using the CLR3 to CLR0 bits in DDCSWR. 2 2 Note that if the ACKE bit is set to 1 with I C bus format thus enabling acknowledge bit decision, ICDRE is not set when data transmission is completed while the acknowledge bit is 1. When ICDRE is set due to the condition (2) above, ICDRE is temporarily cleared to 0 when data is written to ICDR (ICDRT); however, since data is transferred from ICDRT to ICDRS immediately, ICDRE is set to 1 again. Do not write data to ICDR when TRS = 0 because the ICDRE flag value is invalid during the time. Rev. 1.00 Apr. 28, 2008 Page 558 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Bit 3 Bit Name ALIE Initial Value 0 R/W R/W Description Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost. 0: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SCL pin is driven low by another device. 1: When the SDA pin state disagrees with the data that IIC bus interface outputs at the rise of SCL, or when the SDA line is driven low by another device in idle state or after the start condition instruction was executed. 1 0 FNC1 FNC0 0 0 R/W R/W Function 1, 0 These bits cancel some restrictions on usage. FNC0 FNC1 0 0 1 1 0: Restrictions on operation canceled 1: Setting prohibited 0: Setting prohibited 1: Restrictions on operation remaining in effect Note: When the IIC module is used, make sure to set both of the bits to 1. Rev. 1.00 Apr. 28, 2008 Page 559 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4 Operation The I2C bus interface has an I2C bus format and a serial format. 18.4.1 I2C Bus Data Format The I2C bus format is an addressing format with an acknowledge bit. This is shown in figure 18.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 18.4. Figure 18.5 shows the I2C bus timing. The symbols used in figures 18.3 to 18.5 are explained in table 18.7. (a) FS = 0 or FSX = 0 S 1 SLA 7 1 (b) Start condition retransmission FS = 0 or FSX = 0 S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Upper row: Transfer bit count (n1, n2 = 1 to 8) Lower row: Transfer frame count (m1, m2 = from 1) Figure 18.3 I2C Bus Data Format (I2C Bus Format) FS=1 and FSX=1 S 1 DATA 8 1 DATA n m P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1) Figure 18.4 I2C Bus Data Format (Serial Format) Rev. 1.00 Apr. 28, 2008 Page 560 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 SDA SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 18.5 I2C Bus Timing Table 18.7 I2C Bus Data Format Symbols Legend S SLA R/W A Start condition. The master device drives SDA from high to low while SCL is high Slave address. The master device selects the slave device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The slave device returns acknowledge in master transmit mode, and the master device returns acknowledge in master receive mode.) Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR. Stop condition. The master device drives SDA from low to high while SCL is high DATA P Rev. 1.00 Apr. 28, 2008 Page 561 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.2 Initialization Initialize the IIC by the procedure shown in figure 18.6 before starting transmission/reception of data. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) MSTPB4 = 0 (IIC_2) (MSTPCRL, MSTPCRB) Set IICE = 1 in STCR Set ICE = 0 in ICCR Set SAR and SARX Set ICE = 1 in ICCR Set ICSR Set STCR Set ICMR Cancel module stop mode Enable the CPU accessing to the IIC control register and data register Enable SAR and SARX to be accessed Set the first and second slave addresses and IIC communication format (SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX) Enable ICMR and ICDR to be accessed Use SCL/SDA pin as an IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set communication format, wait insertion, and transfer rate (MLS, WAIT, CKS2 to CKS0) Enable interrupt, set communication operation (STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0) Be sure to set as follows: HNDS = 1, FNC1 = 1, and FNC0 = 1. Set interrupt enable, transfer mode, and acknowledge decision (IEIC, MST, TRS, and ACKE) Set ICXR Set ICCR << Start transmit/receive operation >> Figure 18.6 Sample Flowchart for IIC Initialization Note: Be sure to modify the ICMR register after transmit/receive operation has been completed. If the ICMR register is modified during transmit/receive operation, bit counter BC2 to BC0 will be modified erroneously, thus causing incorrect operation. 18.4.3 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 18.7 shows the sample flowchart for the operations in master transmit mode. Rev. 1.00 Apr. 28, 2008 Page 562 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Start Initialize IIC Read BBSY flag in ICCR No [2] Test the status of the SCL and SDA lines. BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Set BBSY =1 and SCP = 0 in ICCR Read IRIC flag in ICCR No [5] Wait for a start condition generation IRIC = 1? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data in ICDR Clear IRIC flag in ICCR Read IRIC flag in ICCR [10] Wait for 1 byte to be transmitted. No IRIC = 1? Yes Read ACKB bit in ICSR [11] Determine end of tranfer No End of transmission? (ACKB = 1?) [1] Initialization [3] Select master transmit mode. [4] Start condition issuance [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.) [7] Wait for 1 byte to be transmitted. No [8] Test the acknowledge bit transferred from the slave device. No Master receive mode [9] Set transmit data for the second and subsequent bytes. (After writing to ICDR, clear IRIC flag continuously.) Yes Clear IRIC flag in ICCR Set BBSY = 0 and SCP = 0 in ICCR End [12] Stop condition issuance Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode Rev. 1.00 Apr. 28, 2008 Page 563 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 The master mode transmission procedure and operations are described below. 1. 2. 3. 4. Initialize the IIC as described in section 18.4.2, Initialization. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TRS to 1 in ICCR to select master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear IRIC continuously so no other interrupt handling routine is executed. If the time for transmission of one frame of data has passed before the IRIC clearing, the end of transmission cannot be determined. The master device sequentially sends the transmission clock and the data written to ICDR. The selected slave device (i.e. the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the transmit operation. 9. Write the transmit data to ICDR. As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is performed in synchronization with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data to be transmitted, go to step [9] to continue the next transmission operation. When the slave device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission. Rev. 1.00 Apr. 28, 2008 Page 564 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Start condition generation SCL (master output) SDA (master output) SDA (slave output) ICDRE 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 IRIC Interrupt request Interrupt request IRTR ICDRT Address + R/W Data 1 ICDRS Address + R/W Data 1 Note:* Data write in ICDR prohibited User processing [4] BBSY set to 1 [6] ICDR write SCP cleared to 0 (start condition issuance) [6] IRIC clear [9] ICDR write [9] IRIC clear Figure 18.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 1.00 Apr. 28, 2008 Page 565 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Stop condition issuance SCL (master output) 8 9 1 Bit 7 [7] A 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [10] A 9 SDA Bit 0 (master output) Data 1 SDA (slave output) ICDRE IRIC IRTR ICDR Data 2 Data 1 Data 2 User processing [9] ICDR write [9] IRIC clear [11] ACKB read [12] IRIC clear [12] Set BBSY= 0 and SCP= 0 (Stop condition issuance) Figure 18.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 1.00 Apr. 28, 2008 Page 566 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Figure 18.10 shows the sample flowchart for the operations in master receive mode. Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Clear IRIC flag in ICCR [1] Select receive mode. Last receive? No Read ICDR Yes [2] Start receiving. The first read is a dummy read. [5] Read the receive data (for the second and subsequent read) Read IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR [3] Wait for 1 byte to be received. (Set IRIC at the rise of the 9th clock for the receive frame) [4] Clear IRIC flag. Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? [6] Set acknowledge data for the last reception. [7] Read the receive data. Dummy read to start receiving if the first frame is the last receive data. [8] Wait for 1 byte to be received. Yes Clear IRIC flag in ICCR Set TRS = 1 in ICCR Read ICDR Set BBSY = 0 and SCP = 0 in ICCR End [9] Clear IRIC flag. [10] Read the receive data. [11] Set stop condition issuance. Generate stop condition. Figure 18.10 Sample Flowchart for Operations in Master Receive Mode Rev. 1.00 Apr. 28, 2008 Page 567 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 The master mode reception procedure and operations are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data. 2. When ICDR is read (dummy data read), reception is started, the receive clock is output in synchronization with the internal clock, and data is received. (Data from the SDA pin is sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.) 3. The master device drives SDA low to return the acknowledge data at the 9th receive clock pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse, setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data reading. 4. Clear the IRIC flag to determine the next interrupt. Go to step [6] to halt reception operation if the next frame is the last receive data. 5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock continuously to receive the next data. Data can be received continuously by repeating steps [3] to [5]. 6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception. 7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the receive clock to receive data. 8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the rise of the 9th receive clock pulse. 9. Clear the IRIC flag to 0. 10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0. 11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Rev. 1.00 Apr. 28, 2008 Page 568 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Master transmit mode Master receive mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR 9 A 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Data 1 Data 2 Undefined value Data 1 User processing [1] TRS=0 clear [1] IRIC clear [2] ICDR read (Dummy read) [4] IRIC clear [5] ICDR read (Data 1) Figure 18.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0) SCL is fixed low until stop condition is issued 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 [8] A 9 SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) SDA (master output) IRIC IRTR ICDRF ICDRR Data 1 Data 2 7 Bit 1 8 Bit 0 [3] A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 Stop condition generation Data 2 Data 3 Data 3 [10] ICDR read (Data 3) [11] Set BBSY=0 and SCP=0 (Stop condition instruction issuance) User processing [4] IRIC clear [7] ICDR read (Data 2) [6] Set ACKB = 1 [9] IRIC clear Figure 18.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0) Rev. 1.00 Apr. 28, 2008 Page 569 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.5 Slave Receive Operation In I2C bus format slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device operates as the device specified by the master device when the slave address in the first frame following the start condition that is issued by the master device matches its own address. Figure 18.13 shows the sample flowchart for the operations in slave receive mode. Rev. 1.00 Apr. 28, 2008 Page 570 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Clear IRIC flag in ICCR ICDRF = 1? No [2] Read the receive data remaining unread. [1] Initialization. Select slave receive mode. Yes Read ICDR, clear IRIC flag Clear IRIC flag in ICCR No IRIC = 1? Yes Clear IRIC flag in ICCR Read AASX, AAS and ADZ in ICSR AAS = 1 and ADZ = 1? No Read TRS in ICCR TRS = 1? No Yes Last reception? No Read ICDR Read IRIC flag in ICCR No IRIC = 1? [8] Clear IRIC flag. [10] Read the receive data. The first read is a dummy read. [5] to [7] Wait for the reception to end. Yes Slave transmit mode Yes General call address processing * Description omitted [8] Clear IRIC flag [3] to [7] Wait for one byte to be received (slave address + R/W) Yes Clear IRIC flag in ICCR Set ACKB = 1 in ICSR Read ICDR Read IRIC flag in ICCR No IRIC = 1? Yes ESTP = 1 or STOP = 1? Yes [9] Set acknowledge data for the last reception. [10] Read the receive data. [5] to [7] Wait for reception end. [11] Detect stop condition. [12] Check STOP bit. No Clear IRIC flag in ICCR [8] Clear IRIC flag. Clear IRIC flag in ICCR End [12] Clear IRIC flag. Figure 18.13 Sample Flowchart for Operations in Slave Receive Mode Rev. 1.00 Apr. 28, 2008 Page 571 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 The slave mode reception procedure and operations are described below. 1. Initialize the IIC as described in section 18.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. The master device then outputs the 7-bit slave address and transmit/receive direction (R/W), in synchronization with the transmit clock pulses. 4. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit (R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave address does not match, receive operation is halted until the next start condition is detected. 5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit as an acknowledge signal. 6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an interrupt request is sent to the CPU. If the AASX bit has been set to 1, IRTR flag is also set to 1. 7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR, setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive clock pulse until data is read from ICDR. 8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0. 9. If the next frame is the last receive frame, set the ACKB bit to 1. 10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the master device to transfer the next data. Receive operations can be performed continuously by repeating steps [5] to [10]. 11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to 0, the IRIC flag is set to 1. 12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0. Rev. 1.00 Apr. 28, 2008 Page 572 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) IRIC ICDRF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1 1 2 2 3 3 4 4 5 5 6 6 7 7 [7] SCL is fixed low until ICDR is read 8 8 9 9 1 1 2 2 Bit 2 Bit 1 Bit 0 R/W [6] A Interrupt request occurrence Bit 7 Bit 6 Data 1 Slave address ICDRS Address+R/W ICDRR Undefined value Address+R/W User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read) Figure 18.14 Example of Slave Receive Mode Operation Timing (1) (MLS = 0) Stop condition generation [7] SCL is fixed low until ICDR is read SCL (master output) SCL (slave output) SDA (master output) Data (n-1) SDA (slave output) IRIC Bit 0 [6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data (n) [6] [11] 8 9 1 2 3 4 5 [7] SCL is fixed low until ICDR is read 6 7 8 9 A A ICDRF ICDRS Data (n-1) Data (n) ICDRR Data (n-2) Data (n-1) Data (n) User processing [8] IRIC clear [5] ICDR read (Data (n-1)) [9] Set ACKB=1 [8] IRIC clear [10] ICDR read (Data (n)) [12] IRIC clear Figure 18.15 Example of Slave Receive Mode Operation Timing (2) (MLS = 0) Rev. 1.00 Apr. 28, 2008 Page 573 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 18.16 shows the sample flowchart for the operations in slave transmit mode. Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR No End of transmission (ACKB = 1)? Yes Clear IRIC in ICCR Clear ACKE to 0 in ICCR (ACKB=0 clear) Set TRS = 0 in ICCR Read ICDR Read IRIC in ICCR No IRIC = 1? Yes Clear IRIC in ICCR End [6] Clear IRIC in ICCR [7] Clear acknowledge bit data [8] Set slave receive mode. [9] Dummy read (to release the SCL line). [10] Wait for stop condition [4] Determine end of transfer. [1], [2] If the slave address matches to the address in the first frame following the start condition detection and the R/W bit is 1 in slave recieve mode, the mode changes to slave transmit mode. [3], [5] Set transmit data for the second and subsequent bytes. [3], [4] Wait for 1 byte to be transmitted. Figure 18.16 Sample Flowchart for Slave Transmit Mode Rev. 1.00 Apr. 28, 2008 Page 574 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit 9th clock until ICDR data is written, to disable the master device to output the next transfer clock. 3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to 0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again. The slave device sequentially sends the data written into ICDRS in accordance with the clock output by the master device. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR register writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. 4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS, transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has been set to 1, this slave device drives SCL low from the fall of the 9th transmit clock until data is written to ICDR. 5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR writing to the IRIC flag clearing should be performed continuously. Prevent any other interrupt processing from being inserted. Transmit operations can be performed continuously by repeating steps [4] and [5]. Rev. 1.00 Apr. 28, 2008 Page 575 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 6. Clear the IRIC flag to 0. 7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in the ACKB bit to 0. 8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode. 9. Dummy-read ICDR to release SCL on the slave side. 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0. Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 [2] Data 1 [4] Data 2 SDA (master output) R/W A IRIC ICDRE ICDR User processing [3] IRIC clear [3] ICDR write [3] IRIC clear Data 1 Data 2 [5] IRIC clear [5] ICDR write Figure 18.17 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 1.00 Apr. 28, 2008 Page 576 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 18.18 to 18.20 show the IRIC set timing and SCL control. When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 7 8 8 9 A 1 1 2 2 3 3 SDA IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. SCL 7 7 8 8 9 A 1 1 SDA IRIC User processing Clear IRIC Write to ICDR (transmit) Clear IRIC or read from ICDR (receive) (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception. Figure 18.18 IRIC Setting Timing and SCL Control (1) Rev. 1.00 Apr. 28, 2008 Page 577 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA IRIC User processing Clear IRIC Clear IRIC 8 8 9 A 1 1 2 2 3 3 (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. SCL 8 8 9 A 1 1 SDA IRIC User processing Clear IRIC Write to ICDR (transmit) Clear IRIC or read from ICDR (receive) (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception. Figure 18.19 IRIC Setting Timing and SCL Control (2) When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL 7 8 1 2 SDA IRIC User processing Clear IRIC 7 8 1 2 3 3 4 4 (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. SCL 7 8 1 SDA 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) Clear IRIC or read from ICDR (receive) (b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception. Figure 18.20 IRIC Setting Timing and SCL Control (3) Rev. 1.00 Apr. 28, 2008 Page 578 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.4.8 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 18.21 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock cycle Sampling clock Figure 18.21 Block Diagram of Noise Canceler 18.4.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in ICRES or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 18.3.7, I2C Bus Control Initialization Register (ICRES). (1) Scope of Initialization The initialization executed by this function covers the following items: * ICDRE and ICDRF internal flags * Transmit/receive sequencer and internal operating clock counter * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) Rev. 1.00 Apr. 28, 2008 Page 579 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE and ICDRF flags) * Internal latches used to retain register read information for setting/clearing flags in ICMR, ICCR, and ICSR * The value of the ICMR bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) Notes on Initialization * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is executed by ICRES, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. * Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY bit to 0, and wait for two transfer rate clock cycles. 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or ICE bit clearing. 4. Initialize (re-set) the IIC registers. Rev. 1.00 Apr. 28, 2008 Page 580 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.5 Interrupt Sources The IIC has interrupt source IICI. Table 18.8 shows the interrupt sources and priority. Individual interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the interrupt controller independently. The IIC interrupts are used as on-chip DTC activation sources. Table 18.8 IIC Interrupt Sources Channel 0 1 2 Name IICI0 IICI1 IICI2 Enable Bit IEIC IEIC IEIC Interrupt Source I C bus interface interrupt request I2C bus interface interrupt request I2C bus interface interrupt request 2 Interrupt Flag Priority IRIC IRIC IRIC Low High Rev. 1.00 Apr. 28, 2008 Page 581 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 18.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I2C bus, neither condition will be output correctly. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when accessing ICDR. Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 18.9 shows the timing of SCL and SDA outputs in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 18.9 I2C Bus Timing (SCL and SDA Outputs) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time Note: * tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28tcyc to 256tcyc 0.5tSCLO 0.5tSCLO 0.5tSCLO - 1tcyc 0.5tSCLO - 1tcyc 1tSCLO 0.5tSCLO + 2tcyc 1tSCLLO - 3tcyc 1tSCLL - (6tcyc or 12tcyc*) 3tcyc ns Unit ns ns ns ns ns ns ns ns Notes See figure 28.24 (for reference) 6tcyc when IICX is 0, 12tcyc when 1. Rev. 1.00 Apr. 28, 2008 Page 582 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 4. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 18.10. Table 18.10 Permissible SCL Rise Time (tsr) Values Time Indication [ns] I C Bus Specification = 8 MHz (Max.) Standard mode 1000 937 300 1000 300 2 IICX tcyc Indication 0 7.5 tcyc = 10 MHz 750 300 1000 300 = 16 MHz 468 300 1000 300 = 20 MHz 375 300 875 300 High-speed mode 300 1 17.5 tcyc Standard mode 1000 High-speed mode 300 5. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in table 18.11. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 18.11 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 1.00 Apr. 28, 2008 Page 583 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Table 18.11 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I C Bus tSr/tSf Influence Specification (Max.) (Min.) Standard mode -1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) = 8 MHz 4000 950 4750 1000* 3875* 825* 1 1 = 10 MHz 4000 950 4750 1000* 3900* 850* 1 1 = 16 MHz 4000 950 4750 1000* 3939* 888* 1 1 = 20 MHz 4000 950 4750 1000* 3950* 900* 1 1 High-speed mode -300 tSCLLO 0.5 tSCLO (-tSf) Standard mode -250 High-speed mode -250 tBUFO 0.5 tSCLO -1 tcyc (-tSr) 0.5 tSCLO -1 tcyc (-tSf) 1 tSCLO (-tSr) Standard mode -1000 1 1 1 1 High-speed mode -300 Standard mode -250 tSTAHO 4625 875 9000 2200 4250 1200 3325 625 2200 4650 900 9000 2200 4200 1150 3400 700 2500 4688 938 9000 2200 4125 1075 3513 813 2950 4700 900 9000 2200 4100 1050 3550 850 3100 High-speed mode -250 Standard mode -1000 tSTASO High-speed mode -300 tSTOSO 0.5 tSCLO + 2 tcyc Standard mode -1000 (-tSr) High-speed mode -300 1 tSCLLO* -3 tcyc Standard mode 3 tSDASO -1000 (master) (-tSr) High-speed mode -300 3 tSDASO 1 tSCLL* (slave) 2 -12 tcyc* (-tSr) tSDAHO 3 tcyc Standard mode -1000 High-speed mode -300 Standard mode 0 100 0 0 -500* 375 375 1 -200* 300 300 1 250 188 188 400 150 150 High-speed mode 0 2 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6 tcyc). 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). Rev. 1.00 Apr. 28, 2008 Page 584 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 6. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 7. Note on ACKE and TRS bits in slave mode In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match. Similarly, if the start condition or address is transmitted from the master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt source even when the address does not match. To use the I2C bus interface module in slave mode, be sure to follow the procedures below. A. When having received 1 as the acknowledge bit value for the last transmit data at the end of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB bit to 0. B. Set receive mode (TRS = 0) before the next start condition is input in slave mode. Complete transmit operation by the procedure shown in figure 18.16, in order to switch from slave transmit mode to slave receive mode. 18.6.1 Module Stop Mode Setting The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, see section 26, Power-Down Modes. Rev. 1.00 Apr. 28, 2008 Page 585 of 994 REJ09B0452-0100 Section 18 I C Bus Interface (IIC) 2 Rev. 1.00 Apr. 28, 2008 Page 586 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Section 19 Keyboard Buffer Control Unit (PS2) This LSI has four on-chip keyboard buffer control unit (PS2) channels. The PS2 is provided with functions conforming to the PS/2 interface specifications. Data transfer using the PS2 employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 19.1 shows a block diagram of the PS2. 19.1 Features * Conforms to PS/2 interface specifications * Direct bus drive (via the KCLK and KD pins) * Interrupt sources: on completion of data reception/transmission, on detection of clock falling edge, and on detection of the first falling edge of a clock * Error detection: parity error, stop bit monitoring, and receive notify monitoring Rev. 1.00 Apr. 28, 2008 Page 587 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) KBBR KBTR KD (PS2AD, PS2BD, PS2CD, PS2DD) KCLK (PS2AC, PS2BC, PS2CC, PS2DC) Transmission start KDI Control logic KCLKI Parity Transmit counter nalue KDO KCLKO KBCRL KBCRH KBCR1 Module data bus Bus interface Internal data bus KBCR2 Register counter value KBI interrupt KCI interrupt KTI interrupt [Legend] KD: KCLK: KBBR: KBCRH: KBCRL: PS2 data I/O pin PS2 clock I/O pin Keyboard data buffer register Keyboard control register H Keyboard control register L KBTR: KBCR1: KBCR2: Keyboard buffer transmit data register Keyboard control register 1 Keyboard control register 2 Figure 19.1 Block Diagram of PS2 Rev. 1.00 Apr. 28, 2008 Page 588 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Figure 19.2 shows how the PS2 is connected. Vcc Vcc System side KCLK in Clock KCLK out Keyboard side KCLK in KCLK out KD in KD out Data KD in KD out Keyboard buffer control unit (This LSI) I/F Figure 19.2 PS2 Connection 19.2 Input/Output Pins Table 19.1 lists the input/output pins used by the keyboard buffer control unit. Table 19.1 Pin Configuration Channel 0 Name PS2 clock I/O pin (KCLK0) PS2 data I/O pin (KD0) 1 PS2 clock I/O pin (KCLK1) PS2 data I/O pin (KD1) 2 PS2 clock I/O pin (KCLK2) PS2 data I/O pin (KD2) 3 PS2 clock I/O pin (KCLK3) PS2 data I/O pin (KD3) Note: * Abbreviation* PS2AC PS2AD PS2BC PS2BD PS2CC PS2CD PS2DC PS2DD I/O I/O I/O I/O I/O I/O I/O I/O I/O Function PS2 clock input/output PS2 data input/output PS2 clock input/output PS2 data input/output PS2 clock input/output PS2 data input/output PS2 clock input/output PS2 data input/output These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK and data I/O pins as KD, omitting the channel designations. Rev. 1.00 Apr. 28, 2008 Page 589 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3 Register Descriptions The PS2 has the following registers for each channel. Table 19.2 Register Configuration Channel Channel 0 Register Name Keyboard control register 1_0 Keyboard control register 2_0 Keyboard buffer transmit data register_0 Keyboard control register H_0 Keyboard control register L_0 Abbreviation KBCR1_0 KBCR2_0 KBTR_0 KBCRH_0 KBCRL_0 R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R Initial Data Bus Value Address Width H'00 H'F0 H'FF H'70 H'70 H'00 H'00 H'F0 H'FF H'70 H'70 H'00 H'00 H'F0 H'FF H'70 H'70 H'00 H'00 H'F0 H'FF H'70 H'70 H'00 H'FEC0 8 H'FEDB 8 H'FEC1 H'FED8 H'FED9 8 8 8 Keyboard data buffer register_0 KBBR_0 Channel 1 Keyboard control register 1_1 Keyboard control register 2_1 Keyboard buffer transmit data register_1 Keyboard control register H_1 Keyboard control register L_1 KBCR1_1 KBCR2_1 KBTR_1 KBCRH_1 KBCRL_1 H'FEDA 8 H'FEC2 8 H'FEDF 8 H'FEC3 8 H'FEDC 8 H'FEDD 8 H'FEDE 8 H'FEC4 H'FEE3 H'FEC5 H'FEE0 H'FEE1 H'FEE2 H'FED2 H'FFE3 H'FED3 H'FFE0 H'FFE1 H'FFE2 8 8 8 8 8 8 8 8 8 8 8 8 Keyboard data buffer register_1 KBBR_1 Channel 2 Keyboard control register 1_2 Keyboard control register 2_2 Keyboard buffer transmit data register_2 Keyboard control register H_2 Keyboard control register L_2 KBCR1_2 KBCR2_2 KBTR_2 KBCRH_2 KBCRL_2 Keyboard data buffer register_2 KBBR_2 Channel 3 Keyboard control register 1_3 Keyboard control register 2_3 Keyboard buffer transmit data register_3 Keyboard control register H_3 Keyboard control register L_3 KBCR1_3 KBCR2_3 KBTR_3 KBCRH_3 KBCRL_3 Keyboard data buffer register_3 KBBR_3 Rev. 1.00 Apr. 28, 2008 Page 590 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3.1 Keyboard Control Register 1 (KBCR1) KBCR1 controls data transmission and interrupt, selects parity, and detects transmit error. Bit 7 Bit Name KBTS Initial Value 0 R/W R/W Description Transmit Start Selects start of data transmission or disables transmission. 0: Data transmission is disabled [Clearing conditions] * * * When 0 is written When the KBTE is set to 1 When the KBIOE is cleared to 0 1: Starts data transmission [Setting condition] When 1 is written after reading the KBTS = 0 6 PS 0 R/W Transmit Parity Selection Selects even or odd parity. 0: Selects odd parity 1: Selects even parity 5 KCIE 0 R/W First KCLK Falling Interrupt Enable Selects whether an interrupt at the first falling edge of KCLK is enabled or disabled. 0: Disables first KCLK falling interrupt 1: Enables first KCLK falling interrupt 4 KTIE 0 R/W Transmit Completion Interrupt Enable Selects whether a transmit completion interrupt is enabled or disabled. 0: Disables transmit completion interrupt 1: Enables transmit completion interrupt 3 0 Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 591 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Bit 2 Bit Name KCIF Initial Value 0 R/W Description Indicates that the first falling edge of KCLK is detected. When KCIE and KCIF are set to 1, requests the CPU an interrupt. 0: [Clearing condition] After reading KCIF = 1, 0 is written 1: [Setting condition] When the first falling edge of KCLK is detected Note that this flag cannot be set when software standby mode or watch mode is cancelled. (However, internal flag is set.) R/(W)* First KCLK Falling Interrupt Flag 1 KBTE 0 R/(W)* Transmit Completion Flag Indicates that data transmission is completed. When KTIE and KBTE are set to 1, requests the CPU an interrupt. 0: [Clearing condition] After reading KBTE = 1, 0 is written 1: [Setting Condition] When all KBTR data has been transmitted (Set at the eleventh rising edge of the KCLK signal) 0 KTER 0 R Transmit Error Stores a notification of receive completion. Valid only when KBTE = 1. 0: 0 received as a notification of receive completion. 1: 1 received as a notification of receive completion. Note: * Only 0 can be written for clearing the flag. Rev. 1.00 Apr. 28, 2008 Page 592 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3.2 Keyboard Buffer Control Register 2 (KBCR2) KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK. Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD (LSB-first). Bit 7 to 4 Bit Name Initial Value All 1 R/W R/W Description Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 TXCR3 TXCR2 TXCR1 TXCR0 0 0 0 0 R R R R Transmit Counter Indicates bit of transmit data. Counter is incremented at the falling edge of KCLK. The transmit counter is initialized by a reset, when the KBTS is cleared to 0, the KBIOE is cleared to 0, or the KBTE is set to 1. 0000: Clear 0001: KBT0 0010: KBT1 0011: KBT2 0100: KBT3 0101: KBT4 0110: KBT5 0111: KBT6 1000: KBT7 1001: Parity bit 1010: Stop bit 1011: Transmit completion notification Rev. 1.00 Apr. 28, 2008 Page 593 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3.3 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer control unit. Bit 7 Bit Name KBIOE Initial Value 0 R/W R/W Description Keyboard In/Out Enable Selects whether or not the keyboard buffer control unit is used. 0: The keyboard buffer control unit is non-operational (KCLK and KD signal pins have port functions) 1: The keyboard buffer control unit is enabled for transmission and reception (KCLK and KD signal pins are in the bus drive state) 6 KCLKI 1 R Keyboard Clock In Monitors the KCLK I/O pin. This bit cannot be modified. 0: KCLK I/O pin is low 1: KCLK I/O pin is high 5 KDI 1 R Keyboard Data In Monitors the KDI I/O pin. This bit cannot be modified. 0: KD I/O pin is low 1: KD I/O pin is high 4 KBFSEL 1 R/W Keyboard Buffer Register Full Select Selects whether the KBF bit is used as the keyboard buffer register full flag or as the KCLK fall interrupt flag. When KBF bit is used as the KCLK fall interrupt flag, the KBE bit in KBCRL should be cleared to 0 to disable reception. 0: KBF bit is used as KCLK fall interrupt flag 1: KBF bit is used as keyboard buffer register full flag 3 KBIE 0 R/W Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer control unit to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled Rev. 1.00 Apr. 28, 2008 Page 594 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Bit 2 Bit Name KBF Initial Value 0 R/W Description Indicates that data reception has been completed and the received data is in KBBR. When both KBIE and KBF are set to1, an interrupt request is sent to the CPU. 0: [Clearing condition] Read KBF when KBF =1, then write 0 in KBF 1: [Setting conditions] * When data has been received normally and has been transferred to KBBR while KBFSEL = 1 (keyboard buffer register full flag) When a KCLK falling edge is detected while KBFSEL = 0 (KCLK interrupt flag) R/(W)* Keyboard Buffer Register Full * 1 PER 0 R/(W)* Parity Error Indicates that an odd parity error has occurred. 0: [Clearing condition] Read PER when PER =1, then write 0 in PER 1: [Setting condition] When an odd parity error occurs 0 KBS 0 R Keyboard Stop Indicates the receive data stop bit. Valid only when KBF = 1. 0: 0 stop bit received 1: 1 stop bit received Note: * Only 0 can be written for clearing the flag. Rev. 1.00 Apr. 28, 2008 Page 595 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3.4 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer control unit pin output. Bit 7 Bit Name KBE Initial Value 0 R/W R/W Description Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled 6 KCLKO 1 R/W Keyboard Clock Out Controls PS2 clock I/O pin output. 0: PS2 clock I/O pin is low 1: PS2 clock I/O pin is high 5 KDO 1 R/W Keyboard Data Out Controls PS2 data I/O pin output. 0: PS2 data I/O pin is low 1: PS2 data I/O pin is high When the start bit (KDO) is automatically cleared (KDO = 1) by means of automatic transmission, 0 is written after reading 1. 4 -- 1 -- Reserved This bit is always read as 1 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 596 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Bit 3 2 1 0 Bit Name RXCR3 RXCR2 RXCR1 RXCR0 Initial Value 0 0 0 0 R/W R R R R Description Receive Counter These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized by a reset and when 0 is written in KBE. Its value returns to B'0000 after a stop bit is received. 0000: -- 0001: Start bit 0010: KB0 0011: KB1 0100: KB2 0101: KB3 0110: KB4 0111: KB5 1000: KB6 1001: KB7 1010: Parity bit 1011: -- 11- -: -- Rev. 1.00 Apr. 28, 2008 Page 597 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.3.5 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit 7 6 5 4 3 2 1 0 Bit Name KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Keyboard Data 7 to 0 8-bit read only data. Initialized to H'00 by a reset or when KBIOE is cleared to 0. 19.3.6 Keyboard Buffer Transmit Data Register (KBTR) KBTR stores transmit data. Bit 7 6 5 4 3 2 1 0 Bit Name KBT7 KBT6 KBT5 KBT4 KBT3 KBT2 KBT1 KBT0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Keyboard Buffer Transmit Data Register 7 to 0 Initialized to H'00 at reset. Rev. 1.00 Apr. 28, 2008 Page 598 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4 19.4.1 Operation Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. Value of KD is valid when the KCLK is low. A sample receive processing flowchart is shown in figure 19.3, and the receive timing in figure 19.4. Start Set KBIOE bit Read KBCRH KCLKI and KDI bits both 1? Yes Set KBE bit Receive enabled state [3] [1] [2] No [1] Set the KBIOE bit to 1 in KBCRL. [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, set the KBE bit (receive enabled state). [3] Detect the start bit output on the keyboard side and receive data in synchronization with the fall of KCLK. [4] When a stop bit is received, the keyboard buffer controller drives KCLK low to disable keyboard transmission (automatic I/O inhibit). If the KBIE bit is set to 1 in KBCRH, an interrupt request is sent to the CPU at the same time. [5] Perform receive data processing. No [6] Clear the KBF flag to 0 in KBCRL. At the same time, the system automatically drives KCLK high, setting the receive enabled state. The receive operation can be continued by Error handling [5] Keyboard side in data transmission state. Execute receive abort processing. KBF = 1? Yes PER = 0? Yes KBS = 1? Yes Read KBBR Receive data processing No [4] No Clear KBF flag (receive enabled state) [6] Figure 19.3 Sample Receive Processing Flowchart Rev. 1.00 Apr. 28, 2008 Page 599 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Receive processing/ error handling KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 Previous data KB0 KB1 Automatic I/O inhibit Receive data 1 Start bit 2 3 9 10 11 Flag cleared 0 1 7 Parity bit Stop bit PER KBS KBF [1] [2] [3] [4] [5] [6] Figure 19.4 Receive Timing Rev. 1.00 Apr. 28, 2008 Page 600 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 19.5, and the transmit timing in figure 19.6. Start Set KBIOE bit Clear KBE bit (reception disabled) Write transmit data to KBTR Read KBCRH Both KCLKI and KDI = 1? Yes Set I/O inhibit (KCLKO = 0) Read KBCRH KDI = 1? Yes Set start bit (KDO = 0)* Set KBTS (KBTS = 1) Clear I/O inhibit (KCLKO = 1) Autmatic transmission (Condition: KBE = 0) [1] [2] [3] [4] [1] Write 1 to the KBIOE bit to enable transmission/ reception. Clear the KBE bit (reception disabled). Write transmit data to KBTR. Read KBCRH, and when both the KCLKI and KDI bits are 1, write 0 to the KCLKO bit to set the I/O inhibit. 60 s or more is required for I/O inhibit. Read KBCRH, and when the KDI bit is 1, write 0 to the KDO (set start bit). Write 1 to the KBTS bit to enter the transmit enabled state. Write 1 to the KCLKO bit to clear the I/O inhibit. Check D0 to D7, the parity bit, the stop bit, and receive completion notification (send data at the falling edge of the KCLK signal). The KBTE bit is set to 1 at the eleventh rising edge of the KCLK signal. When KTIE = 1, a CPU interrupt occurs. [2] [3] [4] No [5] Receive termination processing execution KDO retains 1 [6] [5] [7] No Retransmit request processing execution KCLKO retains 0 [6] [9] [8] [7] KDO retains 0 [8] [9] [10] When KTER = 0, transmission is successfully completed. [11] Clear the KBTE bit to 0. KBTE = 1 Yes KTER = 0 Yes Clear KBTE bit No [10] No [11] Note: * The start bit (KDO = 0) is automatically initialized (KDO = 1) when automatic transmission is started. After initialization, to write 0 to KDO, read 1 before writing 0 to it. Error handling To transmit operation or receive operation Figure 19.5 Sample Transmit Processing Flowchart Rev. 1.00 Apr. 28, 2008 Page 601 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) I/O inhibit KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KBTE KTER KBTS I/O inhibit Start bit 0 1 7 Parity 1 2 8 9 10 11 Receive completed Stop bit notification [4] [6] [7] [8] [9] [10] [11] [1] to [3] [5] Figure 19.6 Transmit Timing 19.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted. Thus the system can abort reception by holding the clock low for a certain period. A sample receive abort processing flowchart is shown in figure 19.7, and the receive abort timing in figure 19.8. Rev. 1.00 Apr. 28, 2008 Page 602 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Start Receive state Read KBCRL KBF = 0? Yes Read KBCRH No Processing 1 No [1] [1] Read KBCRL, and if KBF = 1, perform processing 1. [2] Read KBCRH, and if the value of bits RXCR3 to RXCR0 is less than B'1001, write 0 in KCLKO to abort reception. [3] If the value of bits RXCR3 to RXCR0 is B'1001 or greater, wait until stop bit reception is completed, then perform receive data processing, and proceed to the next operation. If the value of bits RXCR3 to RXCR0 is B'1001 or greater, the parity bit is being received. With the PS2 interface, a receive abort request following parity bit reception is disabled. Wait until stop bit reception is completed, perform receive data processing and clear the KBF flag, then proceed to the next operation. RXCR3 to RXCR0 B'1001? Yes Disable receive abort requests [3] [2] KCLKO = 0 (receive abort request) Retransmit command transmission (data)? Yes KBE = 0 (disable KBBR reception and clear receive counter) Set start bit (KDO = 0) Clear I/O inhibit (KCLKO = 1) Transmit data No KBE = 0 (disable KBBR reception and clear receive counter) KBE = 1 (enable KB operation) Clear I/O inhibit (KCLKO = 1) To transmit operation To receive operation Figure 19.7 Sample Receive Abort Processing Flowchart (1) Rev. 1.00 Apr. 28, 2008 Page 603 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Processing 1 [1] [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. Receive operation ends normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 19.7 Sample Receive Abort Processing Flowchart (2) Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period. Transmit operation Reception in progress KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KD (input) KD (output) Receive abort request Start bit Figure 19.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing Rev. 1.00 Apr. 28, 2008 Page 604 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.4 KCLKI and KDI Read Timing Figure 19.9 shows the KCLKI and KDI read timing. T1 T2 * Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.9 KCLKI and KDI Read Timing 19.4.5 KCLKO and KDO Write Timing Figure 19.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states. T1 T2 * Internal write signal KCLKO, KDO (register) KCLK, KD (pin state) Note: * here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.10 KCLKO and KDO Write Timing Rev. 1.00 Apr. 28, 2008 Page 605 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.6 KBF Setting Timing and KCLK Control Figure 19.11 shows the KBF setting timing and the KCLK pin states. * KCLK (pin) Internal KCLK Falling edge signal RXCR3 to RXCR0 KBF KCLK (output) 11th fall B'1010 B'0000 Automatic I/O inhibit Note: * here indicates the clock signal frequency-divided by N for medium-speed mode. Figure 19.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 1.00 Apr. 28, 2008 Page 606 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.7 Receive Timing Figure 19.12 shows the receive timing. * KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 Note: * here indicates the clock signal frequency-divided by N for medium-speed mode. N N+1 N+2 Figure 19.12 Receive Counter and KBBR Data Load Timing 19.4.8 Operation during Data Reception If the KBS bit in KBCRH is set to 1 with other keyboard buffer control units in reception*, the KCLK is automatically pulled down. Figure 19.13 shows receive timing and the KCLK. Note: * Period from the first falling edge of KCLK to completion of reception (KBF = 1). 1 KCLK KD KBF KCLK for other PS/2 2 8 9 10 11 Automatic I/O inhibit Start bit 0 1 7 Parity Stop bit Figure 19.13 Receive Timing and KCLK Rev. 1.00 Apr. 28, 2008 Page 607 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.9 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRH to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 19.14 shows the setting method and an example of operation. Start Set KBIOE KBE = 0 (KBBR reception disabled) KBFSEL = 0 KBIE = 1 (KCLK falling edge interrupts enabled) KCLK (pin state) KBF bit KCLK pin fall detected? Yes KBF = 1 (interrupt generated) Interrupt handling Clear KBF No Interrupt generated Cleared by software Interrupt generated Note: * The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does not operate. Figure 19.14 Example of KCLK Input Fall Interrupt Operation Rev. 1.00 Apr. 28, 2008 Page 608 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.4.10 First KCLK Falling Interrupt An interrupt can be generated by detecting the first falling edge of KCLK on reception and transmission. Software standby mode and watch mode can be cancelled by a first KCLK falling interrupt. * Reception When both KBIOE and KBE are set to 1, KCIF is set after the first falling edge of KCLK has been detected. At this time, if KCIE is set to 1, the CPU is requested an interrupt. KCIF is set at the same time when the RXCR3 to RXCR0 bits in KBCRL are incremented from B'0000 to B'0001. * Transmission When both KBIOE and KBTS are set to 1, the KCIF is set after the first falling edge of KCLK has been detected. At this time, if KCIE is set to 1, the CPU is requested an interrupt. KCIF is set at the same time when the TXCR3 to TXCR0 bits in KBCR2 are incremented from B'0000 to B'0001. * Determining interrupt generation By checking the KBE, KBTS, and KBTE bits, it can be determined whether the first KCLK falling interrupt is occurred during reception or transmission. During reception: KBE = 1 During transmission: KBTS = 1 or KBTE = 1 (Check KBTE = 1 because the KBTS is automatically cleared after transfer has been completed.) 1 2 3 I/O inhibit 1 2 KCLK KD RXCR3 to RXCR0 Interrupt internal signal 0000 KCLK KD TXCR3 to TXCR0 Interrupt internal signal Start bit 0001 0 0010 1 Start bit 0000 0 0001 1 0010 Interrupt generated (a) Reception Interrupt generated (b) Transmission Figure 19.15 Timing of First KCLK Interrupt Rev. 1.00 Apr. 28, 2008 Page 609 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) * Canceling software standby mode and watch mode Software standby mode and watch mode are cancelled by a first KCLK falling interrupt. In this case, an interrupt is generated at the first KCLK since software standby mode or watch mode has been shifted (figure 19.17). Notes on canceling operation are explained below. When a transition to software standby mode or watch mode is performed while both KBIOE and KCIE are set to 1, canceling the current mode is enabled by a first KCLK falling interrupt (the KBE and KBTS are not affected). When software standby mode and watch mode are cancelled by a first KCLK falling interrupt, the KCIF flag is not set (only the internal flag is set). In the first KCLK interrupt handling routine, the KCIF bit is checked. If the KCIF is 0, it indicates that the interrupt is generated after software standby mode and watch mode have been cancelled. When software standby mode or watch mode is cancelled by receiving a receive clock, the reception is ignored. Execute reception terminating processing by an interrupt handing routine, and then request retransfer. When transition to software standby mode or watch mode is made and the mode is canceled by a first KCLK falling interrupt during data transmission, state before performing mode transition is held immediately after canceling the mode. Therefore, initialization by an interrupt handling routine is required. Precautions as (b) and (c) which are shown in figure 19.17 should be applied on interrupt generation. Priority of canceling software standby mode and watch mode is decided by the setting of ICR. The interrupt signal path and flag setting of the first KCLK interrupt in normal operation differ from those in software standby mode and watch mode. Figure 19.6 shows the interrupt signal paths of the first KCLK interrupt. Signal A: Interrupt signal in normal operation Signal B: Interrupt signal in software standby mode and watch mode KCLK is input directly to the interrupt control block, not through the PS2, in software standby mode and watch mode, and then an interrupt is generated by detection of a falling edge. Therefore, the KCIF flag is not set. In this case, a flag that is in the interrupt control block is set. The internal flag is automatically cleared after an interrupt request is sent to the CPU. Figure 19.18 shows setting and clearing timing. Rev. 1.00 Apr. 28, 2008 Page 610 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) Software standby mode and watch mode Interrupt control block B KCLK PS2 Interrupt control A Falling edge detection circuit Interrupt vector generation circuit Interrupt request to CPU Figure 19.16 First KCLK Interrupt Path (a) Interrupt timing in software standby mode and watch mode 1 KCLK Software standby mode and watch mode internal signal Interrupt internal signal Interrupt generated (b) When a transition to software standby mode or watch mode is performed while the KCLI is high 4 KCLK Software standby mode and watch mode internal signal Interrupt internal signal Interrupt generated (c) When a transition to software standby mode or watch mode is performed while the KCLK is low 4 KCLK Software standby mode and watch mode internal signal Interrupt internal signal Interrupt generated 5 6 5 6 2 Figure 19.17 Interrupt Timing in Software Standby Mode and Watch Mode Rev. 1.00 Apr. 28, 2008 Page 611 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 1 KCLK First KCLK falling edge 2 3 Internal flag Automatic clear Interrupt generated Interrupt accepted (Accepted at any timing) Figure 19.18 Internal Flag of First KCLK Falling Interrupt in Software Standby Mode and Watch Mode Rev. 1.00 Apr. 28, 2008 Page 612 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.5 19.5.1 Usage Notes KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 19.19 shows the timing of KBIOE setting and KCLK falling edge detection. T1 T2 KCLK (pin) Internal KCLK (KCLKI) KBIOE Falling edge signal KBFSEL KBE KBF Figure 19.19 KBIOE Setting and KCLK Falling Edge Detection Timing Rev. 1.00 Apr. 28, 2008 Page 613 of 994 REJ09B0452-0100 Section 19 Keyboard Buffer Control Unit (PS2) 19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission Figure 19.20 shows the relationship between the KD output by the KDO bit (KBCRL) and by the automatic transmission. Switch to the KD output by the automatic transmission is performed when KBTS is set to 1 and TXCR is not cleared to 0. In this case, the KD output by the KDO bit (KBCRL) is masked. Output switch signal KBTS * (TXCR0 + TXCR1 + TXCR2 + TXCR3) Output by KDO bit (KBCRL) KD output Output by automatic transmission Figure 19.20 KDO Output 19.5.3 Module Stop Mode Setting Keyboard buffer control unit operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer control unit operation to be halted. Register access is enabled by canceling module stop mode. For details, see section 26, Power-Down Modes. 19.5.4 Medium-Speed Mode In medium-speed mode, the KBU operates with the medium-speed clock. For normal operation of the KBU, set the medium-speed clock to a frequency of 300 kHz or higher. 19.5.5 Transmit Completion Flag (KBTE) When TXCR3 to TXCR0 are 1011 (transmit completion notification) and then the TXCR3 to TXCR0 are initialized by clearing KBIOE or KBTS to 0, the transmit completion flag (KBTE) is set. In this case, KTER is invalid. Rev. 1.00 Apr. 28, 2008 Page 614 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Section 20 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC includes four register sets, each of which comprises data and status registers, control register, the fast Gate A20 logic circuit, and the host interrupt request circuit. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC module supports I/O read and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the LPC interface. 20.1 Features * Supports LPC interface I/O read and I/O write cycles Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data. Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME). * Four register sets comprising data and status registers The basic register set comprises three bytes: an input register (IDR), output register (ODR), and status register (STR). I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 4. A fast Gate A20 function is provided for channel 1. For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to the basic register set. * Supports SCIF The LPC interface is connected to the SCIF, allowing direct control of the SCIF by the LPC host. * Supports SERIRQ Host interrupt requests are transferred serially on a single signal line (SERIRQ). On channel 1, HIRQ1 and HIRQ12 can be generated. On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated. In the SCIF, HIRQ1, SMI, and HIRQ3 to HIRQ15 can be generated. Operation can be switched between quiet mode and continuous mode. The CLKRUN signal can be manipulated to restart the PCI clock (LCLK). * Power-down modes and interrupts The LPC module can be shut down by inputting the LPCPD signal. Three pins, PME, LSMI, and LSCI, are provided for general input/output. Rev. 1.00 Apr. 28, 2008 Page 615 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Figure 20.1 shows a block diagram of the LPC. Module data bus TWR0MW IDR4 IDR3 IDR2 IDR1 Parallel serial conversion SERIRQ TWR1 to TWR15 SIRQCR0 to 4 HISEL CLKRUN Cycle detection Serial parallel conversion Control logic LPCPD LFRAME Address match LRESET LAD0 to LAD3 LADR1H/L LADR2H/L LADR3H/L LADR4H/L SCIFADRH/L LSCIE LSCIB LSCI input LSMIE LSMIB LSMI input PMEE PMEB PME input LCLK LSCI LSMI Serial parallel conversion PME SYNC output ODR4 TWR0SW ODR3 ODR2 ODR1 STR4 STR3 STR2 STR1 OBEI IBFI4 IBFI1 IBFI2 IBFI3 ERRI HICR0 to HICR5 GA20 TWR1 to TWR15 Internal interrupt control [Legend] HICR0 to HICR5: Host interface control registers 0 to 5 LADR1H/L to 4H/L: LPC channel 1 to 4 address registers H and L SCIFADRH/L: SCIF address register H and L IDR1 to IDR4: Input data registers 1 to 4 ODR1 to ODR4: Output data registers 1 to 4 STR1 to STR4: Status registers 1 to 4 TWR0MW: Bidirectional data register 0MW TWR0SW: Bidirectional data register 0SW TWR1 to TWR15: Bidirectional data registers 1 to 15 SIRQCR0 to SIRQCR4: SERIRQ control registers 0 to 4 HISEL: Host interface select register Figure 20.1 Block Diagram of LPC Rev. 1.00 Apr. 28, 2008 Page 616 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.2 Input/Output Pins Table 20.1 lists the LPC pin configuration. Table 20.1 Pin Configuration Name LPC address/ data 3 to 0 LPC frame LPC reset LPC clock Serialized interrupt request LSCI general output LSMI general output PME general output GATE A20 LPC clock run LPC power-down Abbreviation Port I/O Function Cycle type/address/data signals serially (4-signal-line) transferred in synchronization with LCLK Transfer cycle start and forced termination signal LPC interface reset signal 33-MHz PCI clock signal Serialized host interrupt request signal in synchronization with LCLK General output General output General output Gate A20 control signal output LCLK restart request signal when serial host interrupt is requested LPC module shutdown signal LAD3 to LAD0 P33 to P30 I/O LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD P34 P35 P36 P37 PB1 PB0 P80 P81 P82 P83 Input*1 Input*1 Input I/O* 1 Output*1, *2 Output*1, *2 Output*1, *2 Output*1, *2 I/O* * 1, 2 Input*1 Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output function. 2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an external resistor is necessary to pull the signal up to VCC. Rev. 1.00 Apr. 28, 2008 Page 617 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3 Register Descriptions The LPC has the following registers. Table 20.2 Register Configuration Initial Data Bus Abbreviation Slave Host Value Address Width HICR0 HICR1 HICR2 HICR3 HICR4 HICR5 LADR1H LADR1L LADR2H LADR2L LADR3H LADR3L LADR4H LADR4L IDR1 IDR2 IDR3 IDR4 ODR1 ODR2 ODR3 ODR4 STR1 STR2 STR3 STR4 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W W W W W R R R R R R R R H'00 H'00 H'00 H'00 H'00 H'60 H'00 H'62 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FE40 H'FE41 H'FE42 H'FE43 H'FDD9 H'FE33 H'FDC0 H'FDC1 H'FDC2 H'FDC3 H'FE34 H'FE35 H'FDD4 H'FDD5 H'FE38 H'FE3C H'FE30 H'FDD6 H'FE39 H'FE3D H'FE31 H'FDD7 H'FE3A H'FE3E H'FE32 H'FDD8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R/W Register Name Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3 Host interface control register 4 Host interface control register 5 LPC channel 1 address register H LPC channel 1 address register L LPC channel 2 address register H LPC channel 2 address register L LPC channel 3 address register H LPC channel 3 address register L LPC channel 4 address register H LPC channel 4 address register L Input data register 1 Input data register 2 Input data register 3 Input data register 4 Output data register 1 Output data register 2 Output data register 3 Output data register 4 Status register 1 Status register 2 Status register 3 Status register 4 Rev. 1.00 Apr. 28, 2008 Page 618 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Register Name Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 SERIRQ control register 0 SERIRQ control register 1 SERIRQ control register 2 SERIRQ control register 3 SERIRQ control register 4 Host interface select register SCIF address register H SCIF address register L Initial Data Bus Abbreviation Slave Host Value Address Width TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 SIRQCR0 SIRQCR1 SIRQCR2 SIRQCR3 SIRQCR4 HISEL SCIFADRH SCIFADRL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'03 H'03 H'F8 H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE36 H'FE37 H'FDDA H'FDDB H'FE3B H'FE3F H'FDC4 H'FDC5 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 R/W Notes: R/W in the register description means as follows: 1. R/W slave indicates access from the slave (this LSI). 2. R/W host indicates access from the host. Rev. 1.00 Apr. 28, 2008 Page 619 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface. * HICR0 Initial Value 0 0 0 R/W Slave Host Description R/W R/W R/W LPC Enables 3 to 1 Enable or disable the LPC interface function. When the LPC interface is enabled (one of the three bits is set to 1), processing for data transfer between the slave (this LSI) and the host is performed using pins LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and LPCPD. * LPC3E 0: LPC channel 3 operation is disabled No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15 1: LPC channel 3 operation is enabled * LPC2E 0: LPC channel 2 operation is disabled No address (LADR2) matches for IDR2, ODR2, or STR2 1: LPC channel 2 operation is enabled * LPC1E 0: LPC channel 1 operation is disabled No address (LADR1) matches for IDR1, ODR1, or STR1 1: LPC channel 1 operation is enabled Bit 7 6 5 Bit Name LPC3E LPC2E LPC1E Rev. 1.00 Apr. 28, 2008 Page 620 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 4 Bit Name FGA20E Initial Value 0 R/W Slave Host Description R/W Fast Gate A20 Function Enable Enables or disables the fast Gate A20 function. When the fast Gate A20 is disabled, the normal Gate A20 can be implemented by firmware controlling P81 output. 0: Fast Gate A20 function disabled Other function (input/output) of pin P81 is enabled The internal state of GA20 output is initialized to 1 1: Fast Gate A20 function enabled GA20 pin output is open-drain (external pull-up resistor (Vcc) required) 3 SDWNE 0 R/W LPC Software Shutdown Enable Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 20.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state, LPC software shutdown setting enabled [Clearing conditions] * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown release (rising edge of LPCPD signal) 1: LPC hardware shutdown state setting enabled Hardware shutdown state when LPCPD signal is low level [Setting condition] Writing 1 after reading SDWNE = 0 Rev. 1.00 Apr. 28, 2008 Page 621 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 2 Bit Name PMEE Initial Value 0 R/W Slave Host Description R/W PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor (Vcc) is needed. PMEE 0 1 1 PMEB X 0 1 : PME output disabled, other function of pin is enabled : PME output enabled, PME pin output goes to 0 level : PME output enabled, PME pin output is high-impedance 1 LSMIE 0 R/W LSMI output Enable Controls LSMI output in combination with the LSMIB bit in HICR1. LSMI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. LSMIE 0 1 1 LSMIB X 0 1 : LSMI output disabled, other function of pin is enabled : LSMI output enabled, LSMI pin output goes to 0 level : LSMI output enabled, LSMI pin output is Hi-Z 0 LSCIE 0 R/W LSCI output Enable Controls LSCI output in combination with the LSCIB bit in HICR1. LSCI pin output is open-drain, and an external pull-up resistor (Vcc) is needed. LSCIE 0 1 1 LSCIB X 0 1 : LSCI output disabled, other function of pin is enabled : LSCI output enabled, LSCI pin output goes to 0 level : LSCI output enabled, LSCI pin output is high-impedance [Legend] X: Don't care Rev. 1.00 Apr. 28, 2008 Page 622 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * HICR1 R/W Initial Bit Name Value Slave Host Description LPCBSY 0 R LPC Busy Indicates that the LPC interface is processing a transfer cycle. 0: LPC interface is in transfer cycle wait state * * Bus idle, or transfer cycle not subject to processing is in progress Cycle type or address indeterminate during transfer cycle LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown Forced termination (abort) of transfer cycle subject to processing Normal termination of transfer cycle subject to processing Bit 7 [Clearing conditions] * * * * 1: LPC interface is performing transfer cycle processing [Setting condition] Match of cycle type and address 6 CLKREQ 0 R LCLK Request Indicates that the LPC interface's SERIRQ output is requesting a restart of LCLK. 0: No LCLK restart request [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown There are no further interrupts for transfer to the host in quiet mode in which SERIRQ is set to continuous mode 1: LCLK restart request issued [Setting condition] In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped Rev. 1.00 Apr. 28, 2008 Page 623 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 5 R/W Initial Bit Name Value Slave Host Description IRQBSY 0 R SERIRQ Busy Indicates that the LPC interface's SERIRQ is engaged in transfer processing. 0: SERIRQ transfer frame wait state [Clearing conditions] * * * LPC hardware reset or LPC software reset LPC hardware shutdown or LPC software shutdown End of SERIRQ transfer frame 1: SERIRQ transfer processing in progress [Setting condition] Start of SERIRQ transfer frame 4 LRSTB 0 R/W LPC Software Reset Bit Resets the LPC interface. For the scope of initialization by an LPC reset, see section 20.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * Writing 0 LPC hardware reset 1: LPC software reset state [Setting condition] Writing 1 after reading LRSTB = 0 Rev. 1.00 Apr. 28, 2008 Page 624 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 3 R/W Initial Bit Name Value Slave Host Description SDWNB 0 R/W LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 20.4.4, LPC Interface Shutdown Function (LPCPD). 0: Normal state [Clearing conditions] * * * * Writing 0 LPC hardware reset or LPC software reset LPC hardware shutdown (falling edge of LPCPD signal when SDWNE = 1) LPC hardware shutdown release (rising edge of LPCPD signal when SDWNE = 0) 1: LPC software shutdown state [Setting condition] Writing 1 after reading SDWNB = 0 2 PMEB 0 R/W PME Output Bit Controls PME output in combination with the PMEE bit. For details, refer to description on the PMEE bit in HICR0. 1 LSMIB 0 R/W LSMI Output Bit Controls LSMI output in combination with the LSMIE bit. For details, refer to description on the LSMIE bit in HICR0. 0 LSCIB 0 R/W LSCI output Bit Controls LSCI output in combination with the LSCIE bit IN HICR0. For details, refer to description on the LSCIE bit in HICR0. Rev. 1.00 Apr. 28, 2008 Page 625 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3) HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 and the bit 7 in HICR2 monitor the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless of the LPC interface operating state or the operating state of the functions that use pin multiplexing. * HICR2 Initial Value 0 R/W Slave Host Description GA20 Pin Monitor LPC Reset Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware reset occurs. 0: [Clearing condition] Writing 0 after reading LRST = 1 1: [Setting condition] LRESET pin falling edge detection 5 SDWN 0 R/(W)* LPC Shutdown Interrupt Flag This bit is a flag that generates an ERRI interrupt when an LPC hardware shutdown request is generated. 0: [Clearing conditions] * * * Writing 0 after reading SDWN = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) 1: [Setting condition] LPCPD pin falling edge detection R/(W)* Bit 7 6 Bit Name GA20 LRST Undefined R Rev. 1.00 Apr. 28, 2008 Page 626 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 4 Bit Name ABRT Initial Value 0 R/W Slave Host Description LPC Abort Interrupt Flag This bit is a flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs. 0: [Clearing conditions] * * * * Writing 0 after reading ABRT = 1 LPC hardware reset (LRESET pin falling edge detection) LPC software reset (LRSTB = 1) LPC hardware shutdown (SDWNE = 1 and LPCPD pin falling edge detection) * LPC software shutdown (SDWNB = 1) 1: [Setting condition] LFRAME pin falling edge detection during LPC transfer cycle R/(W)* 3 IBFIE3 0 R/W IDR3 and TWR Receive Complete interrupt Enable Enables or disables IBFI3 interrupt to the slave (this LSI). 0: Input data register IDR3 and TWR receive complete interrupt requests disabled 1: [When TWRIE = 0 in LADR3] Input data register (IDR3) receive complete interrupt requests enabled [When TWRIE = 1 in LADR3] Input data register (IDR3) and TWR receive complete interrupt requests enabled 2 IBFIE2 0 R/W IDR2 Receive Complete interrupt Enable Enables or disables IBFI2 interrupt to the slave (this LSI). 0: Input data register (IDR2) receive complete interrupt requests disabled 1: Input data register (IDR2) receive complete interrupt requests enabled Rev. 1.00 Apr. 28, 2008 Page 627 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Bit 1 Bit Name IBFIE1 Initial Value 0 R/W Slave Host Description R/W IDR1 Receive Complete interrupt Enable Enables or disables IBFI1 interrupt to the slave (this LSI). 0: Input data register (IDR1) receive complete interrupt requests disabled 1: Input data register (IDR1) receive complete interrupt requests enabled 0 ERRIE 0 R/W Error Interrupt Enable Enables or disables ERRI interrupt to the slave (this LSI). 0: Error interrupt requests disabled 1: Error interrupt requests enabled Note: * Only 0 can be written to bits 6 to 4, to clear the flag. * HICR3 R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description LFRAME Undefined CLKRUN Undefined SERIRQ LRESET LPCPD PME LSMI LSCI Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R LFRAME Pin Monitor CLKRUN Pin Monitor SERIRQ Pin Monitor LRESET Pin Monitor LPCPD Pin Monitor PME Pin Monitor LSMI Pin Monitor LSCI Pin Monitor Rev. 1.00 Apr. 28, 2008 Page 628 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.3 Host Interface Control Register 4 (HICR4) HICR4 enables/disables channel 4 and controls interrupts to the channel 4 of an LPC interface slave (this LSI). Initial Value 0 0 R/W Slave Host Description R/W R/W Reserved The initial value bit should not be changed. 6 LPC4E LPC Enable 4 0: LPC channel 4 is disabled For IDR4, ODR4, and STR4, address (LADR4) match is not occurred. 1: LPC channel 4 enabled 5 IBFIE4 0 R/W IDR4 Receive Completion Interrupt Enable Enables or disables IBFI4 interrupt to the slave (this LSI). 0: Input data register (IDR4) receive complete interrupt requests disabled 1: Input data register (IDR4) receive complete interrupt requests enabled 4 to 0 All 0 R/W Reserved The initial value should not be changed. Bit 7 Bit Name Rev. 1.00 Apr. 28, 2008 Page 629 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.4 Host Interface Control Register 5 (HICR5) HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts. Initial Value 0 R/W Slave Host Description R/W Output Buffer Empty Interrupt Enable Enables or disables OBEI interrupts (for this LSI). 0: Output buffer empty interrupt request is disabled 1: Output buffer empty interrupt request is enabled 6 OBEI 0 R/W Output Buffer Empty Interrupt Flag 0: [Clearing conditions] * * Writing 0 after reading OBEI = 1 LPC hardware reset or LPC software reset Bit 7 Bit Name OBEIE 1: [Setting condition] When one of OBF1, OBF2, OBF3A, OBF3B, and OBF4 is cleared 5 to 4 3 SCIFE All 0 0 R/W R/W Reserved The initial value bit should not be changed. SCIF Enable Enables or disables access from the LPC host of the SCIF. 0: Disables access from the LPC host of the SCIF 1: Enables access from the LPC host of the SCIF 2 to 0 All 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 630 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L) LADR1 sets the LPC channel 1 host address. The LADR1 contents must not be changed while channel 1 is operating (while LPC1E is set to 1). * LADR1H Initial Value 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Channel 1 Address Bits 15 to 8 Set the LPC channel 1 host address. Bit 7 6 5 4 3 2 1 0 Bit Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 * LADR1L Initial Value 0 1 1 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W Reserved This bit is ignored when an address match is decided. 1 0 Bit 1 Bit 0 0 0 R/W R/W Channel 1 Address Bits 1 and 0 Set the LPC channel 1 host address. Channel 1 Address Bits 7 to 3 Set the LPC channel 1 host address. Bit 7 6 5 4 3 2 Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Rev. 1.00 Apr. 28, 2008 Page 631 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * Host select register I/O Address Bits 5 to 3 Bits 15 to 3 in LADR1 Bits 15 to 3 in LADR1 Bits 15 to 3 in LADR1 Bits 15 to 3 in LADR1 Note: * Bit 2 0 1 0 1 Bits 1 and 0 Bits 1 and 0 in LADR1 Bits 1 and 0 in LADR1 Bits 1 and 0 in LADR1 Bits 1 and 0 in LADR1 Transfer Cycle I/O write I/O write I/O read I/O read Host Select Register IDR1 write (data) IDR1 write (command) ODR1 read STR1 read When channel 1 is used, the content of LADR1 must be set so that the addresses for channels 2, 3, 4, and SCIF are different. 20.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L) LADR2 sets the LPC channel 2 host address. The LADR2 contents must not be changed while channel 2 is operating (while LPC2E is set to 1). * LADR2H Initial Value 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Channel 2 Address Bits 15 to 8 Set the LPC channel 2 host address. Bit 7 6 5 4 3 2 1 0 Bit Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Rev. 1.00 Apr. 28, 2008 Page 632 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * LADR2L Initial Value 0 1 1 0 0 0 1 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Reserved This bit is ignored when an address match is decided. 1 0 Bit 1 Bit 0 Channel 2 Address Bits 1 and 0 Set the LPC channel 2 host address. Channel 2 Address Bits 7 to 3 Set the LPC channel 2 host address. Bit 7 6 5 4 3 2 Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 * Host select register I/O Address Bits 5 to 3 Bits 15 to 3 in LADR2 Bits 15 to 3 in LADR2 Bits 15 to 3 in LADR2 Bits 15 to 3 in LADR2 Note: * Bit 2 0 1 0 1 Bits 1 and 0 Bits 1 and 0 in LADR2 Bits 1 and 0 in LADR2 Bits 1 and 0 in LADR2 Bits 1 and 0 in LADR2 Transfer Cycle I/O write I/O write I/O read I/O read Host Select Register IDR2 write (data) IDR2 write (command) ODR2 read STR2 read When channel 2 is used, the content of LADR2 must be set so that the addresses for channels 1, 3, 4, and SCIF are different. Rev. 1.00 Apr. 28, 2008 Page 633 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L) LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data registers. The contents of the address fields in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1). * LADR3H R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 3 Address Bits 15 to 8 Set the LPC channel 3 host address. * LADR3L R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 TWRE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reserved The initial value should not be changed. Channel 3 Address Bit 1 Sets the LPC channel 3 host address. Bidirectional Data Register Enable Enables or disables bidirectional data register operation. 0: TWR operation is disabled TWR-related I/O address match determination is halted 1: TWR operation is enabled Rev. 1.00 Apr. 28, 2008 Page 634 of 994 REJ09B0452-0100 Channel 3 Address Bits 7 to 3 Set the LPC channel 3 host address. Section 20 LPC Interface (LPC) When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 in LADR3 is inverted, and the values of bits 3 to 0 are ignored. * Host select register I/O Address Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 4 Bit 3 Bit 3 Bit 3 Bit 3 Bit 3 0 0 : 1 Bit 4 Bit 4 0 0 : 1 Note: * Bit 2 0 1 0 1 0 0 : 1 0 0 : 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 0 0 : 1 0 0 : 1 Bit 0 0 0 0 0 0 1 : 1 0 1 : 1 I/O read I/O read TWR0SW read TWR1 to TWR15 read Transfer Cycle I/O write I/O write I/O read I/O read I/O write I/O write Host Select Register IDR3 write, C/D3 0 IDR3 write, C/D3 1 ODR3 read STR3 read TWR0MW write TWR1 to TWR15 write When channel 3 is used, the content of LADR3 must be set so that the addresses for channels 1, 2, 4, and SCIF are different. Rev. 1.00 Apr. 28, 2008 Page 635 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L) LADR4 sets the LPC channel 4 host address. The LADR4 contents must not be changed while channel 4 is operating (while LPC4E is set to 1). * LADR4H R/W Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value Slave Host Description Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 4 Address Bits 15 to 8 Set the LPC channel 4 host address. * LADR4L R/W Bit 7 6 5 4 3 2 Bit Name Initial Value Slave Host Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Reserved This bit is ignored when an address match is decided. 1 0 Bit 1 Bit 0 0 0 R/W R/W Channel 4 Address Bits 1 and 0 Set the LPC channel 4 host address. Channel 4 Address Bits 7 to 3 Set the LPC channel 4 host address. Rev. 1.00 Apr. 28, 2008 Page 636 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * Host select register I/O Address Bits 5 to 3 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Bits 15 to 3 in LADR4 Note: * Bit 2 0 1 0 1 Bits 1 and 0 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Bits 1 and 0 in LADR4 Transfer Cycle I/O write I/O write I/O read I/O read Host Select Register IDR4 write (data) IDR4 write (command) ODR4 read STR4 read When channel 4 is used, the content of LADR4 must be set so that the addresses for channels 1, 2, 3 and SCIF are different. 20.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) IDR1 to IDR4 are 8-bit read-only registers for the slave (this LSI), and 8-bit write-only registers for the host. The registers selected from the host according to the I/O address are shown in the following table. Data transferred in an LPC I/O write cycle is written to the selected register. The value of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether the written information is a command or data. The initial values of IDR1 to IDR4 are H'00. I/O Address Bits 15 to 4 Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Bit 3 Bit 3 Bit 3 Bit 2 0 1 Bit 1 Bit 1 Bit 1 Bit 0 Bit 0 Bit 0 Transfer Cycle I/O write I/O write Host Register Selection IDRn write, C/Dn 0 IDRn write, C/Dn 1 20.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4) ODR1 to ODR4 are 8-bit readable/writable registers for the slave (this LSI), and 8-bit read-only registers for the host. The registers selected from the host according to the I/O address are shown in the following table. In an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of ODR1 to ODR4 are H'00. I/O Address Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Bit 3 Bit 3 Bit 2 0 Bit 1 Bit1 Bit 0 Bit 0 Transfer Cycle I/O read Host Register Selection ODRn read Rev. 1.00 Apr. 28, 2008 Page 637 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave (this LSI) and host. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host and the slave addresses. TWR0MW is a write-only register for the host, and a read-only register for the slave, while TWR0SW is a write-only register for the slave and a readonly register for the host. When the host and slave begin a write, after the respective registers of TWR0 have been written to, arbitration for simultaneous access is performed by checking the status flags whether or not those writes were valid. For the registers selected from the host according to the I/O address, see section 20.3.7, LPC Channel 3 Address Registers H and L (LADR3H and LADR3L). Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to TWR15 are H'00. 20.3.12 Status Registers 1 to 4 (STR1 to STR4) STR1 to STR4 are 8-bit registers that indicate status information during LPC interface processing. The registers selected from the host according to the I/O address are shown in the following table. In an LPC I/O read cycle, the data in the selected register is transferred to the host. I/O Address Bits 15 to 4 Bits 15 to 4 n = 1 to 4 Bit 3 Bit 3 Bit 2 1 Bit 1 Bit1 Bit 0 Bit 0 Transfer Cycle I/O read Host Register Selection STRn read Rev. 1.00 Apr. 28, 2008 Page 638 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * STR1 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave DBU17 DBU16 DBU15 DBU14 C/D1 0 0 0 0 0 R/W R/W R/W R/W R Host Description R R R R R Command/Data When the host writes to IDR1, bit 2 of the I/O address is written into this bit to indicate whether IDR1 contains data or a command. 0: Content of input data register (IDR1) is a data 1: Content of input data register (IDR1) is a command 2 1 DBU12 IBF1 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). The IBF1 flag setting and clearing conditions are different when the fast Gate A20 is used. For details, see table 20.5. 0: [Clearing condition] When the slave reads IDR1 1: [Setting condition] When the host writes to IDR1 in I/O write cycle 0 OBF1 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * When the host reads ODR1 in I/O read cycle When the slave writes 0 to the OBF1 bit Defined by User The user can use these bits as necessary. 1: [Setting condition] When the slave writes to ODR1 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 639 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * STR2 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave DBU27 DBU26 DBU25 DBU24 C/D2 0 0 0 0 0 R/W R/W R/W R/W R Host Description R R R R R Command/Data When the host writes to IDR2, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command. 0: Content of input data register (IDR2) is a data 1: Content of input data register (IDR2) is a command 2 1 DBU22 IBF2 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR2 1: [Setting condition] When the host writes to IDR2 in I/O write cycle 0 OBF2 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * When the host reads ODR2 in I/O read cycle When the slave writes 0 to the OBF2 bit Defined by User The user can use these bits as necessary. 1: [Setting condition] When the slave writes to ODR2 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 640 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit 7 Bit Name Initial Value Slave Host Description IBF3B 0 R R Bidirectional Data Register Input Buffer Full Flag This is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR15 in I/O write cycle 6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full Flag 0: [Clearing conditions] * * When the host reads TWR15 in I/O read cycle When the slave writes 0 to the OBF3B bit 1: [Setting condition] When the slave writes to TWR15 5 MWMF 0 R R Master Write Mode Flag 0: [Clearing condition] When the slave reads TWR15 1: [Setting condition] When the host writes to TWR0 in I/O write cycle while SWMF = 0 4 SWMF 0 R/(W)* R Slave Write Mode Flag In the event of simultaneous writes by the master and the slave, the master write has priority. 0: [Clearing conditions] * * When the host reads TWR15 in I/O read cycle When the slave writes 0 to the SWMF bit 1: [Setting condition] When the slave writes to TWR0 while MWMF = 0 Rev. 1.00 Apr. 28, 2008 Page 641 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 3 Bit Name Initial Value Slave C/D3 0 R Host Description R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 1 DBU32 IBF3A 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR3 1: [Setting condition] When the host writes to IDR3 in I/O write cycle 0 OBF3A 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * When the host reads ODR3 in I/O read cycle When the slave writes 0 to the OBF3 bit 1: [Setting condition] When the slave writes to ODR3 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 642 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU37 DBU36 DBU35 DBU34 C/D3 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data Flag When the host writes to IDR3, bit 2 of the I/O address is written into this bit to indicate whether IDR3 contains data or a command. 0: Content of input data register (IDR3) is a data 1: Content of input data register (IDR3) is a command 2 1 DBU32 IBF3 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR3 1: [Setting condition] When the host writes to IDR3 in I/O write cycle 0 OBF3 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * When the host reads ODR3 in I/O read cycle When the slave writes 0 to the OBF3 bit Defined by User The user can use these bits as necessary. 1: [Setting condition] When the slave writes to ODR3 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 643 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) * STR4 R/W Bit 7 6 5 4 3 Bit Name Initial Value Slave Host Description DBU47 DBU46 DBU45 DBU44 C/D4 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Command/Data Flag When the host writes to IDR4, bit 2 of the I/O address is written into this bit to indicate whether IDR4 contains data or a command. 0: Content of input data register (IDR4) is a data 1: Content of input data register (IDR4) is a command 2 1 DBU42 IBF4 0 0 R/W R R R Defined by User The user can use this bit as necessary. Input Buffer Full This bit is an internal interrupt source to the slave (this LSI). 0: [Clearing condition] When the slave reads IDR4 1: [Setting condition] When the host writes to IDR4 in I/O write cycle 0 OBF4 0 R/(W)* R Output Buffer Full 0: [Clearing conditions] * * When the host reads ODR4 in I/O read cycle When the slave writes 0 to the OBF3 bit Defined by User The user can use these bits as necessary. 1: [Setting condition] When the slave writes to ODR4 Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 644 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.13 SERIRQ Control Register 0 (SIRQCR0) SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit 7 Bit Name Initial Value Slave Host Description Q/C 0 R Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame). 0: Continuous mode [Clearing conditions] * * LPC hardware reset, LPC software reset Specification by SERIRQ transfer cycle stop frame 1: Quiet mode [Setting condition] Specification by SERIRQ transfer cycle stop frame. 6 SELREQ 0 R/W Start Frame Initiation Request Select Selects the condition of a start frame initiation request when a host interrupt request is cleared in quiet mode. 0: Start frame initiation is requested when all interrupt requests are cleared 1: Start frame initiation is requested when one or more interrupt requests are cleared 5 IEDIR2 0 R/W Interrupt Enable Direct Mode 2 Selects whether an SERIRQ interrupt generation of LPC channel 2 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set Rev. 1.00 Apr. 28, 2008 Page 645 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 4 Bit Name Initial Value Slave Host Description SMIE3B 0 R/W Host SMI Interrupt Enable 3B Enables or disables an SMI interrupt request when OBF3B is set by a TWR15 write. 0: Host SMI interrupt request by OBF3B and SMIE3B is disabled [Clearing conditions] * * * Writing 0 to SMIE3B LPC hardware reset, LPC software reset Clearing OBF3B to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting OBF3B to 1 is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3B = 0 3 SMIE3A 0 R/W Host SMI Interrupt Enable 3A Enables or disables an SMI interrupt request when OBF3A is set by an ODR3 write. 0: Host SMI interrupt request by OBF3A and SMIE3A is disabled [Clearing conditions] * * * Writing 0 to SMIE3A LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) Host SMI interrupt request by setting is enabled [When IEDIR3 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE3A = 0 1: [When IEDIR3 = 0] 1: [When IEDIR3 = 0] Rev. 1.00 Apr. 28, 2008 Page 646 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 2 Bit Name Initial Value Slave Host Description SMIE2 0 R/W Host SMI Interrupt Enable 2 Enables or disables an SMI interrupt request when OBF2 is set by an ODR2 write. 0: Host SMI interrupt request by OBF2 and SMIE2 is disabled [Clearing conditions] * * * Writing 0 to SMIE2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) Host SMI interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE2 = 0 1 IRQ12E1 0 R/W Host IRQ12 Interrupt Enable 1 Enables or disables an HIRQ12 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ12E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: [When IEDIR2 = 0] 1: HIRQ12 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ12E1 = 0 Rev. 1.00 Apr. 28, 2008 Page 647 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 0 Bit Name Initial Value Slave Host Description IRQ1E1 0 R/W Host IRQ1 Interrupt Enable 1 Enables or disables a host HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] * * * Writing 0 to IRQ1E1 LPC hardware reset, LPC software reset Clearing OBF1 to 0 1: HIRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] Writing 1 after reading IRQ1E1 = 0 Rev. 1.00 Apr. 28, 2008 Page 648 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.14 SERIRQ Control Register 1 (SIRQCR1) SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. R/W Bit 7 Bit Name Initial Value Slave Host Description IRQ11E3 0 R/W Host IRQ11 Interrupt Enable 3 Enables or disables an HIRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ11 interrupt request by OBF3A and IRQE11E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ11 interrupt is requested [Setting condition] Writing 1 after reading IRQ11E3 = 0 6 IRQ10E3 0 R/W Host IRQ10 Interrupt Enable 3 Enables or disables an HIRQ10 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ10 interrupt request by OBF3A and IRQE10E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ10 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ10 interrupt is requested [Setting condition] Writing 1 after reading IRQ10E3 = 0 Rev. 1.00 Apr. 28, 2008 Page 649 of 994 REJ09B0452-0100 1: [When IEDIR3 = 0] 1: [When IEDIR3 = 0] Section 20 LPC Interface (LPC) R/W Bit 5 Bit Name Initial Value Slave Host Description IRQ9E3 0 R/W Host IRQ9 Interrupt Enable 3 Enables or disables an HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQE9E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ9 interrupt is requested [Setting condition] Writing 1 after reading IRQ9E3 = 0 4 IRQ6E3 0 R/W Host IRQ6 Interrupt Enable 3 Enables or disables an HIRQ6 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ6 interrupt request by OBF3A and IRQE6E3 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E3 LPC hardware reset, LPC software reset Clearing OBF3A to 0 (when IEDIR3 = 0) HIRQ6 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ6 interrupt is requested [Setting condition] Writing 1 after reading IRQ6E3 = 0 1: [When IEDIR3 = 0] 1: [When IEDIR3 = 0] Rev. 1.00 Apr. 28, 2008 Page 650 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 3 Bit Name Initial Value Slave Host Description IRQ11E2 0 R/W Host IRQ11 Interrupt Enable 2 Enables or disables an HIRQ11 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQE11E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ11 interrupt is requested [Setting condition] Writing 1 after reading IRQ11E2 = 0 2 IRQ10E2 0 R/W Host IRQ10 Interrupt Enable 2 Enables or disables an HIRQ10 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ10 interrupt request by OBF2 and IRQE10E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ10 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ10 interrupt is requested [Setting condition] Writing 1 after reading IRQ10E2 = 0 1: [When IEDIR2 = 0] 1: [When IEDIR2 = 0] Rev. 1.00 Apr. 28, 2008 Page 651 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description IRQ9E2 0 R/W Host IRQ9 Interrupt Enable 2 Enables or disables an HIRQ9 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQE9E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ9 interrupt is requested [Setting condition] Writing 1 after reading IRQ9E2 = 0 0 IRQ6E2 0 R/W Host IRQ6 Interrupt Enable 2 Enables or disables an HIRQ6 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ6 interrupt request by OBF2 and IRQE6E2 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E2 LPC hardware reset, LPC software reset Clearing OBF2 to 0 (when IEDIR2 = 0) HIRQ6 interrupt request by setting OBF2 to 1 is enabled [When IEDIR2 = 1] HIRQ6 interrupt is requested [Setting condition] Writing 1 after reading IRQ6E2 = 0 1: [When IEDIR2 = 0] 1: [When IEDIR2 = 0] Rev. 1.00 Apr. 28, 2008 Page 652 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.15 SERIRQ Control Register 2 (SIRQCR2) SIRQCR2 contains bits that enable or disable SERIRQ interrupt requests and select the host interrupt request outputs. R/W Bit 7 Bit Name Initial Value Slave Host Description IEDIR3 0 R/W Interrupt Enable Direct Mode 3 Selects whether an SERIRQ interrupt generation of LPC channel 3 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set 6 IEDIR4 0 R/W Interrupt Enable Direct Mode 4 Selects whether an SERIRQ interrupt generation of LPC channel 4 is affected only by a host interrupt enable bit or by an OBF flag in addition to the enable bit. 0: A host interrupt is generated when both the enable bit and the corresponding OBF flag are set 1: A host interrupt is generated when the enable bit is set Rev. 1.00 Apr. 28, 2008 Page 653 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 5 Bit Name Initial Value Slave Host Description IRQ11E4 0 R/W Host IRQ11 Interrupt Enable 4 Enables or disables an HIRQ11 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ11 interrupt request by OBF4 and IRQE11E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ11E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ11 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ11 interrupt is requested [Setting condition] Writing 1 after reading IRQ11E4 = 0 4 IRQ10E4 0 R/W Host IRQ10 Interrupt Enable 4 Enables or disables an HIRQ10 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ10 interrupt request by OBF4 and IRQE10E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ10E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ10 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ10 interrupt is requested [Setting condition] Writing 1 after reading IRQ10E4 = 0 1: [When IEDIR4 = 0] 1: [When IEDIR4 = 0] Rev. 1.00 Apr. 28, 2008 Page 654 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 3 Bit Name Initial Value Slave Host Description IRQ9E4 0 R/W Host IRQ9 Interrupt Enable 4 Enables or disables an HIRQ9 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ9 interrupt request by OBF4 and IRQE9E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ9E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ9 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ9 interrupt is requested [Setting condition] Writing 1 after reading IRQ9E4 = 0 2 IRQ6E4 0 R/W Host IRQ6 Interrupt Enable 4 Enables or disables an HIRQ6 interrupt request when OBF4 is set by an ODR4 write. 0: HIRQ6 interrupt request by OBF4 and IRQE6E4 is disabled [Clearing conditions] * * * Writing 0 to IRQ6E4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) HIRQ6 interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] HIRQ6 interrupt is requested [Setting condition] Writing 1 after reading IRQ6E4 = 0 1: [When IEDIR4 = 0] 1: [When IEDIR4 = 0] Rev. 1.00 Apr. 28, 2008 Page 655 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) R/W Bit 1 Bit Name Initial Value Slave Host Description SMIE4 0 R/W Host SMI Interrupt Enable 4 Enables or disables an SMI interrupt request when OBF4 is set by an ODR4 write. 0: Host SMI interrupt request by OBF4 and SMIE4 is disabled [Clearing conditions] * * * Writing 0 to SMIE4 LPC hardware reset, LPC software reset Clearing OBF4 to 0 (when IEDIR4 = 0) Host SMI interrupt request by setting OBF4 to 1 is enabled [When IEDIR4 = 1] Host SMI interrupt is requested [Setting condition] Writing 1 after reading SMIE4 = 0 0 0 R/W Reserved The initial value should not be changed. 1: [When IEDIR4 = 0] 20.3.16 SERIRQ Control Register 3 (SIRQCR3) SIRQCR3 contains bits that select the host interrupt request outputs. Initial Value 0 0 0 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W Host IRQ Interrupt Select These bits select the state of the output on the SERIRQ pins. 0: SERIRQ pin output is in the Hi-Z state 1: SERIRQ pin output is low Bit 7 6 5 4 3 2 1 0 Bit Name SELIRQ15 SELIRQ14 SELIRQ13 SELIRQ8 SELIRQ7 SELIRQ5 SELIRQ4 SELIRQ3 Rev. 1.00 Apr. 28, 2008 Page 656 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.17 SERIRQ Control Register 4 (SIRQCR4) SIRQCR4 is used to select the SERIRQ interrupt requests of the SCIF. Initial Value All 0 0 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W Reserved The initial value should not be changed. 3 2 1 0 SCSIRQ3 SCSIRQ2 SCSIRQ1 SCSIRQ0 SCIF SERIRQ Request These bits select host interrupt requests of the SCIF. 0000: No host interrupt request 0001: HIRQ1 0010: SMI 0011: HIRQ3 0100: HIRQ4 0101: HIRQ5 0110: HIRQ6 0111: HIRQ7 1000: HIRQ8 1001: HIRQ9 1010: HIRQ10 1011: HIRQ11 1100: HIRQ12 1101: HIRQ13 1110: HIRQ14 1111: HIRQ15 Bit Bit Name 7 to 4 Rev. 1.00 Apr. 28, 2008 Page 657 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) SCIFADR sets the host addresses of the SCIF. Do not change the contents of SCIFADR during operation of the SCIF (i.e. while SCIFE is set to 1). * SCIFADRH Initial Value 0 0 0 0 0 0 1 1 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W SCIF Addresses 15 to 8 These bits set the host addresses of the SCIF. Bit 7 6 5 4 3 2 1 0 Bit Name * SCIFADRL Initial Value 1 1 1 1 1 0 0 0 R/W Slave Host Description R/W R/W R/W R/W R/W R/W R/W R/W SCIF Addresses 7 to 0 These bits set the host addresses of the SCIF. Bit 7 6 5 4 3 2 1 0 Bit Name Note: When the SCIF is in use, set different addresses in the SCIFADR for channels 1, 2, 3, and 4. Rev. 1.00 Apr. 28, 2008 Page 658 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.3.19 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and selects the output of the host interrupt request signal of each frame. Initial Value 0 R/W Slave Host Description R/W Status Register 3 Selection Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. For details of STR3, see section 20.3.12, Status Registers 1 to 4 (STR1 to STR4). 0: Bits 7 to 4 in STR3 indicate processing status of the LPC interface. 1: [When TWRE = 1] Bits 7 to 4 in STR3 indicate processing status of the LPC interface. [When TWRE = 0] Bits 7 to 4 in STR3 are readable/writable bits which user can use as necessary 6 5 4 3 2 1 0 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6 SELSMI SELIRQ12 SELIRQ1 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W Host IRQ Interrupt Select These bits select the state of the output on the SERIRQ pins. 0: [When host interrupt request is cleared] SERIRQ pin output is in the Hi-Z state [When host interrupt request is set] SERIRQ pin output is low 1: [When host interrupt request is cleared] SERIRQ pin output is low [When host interrupt request is set] SERIRQ pin output is in the Hi-Z state. Bit 7 Bit Name SELSTR3 Rev. 1.00 Apr. 28, 2008 Page 659 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.4 20.4.1 Operation LPC interface Activation The LPC interface is activated by setting one of the following bits to 1: LPC3E to LPC1E in HICR0 and LPC4E in HICR4. When the LPC interface is activated, the related I/O ports (P37 to P30, P83 and P82) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (P81, P80, PB0, and PB1) to the LPC interface's input/output pins. Use the following procedure to activate the LPC interface after a reset release. 1. Read the signal line status and confirm that the LPC module can be connected. Also check that the LPC module is initialized internally. 2. When using channels 1, 2 and 4, set LADR1, LADR2, and LADR4 to determine the I/O address. 3. When using channel 3, set LADR3 to determine the I/O address and whether bidirectional data registers are to be used. 4. Set the enable bit (LPC4E to LPC1E) for the channel to be used. 5. Set the enable bits (FGA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be used. 6. Set the selection bits for other functions (SDWNE, IEDIR). 7. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF, and OBEI). Read IDR or TWR15 to clear IBF. 8. Set receive complete interrupt enable bits (IBFIE4 to IBFIE1, ERRIE, and OBEI) as necessary. Rev. 1.00 Apr. 28, 2008 Page 660 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.4.2 LPC I/O Cycles There are 12 types of LPC transfer cycle: LPC memory read, LPC memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, bus master I/O write, FW memory read, and FW memory write. Of these, the LPC of this LSI supports I/O read and I/O write. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of the LPC transfer cycle has been requested. In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the following order, in synchronization with LCLK. The host can be made to wait by sending back a value other than B'0000 in the slave's synchronization return cycle, but with the LPC of this LSI a value of B'0000 always returns. If the received address matches the host address in an LPC register (IDR, ODR, STR, and TWR), the LPC interface enters the busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle forced termination (abort), registers and flags are not changed. The timing of the LFRAME, LCLK, and LAD signals is shown in figures 20.2 and 20.3. Rev. 1.00 Apr. 28, 2008 Page 661 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.3 LPC I/O Cycle I/O Read Cycle State Count 1 2 3 4 5 6 7 8 9 10 11 12 13 Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Drive Source Host Host Host Host Host Host Value (3 to 0) 0000 0000 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 1111 ZZZZ 0000 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ Contents Start Cycle type/direction Address 1 Address 2 Address 3 Address 4 Data 1 Data 2 I/O Write Cycle Drive Source Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0010 Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 Bits 3 to 0 Bits 7 to 4 1111 ZZZZ 0000 1111 ZZZZ Turnaround (recovery) Host Turnaround Synchronization Data 1 Data 2 None Slave Slave Slave Turnaround (recovery) Host Turnaround Synchronization None Slave Turnaround (recovery) Slave Turnaround None Turnaround (recovery) Slave Turnaround None Rev. 1.00 Apr. 28, 2008 Page 662 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) LCLK LFRAME LAD3 to LAD0 Start Cycle type, direction, and size ADDR TAR Sync Data TAR Start Number of clocks 1 1 4 2 1 2 2 1 Figure 20.2 Typical LFRAME Timing LCLK LFRAME LAD3 to LAD0 Start Cycle type, direction, and size ADDR TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 20.3 Abort Mechanism Rev. 1.00 Apr. 28, 2008 Page 663 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.4.3 Gate A20 The Gate A20 signal can mask address A20 to emulate the address mode of the 8086* architecture CPU used in personal computers. Normally, the Gate A20 signal can be controlled by a firmware. The fast Gate A20 function that realizes high-seed performance by hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: An Intel microprocessor (1) Regular Gate A20 Operation Output of the Gate A20 signal can be controlled by an H'D1 command and data. When the slave (this LSI) receives data, it normally reads IDR1 in the interrupt handling routine activated by the IBFI1 interrupt. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it on pin GA20. (2) Fast Gate A20 Operation The internal state of pin GA20 is initialized to 1 since the initial value of the FGA20E bit is 0. When the FGA20E bit is set to 1, pin P81/GA20 functions as the output of the fast GA20 signal. The state of pin GA20 can be monitored by reading bit GA20 in HICR2. The initial output from this pin is 1, which is the initial value. Afterward, the host can manipulate the output from this pin by sending commands and data. This function is only available via the IDR1. The LPC decodes commands input from the host. When an H'D1 host command is detected, bit 1 of the data following the host command is output from pin GA20. This operation does not depend on firmware or interrupts, and is faster than the regular processing using interrupts. Table 20.4 shows the conditions that set and clear pin GA20. Figure 20.4 shows the GA20 output flow. Table 20.5 indicates the GA20 output signal values. Rev. 1.00 Apr. 28, 2008 Page 664 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.4 GA20 Setting/Clearing Timing Pin Name GA20 Setting Condition When bit 1 of the data that follows an H'D1 host command is 1 Clearing Condition When bit 1 of the data that follows an H'D1 host command is 0 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to the bit of GA20 in DR Figure 20.4 GA20 Output Rev. 1.00 Apr. 28, 2008 Page 665 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.5 Fast Gate A20 Output Signals Internal CPU Interrupt Flag (IBF) 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 GA20 (P81) Q 1 Q (1) Q 0 Q (0) Q 1 Q (1) Q 0 Q (0) Q Q Q Q Q 1/0 Q (1/0) Consecutively executed sequences Retriggered sequence Cancelled sequence Turn-off sequence (abbreviated form) Turn-on sequence (abbreviated form) Turn-off sequence C/D1 Data/Command 1 0 1 1 0 1 1 0 1/0 1 0 1/0 1 1 1 1 1 0 1 H'D1 command 1 data*1 H'FF command H'D1 command 0 data* 2 Remarks Turn-on sequence H'FF command H'D1 command 1 data* 1 Command other than H'FF and H'D1 H'D1 command 0 data* 2 Command other than H'FF and H'D1 H'D1 command Command other than H'D1 H'D1 command H'D1 command H'D1 command Any data H'D1 command Notes: 1. Any data with bit 1 set to 1. 2. Any data with bit 1 cleared to 0. Rev. 1.00 Apr. 28, 2008 Page 666 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.4.4 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC software shutdown state is controlled by the SDWNB bit. In both states, the LPC interface enters the reset state by itself, and is no longer affected by external signals other than the LRESET and LPCPD signals. Placing the slave in sleep mode or software standby mode is effective in reducing current dissipation in the shutdown state. If software standby mode is set, some means must be provided for exiting software standby mode before clearing the shutdown state with the LPCPD signal. If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown state cannot be cleared at the same time as the rising edge of the LPCPD signal. Taking these points into consideration, the following operating procedure uses a combination of LPC software shutdown and LPC hardware shutdown. 1. Clear the SDWNE bit to 0. 2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag. 3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal status flags and perform any necessary processing. 4. Set the SDWNB bit to 1 to set LPC software standby mode. 5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB bit is cleared automatically. 6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1. 7. If software standby mode has been set, exit software standby mode by some means independent of the LPC. 8. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared to 0. If the slave has been placed in sleep mode, the mode is exited by means of LRESET signal input, on completion of the LPC transfer cycle, or by some other means. Rev. 1.00 Apr. 28, 2008 Page 667 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.6 shows the scope of the LPC interface pin shutdown. Table 20.6 Scope of LPC Interface Pin Shutdown Abbreviation LAD3 to LAD0 LFRAME LRESET LCLK SERIRQ LSCI LSMI PME GA20 CLKRUN LPCPD Port P33 to P30 P34 P35 P36 P37 PB1 PB0 P80 P81 P82 P83 Scope of Shutdown O O X O O O X I/O I/O Input Input Input I/O I/O I/O I/O I/O Input Input Notes Hi-Z Hi-Z LPC hardware reset function is active Hi-Z Hi-Z Hi-Z, only when LSCIE = 1 Hi-Z, only when LSMIE = 1 Hi-Z, only when PMEE = 1 Hi-Z, only when FGA20E = 1 Hi-Z Needed to clear shutdown state [Legend] O: Pin that is shutdown by the shutdown function : Pin that is shutdown only when the LPC function is selected by register setting X: Pin that is not shutdown In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order of priority of LPC shutdown and reset states is as follows. 1. System reset (reset by RES pin input, or WDT overflow) All register bits, including bits LPC4E to LPC1E, are initialized. 2. LPC hardware reset (reset by LRESET pin input) LRSTB, SDWNE, and SDWNB bits are cleared to 0. 3. LPC software reset (reset by LRSTB) SDWNE and SDWNB bits are cleared to 0. 4. LPC hardware shutdown SDWNB bit is cleared to 0. 5. LPC software shutdown The scope of the initialization in each mode is shown in table 20.7. Rev. 1.00 Apr. 28, 2008 Page 668 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.7 Scope of Initialization in Each LPC interface Mode Items Initialized LPC transfer cycle sequencer (internal state), LPCBSY and ABRT flags SERIRQ transfer cycle sequencer (internal state), CLKREQ and IRQBSY flags System Reset Initialized Initialized LPC Reset Initialized Initialized Initialized LPC Shutdown Initialized Initialized Retained LPC interface flags Initialized (IBF1, IBF2, IBF3A, IBF3B, IBF4, MWMF, C/D1, C/D2, C/D3, C/D4, OBF1, OBF2, OBF3A, OBF3B, OBF4, SWMF, DBU), GA20 (internal state) Host interrupt enable bits Initialized (IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, SMIE4, IRQ6E4, IRQ9E4 to IRQ11E4, IEDIR2 to IEDIR4), Q/C flag LRST flag SDWN flag LRSTB bit SDWNB bit SDWNE bit Initialized Retained Initialized (0) Can be set/cleared Can be set/cleared Initialized (0) Initialized (0) Can be set/cleared Initialized (0) HR: 0 SR: 1 0 (can be set) Initialized (0) Initialized (0) HS: 0 SS: 1 Initialized (0) Initialized (0) HS: 1 SS: 0 or 1 Retained Retained Initialized LPC interface operation control bits (LPC4E to LPC1E, FGA20E, LADR1 to LADR4, IBFIE1 to IBFIE4, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, OBEIE, SCIFE, IDR1 to IDR4, ODR1 to ODR4, TWR0 to TWR15, SCSIRQ0 to SCSIRQ3, and SCIFADRH/L) LRESET signal LPCPD signal LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals PME, LSMI, LSCI, GA20 signals (when function is selected) PME, LSMI, LSCI, GA20 signals (when function is not selected) Input (port function Input Input Input Output Input Input Hi-Z Hi-Z Port function Port function Note: System reset: Reset by RES pin input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS) Rev. 1.00 Apr. 28, 2008 Page 669 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Figure 20.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3 to LAD0 LFRAME At least 30 s At least 100 s At least 60 s LRESET Figure 20.5 Power-Down State Termination Timing Rev. 1.00 Apr. 28, 2008 Page 670 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 20.6. SL or H LCLK SERIRQ Drive source IRQ1 START Host controller None IRQ1 None Start frame H R T IRQ0 frame S R T IRQ1 frame S R T IRQ2 frame S R T H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample IRQ14 frame S LCLK SERIRQ Driver None R T IRQ15 frame S R T IOCHCK frame S R T I Stop frame H R T Next cycle STOP IRQ15 None Host controller START H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle Figure 20.6 SERIRQ Timing The serialized interrupt transfer cycle frame configuration is as follows. Two of the states comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The recover state must be driven by the host or slave that was driving the preceding state. Rev. 1.00 Apr. 28, 2008 Page 671 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.8 Serialized Interrupt Transfer Cycle Frame Configuration Serial Interrupt Transfer Cycle Frame Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Contents Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK Stop Drive Source Slave Host Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Host Number of States 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Undefined First, 1 or more idle states, then 2 or 3 states 0-driven by host 2 states: Quiet mode next 3 states: Continuous mode next Drive possible in LPC channel 1 and SCIF Drive possible in LPC channels 2, 3, 4, and SCIF Drive possible in SCIF Drive possible in SCIF Drive possible in SCIF Drive possible in LPC channels 2, 3, 4, and SCIF Drive possible in SCIF Drive possible in SCIF Drive possible in LPC channels 2, 3, 4, and SCIF Drive possible in LPC channels 2, 3, 4, and SCIF Drive possible in LPC channels 2, 3, 4, and SCIF Drive possible in LPC channel 1 and SCIF Drive possible in SCIF Drive possible in SCIF Drive possible in SCIF Notes In quiet mode only, slave drive possible in first state, then next 3 states 0-driven by host Rev. 1.00 Apr. 28, 2008 Page 672 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) There are two modescontinuous mode and quiet modefor serialized interrupts. The mode initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer cycle that ended before that cycle. In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet mode, the slave with interrupt sources requiring a request can also initiate an interrupt transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-down state. In order for a slave to transfer an interrupt request in this case, a request to restart the clock must first be issued to the host. For details see section 20.4.6, LPC Interface Clock Start Request. 20.4.6 LPC Interface Clock Start Request A request to restart the clock (LCLK) can be sent to the host by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 20.7. LCLK 1 2 3 4 5 6 CLKRUN Pull-up enable Driven by the slave processor Driven by the host processor Figure 20.7 Clock Start Request Timing Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a different protocol, using the PME signal, etc. 20.4.7 SCIF Control from LPC Interface Setting the SCIFE bit in HICR5 to 1 allows the LPC host to communicate with the SCIF. Then, the LPC interface can access the registers of the module SCIF other than SCIFCR. For details on transmission and reception, see section 17, Serial Communication Interface with FIFO (SCIF). Rev. 1.00 Apr. 28, 2008 Page 673 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.5 20.5.1 Interrupt Sources IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. The LMCI and LMCUI interrupts are command receive complete interrupts. OBEI is an output buffer empty interrupt. An interrupt request is enabled by setting the corresponding enable bit. Table 20.9 Receive Complete Interrupts and Error Interrupt Interrupt IBFI1 IBFI2 IBFI3 IBFI4 OBEI ERRI Description When IBFIE1 is set to 1 and IDR1 reception is completed When IBFIE2 is set to 1 and IDR2 reception is completed When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and IBFIE3 are set to 1 and reception is completed up to TWR15 When IBFIE4 is set to 1 and IDR4 reception is completed When OBEIE is set to 1 with OBEI set to 1. When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1 Rev. 1.00 Apr. 28, 2008 Page 674 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9, HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF. HIRQ3, HIRQ4, HIRQ5, HIRQ7, HIRQ8, HIRQ13, HIRQ14, and HIRQ15 are only for the SCIF. There are two ways of clearing a host interrupt request when the LPC channels are used. When the IEDIR bit in SIRQCR is cleared to 0, host interrupt sources and LPC channels are all linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt enable bit is automatically cleared to 0, and the host interrupt request is cleared. When the IEDIR bit is set to 1 in SIRQCR, a host interrupt is requested by the only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore, SMIE1, SMIE2, SMIE3A and SMIE3B, SMIE4, IRQ6En, IRQ9En, IRQ10En, and IRQ11En lose their respective functional differences. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. (n = 2 to 4.) When the SCIF channels are used, clearing the DDCD bit in FMSR of the SCIF clears a host interrupt request. Table 20.10 summarizes the methods of setting and clearing these bits when the LPC channels are used, and table 20.11 summarizes the methods of setting and clearing these bits when the SCIF channels are used. Figure 20.8 shows the processing flowchart. Rev. 1.00 Apr. 28, 2008 Page 675 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.10 HIRQ Setting and Clearing Conditions when LPC Channels are Used Host Interrupt HIRQ1 HIRQ12 SMI (IEDIR2 = 0, IEDIR3 = 0, or IEDIR4 = 0) Setting Condition Clearing Condition Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit IRQ1E1, from bit IRQ1E1 and writes 1 or host reads ODR1 Internal CPU writes to ODR1, then reads 0 Internal CPU writes 0 to bit from bit IRQ12E1 and writes 1 IRQ12E1, or host reads ODR1 Internal CPU * * * * writes to ODR2, then reads 0 from bit SMIE2 and writes 1 writes to ODR3, then reads 0 from bit SMIE3A and writes 1 Internal CPU * * writes 0 to bit SMIE2, or host reads ODR2 writes 0 to bit SMIE3A, or host reads ODR3 writes 0 to bit SMIE3B, or host reads TWR15 writes 0 to bit SMIE4, or host reads ODR4 writes 0 to bit SMIE2 writes 0 to bit SMIE3A writes 0 to bit SMIE3B writes 0 to bit SMIE4 writes 0 to bit IRQiE2, or host reads ODR2 CPU writes 0 to bit IRQiE3, or host reads ODR3 CPU writes 0 to bit IRQiE4, or host reads ODR4 writes 0 to bit IRQiE2 writes 0 to bit IRQiE3 writes 0 to bit IRQiE4 writes to TWR15, then reads 0 from bit * SMIE3B and writes 1 writes to ODR4, then reads 0 from bit SMIE4 and writes 1 reads 0 from bit SMIE2, then writes 1 * SMI (IEDIR2 = 1, IEDIR3 = 1, or IEDIR4 = 1) Internal CPU * * * * Internal CPU * reads 0 from bit SMIE3A, then writes 1 * reads 0 from bit SMIE3B, then writes 1 * reads 0 from bit SMIE4, then writes 1 * * * * HIRQi Internal CPU (i = 6, 9, 10, 11) * writes to ODR2, then reads 0 from bit (IEDIR2 = 0, IRQiE2 and writes 1 IEDIR3 = 0, or * writes to ODR3, then reads 0 from bit IEDIR4 = 0) IRQiE3 and writes 1 * HIRQi (i = 6, 9, 10, 11) (IEDIR2 = 1, IEDIR3 = 1, or IEDIR4 = 1) writes to ODR4, then reads 0 from bit IRQiE4 and writes 1 reads 0 from bit IRQiE2, then writes 1 reads 0 from bit IRQiE3, then writes 1 reads 0 from bit IRQiE4, then writes 1 Internal CPU Internal CPU * * * Internal CPU * * * Rev. 1.00 Apr. 28, 2008 Page 676 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used Host Interrupt HIRQi (i = 1 to 15) Setting Condition Internal CPU sets the corresponding SERIRQ host interrupt request for the SCIF in SIRQCR4 (for details, see the description of SIRQCR4). Changes in the SCIF input signal DCD are detected. Clearing Condition Reads FMSR and clears the DDCD bit in FMSR Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 SERIRQ IRQ1 output SERIRQ IRQ1 source clear Interrupt initiation ODR1 read OBF1 = 0? No Yes All bytes transferred? Hardware operation Yes Software operation No Figure 20.8 HIRQ Flowchart (Example of Channel 1) Rev. 1.00 Apr. 28, 2008 Page 677 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) 20.6 20.6.1 Usage Note Data Conflict The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid data conflict. For example, if the host and slave both try to access IDR or ODR at the same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to data for which writing has finished. Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to TWR15 has been obtained. Table 20.12 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3, TWR0MW, TWR0SW, and TWR1 to TWR15. Rev. 1.00 Apr. 28, 2008 Page 678 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Table 20.12 Host Address Example Register IDR3 ODR3 STR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0 H'A24A and H'A24E H'A24A H'A24E H'A250 H'A250 H'A251 H'A252 H'A253 H'A254 H'A255 H'A256 H'A257 H'A258 H'A259 H'A25A H'A25B H'A25C H'A25D H'A25E H'A25F H'3FD0 and H'3FD4 H'3FD0 H'3FD4 H'3FC0 H'3FC0 H'3FC1 H'3FC2 H'3FC3 H'3FC4 H'3FC5 H'3FC6 H'3FC7 H'3FC8 H'3FC9 H'3FCA H'3FCB H'3FCC H'3FCD H'3FCE H'3FCF Rev. 1.00 Apr. 28, 2008 Page 679 of 994 REJ09B0452-0100 Section 20 LPC Interface (LPC) Rev. 1.00 Apr. 28, 2008 Page 680 of 994 REJ09B0452-0100 Section 21 FSI Interface Section 21 FSI Interface This LSI incorporates the SPI flash memory serial interface (FSI) that supports the communication between this LSI and SPI flash memory. The FSI performs communications using the LPC or CPU of this LSI as a master. 21.1 Features Figure 21.1 shows a block diagram of the FSI. * * * * * * * * * * Supports communications between this LSI and SPI flash memory. Can operate as a master. Transfer clock selectable from system clock or LCLK. Four interrupt sources: Transmit end, receive data full, and command and write receive interrupts Direct transfer between LPC and SPI: Supports Read instruction, and Byte/Page-Program, and AAI-Program instructions. LPC-SPI command transfer: Supports instructions other than above. Supports LPC/FW memory cycles of the LPC interface. Supports byte, word, and longword transfers of FW memory cycles. Provides independent LPC communication enable bits Supports LPC reset and LPC shut-down. Rev. 1.00 Apr. 28, 2008 Page 681 of 994 REJ09B0452-0100 Section 21 FSI Interface FSICMDI, FSIWI FSICR1/2 SLCR FSIHBARH/L FSISR LCLK LAD 3 to 0 LFRAME LPC I/F FSITEI, FSIRXI FSIBNR FSISTR FSIINS FS FSIRDINS FSIPPINS Address-Change CMDHBRH/L FSILSTR1/2 FSIGPR1 to F FSIARLH/M/L FSIWDHH/HL/LH/LL FSICMDR FSITDR 0 to 7 FSIRDR Trans/Rev Controller FSISS FSICK FSISFR FSIDO FSIDI [Legend] FSISFR: FSI shift register Figure 21.1 FSI Block Diagram Rev. 1.00 Apr. 28, 2008 Page 682 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.2 Input/Output Pins Table 21.1 shows the input/output pins of the FSI. Table 21.1 Pin Configuration Pin Name FSI slave select FSI clock FSI master data input FSI master data output Symbol FSISS FSICK FSIDI FSIDO I/O Output Output Input Output Function FSI slave select signal FSI clock signal FSI data input signal FSI address/direction/data output signal For details on the input/output pins of the LPC interface, see section 20.2, Input/Output Pins. Table 21.2 shows the initial state of the FSI input/output pins when the FSIE bit in the FSICR1 register is set to 1. Table 21.2 Initial State of FSI Pins (when FSIE = 1) Pin Name FSI slave select FSI clock FSI master data input FSI master data output Symbol FSISS FSICK FSIDI FSIDO Pin State When FSIE is Set to 1 Outputs high level. Outputs high level or low level depending on CPHS and CPOS. Inputs data. Outputs high level. Rev. 1.00 Apr. 28, 2008 Page 683 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3 Register Description The FSI consists of the following registers. Table 21.3 List of Register Addresses R/W Register Name FSI control register 1 FSI control register 2 FSI byte count register FSI instruction register FSI read instruction register FSI program instruction register FSI status register FSI transmit data register 0 FSI transmit data register 1 FSI transmit data register 2 FSI transmit data register 3 FSI transmit data register 4 FSI transmit data register 5 FSI transmit data register 6 FSI transmit data register 7 FSI receive data register FSI access host base address register H FSI access host base address register L FSI flash memory size register FSI command host base address register H FSI command host base address register L FSI command register FSILPC command status register 1 Abbreviation FSICR1 FSICR2 FSIBNR FSIINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR FSIHBARH FSIHBARL FSISR CMDHBARH CMDHBARL FSICMDR FSILSTR1 EC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W Host R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FC90 H'FC91 H'FC92 H'FC93 H'FC94 H'FC95 H'FC96 H'FC98 H'FC99 H'FC9A H'FC9B H'FC9C H'FC9D H'FC9E H'FC9F H'FCA0 H'FC50 H'FC51 H'FC52 H'FC53 H'FC54 H'FC55 H'FC56 Rev. 1.00 Apr. 28, 2008 Page 684 of 994 REJ09B0452-0100 Section 21 FSI Interface R/W Register Name FSI general-purpose register 1 FSI general-purpose register 2 FSI general-purpose register 3 FSI general-purpose register 4 FSI general-purpose register 5 FSI general-purpose register 6 FSI general-purpose register 7 FSI general-purpose register 8 FSI general-purpose register 9 FSI general-purpose register A FSI general-purpose register B FSI general-purpose register C FSI general-purpose register D FSI general-purpose register E FSI general-purpose register F FSILPC control register FSI address register H FSI address register M FSI address register L FSI write data register HH FSI write data register HL FSI write data register LH FSI write data register LL FSI LPC command register 2 Note: Abbreviation FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL FSIWDRHH FSIWDRHL FSIWDRLH FSIWDRLL FSILSTR2 EC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W Host R R R R R R R R R R R R R R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'01 Address H'FC57 H'FC58 H'FC59 H'FC5A H'FC5B H'FC5C H'FC5D H'FC5E H'FC5F H'FC60 H'FC61 H'FC62 H'FC63 H'FC64 H'FC65 H'FC66 H'FC67 H'FC68 H'FC69 H'FC6A H'FC6B H'FC6C H'FC6D H'FC6E 1. Before accessing these registers, clear bit 0 in MSTPCRL (MSTP0) and bit 2 in MSTPCRA (MSTPA2) to 0. 2. "R/W" in table 21.3 has the following meanings. a) "R/W EC" indicates the access from the EC (Embedded Controller = this LSI). b) "R/W Host" indicates the access from the host. Rev. 1.00 Apr. 28, 2008 Page 685 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.1 FSI Control Register 1 (FSICR1) The FSICR1 control bits are classified into three functionalities: resetting the FSI internal signals, enabling/disabling FSI functions, and selecting FSI functions. Initial Value 0 R/W EC R/W Host Description Software Reset Controls initialization of the FSI internal sequencer. 0: Normal state 1: Clears the internal sequencer. Writing 1 to this bit generates a clear signal for the sequencer in the corresponding module, resulting in the initialization of the FSI's internal state. 6 FSIE 0 R/W FSI Enable 0: Disables FSI operation. 1: Enables FSI operation. The following shows the initial state of the FSI pins when FSIE is set to 1: FSISS: Outputs high level. FSICK: Outputs high level or low level depending on DPHS and CPOS. FSIDO: Outputs high level. FSIDI: Inputs data. 5 FRDE 0 R/W Fast-Read Enable 0: The FSI is in normal read operation mode. 1: The FSI is in fast-read operation mode. 4 AAIE 0 R/W AAI (Auto Address Increment) Program Enable 0: The FSI performs byte-program operation. 1: The FSI performs AAI program operation. Bit 7 Bit Name SRES Rev. 1.00 Apr. 28, 2008 Page 686 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit 3 2 Bit Name CPHS CPOS Initial Value 0 0 R/W EC R/W R/W Host Description CPHS: Selects the polarity of the FSICK clock. CPOS: Selects the phase of the FSICK clock. CPHS 0 CPOS 0 Initial value of FSICK: Low level Data changes at the FSICK falling edge. 1 1 Initial value of FSICK: High level Data changes at the FSICK falling edge. 0 1 1 0 Setting prohibited Setting prohibited 1 0 CKSEL All 0 0 R/W R/W Reserved The initial value should not be modified. Clock select 0: Selects the system clock for FSICK 1: Selects LCLK for FSICK Note: Before selecting LCLK for FSICK, clear the CPHS and CPOS bits of FSICR1 to 0. Rev. 1.00 Apr. 28, 2008 Page 687 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.2 FSI Control Register 2 (FSICR2) The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI communications and enabling/disabling the FSI internal interrupts. Initial Value 0 R/W EC R/W Host Description FSI Transmit Enable Controls FSI transmission and indicates transmission status in combination with the LFBUSY bit. 0: FSI transmission wait state [Clearing condition] When FSI data transmission is completed. 1: When LFBUSY = 0: Starts transmission. When LFBUSY = 1: FSI transmission is in progress (automatically set). 6 RE 0 R/W FSI Reception Enable Controls FSI reception and indicates reception status in combination with the LFBUSY bit. 0: FSI reception wait state [Clearing condition] When FSI data reception is completed. 1: When LFBUSY = 0: Starts reception. When LFBUSY = 1: FSI reception is in progress (automatically set). 5 FSITEIE 0 R/W FSI Transmit End Interrupt Enable 0: Disables the FSITEI interrupt request. 1: Enables the FSITEI interrupt request. 4 FSIRXIE 0 R/W FSI Receive Interrupt Enable 0: Disables the FSIRXI interrupt request. 1: Enables the FSIRXI interrupt request. 3 to 0 All 0 R/W Reserved The initial value should not be modified. Bit 7 Bit Name TE Rev. 1.00 Apr. 28, 2008 Page 688 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.3 FSI Byte Count Register (FSIBNR) The FSIBNR sets the number of bytes to be transmitted or received by the FSI. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. Initial Value 0 0 0 0 R/W EC R/W Host Description Transmit Byte Count 3-0 These bits specify the number of data bytes to be transmitted. The TBN value is decremented each time one byte of FSI data transmission is completed. When the FSI transmission ends, TBN is cleared to B'0000. 0000: Transmits no data 0001: Transmits one byte of data 0010: Transmits two bytes of data 0011: Transmits three bytes of data 0100: Transmits four bytes of data 0101: Transmits five bytes of data 0110: Transmits six bytes of data 0111: Transmits seven bytes of data 1000: Transmits eight bytes of data 1001 to 1111: Setting prohibited If transmission of nine bytes or more is specified, data in FSITDR7 is transmitted. 3 0 R/W Reserved The initial value should not be modified. Bit Bit Name 7 to 4 TBN3 TBN2 TBN1 TBN0 Rev. 1.00 Apr. 28, 2008 Page 689 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit Bit Name Initial Value 0 0 0 R/W EC R/W Host Description Receive Byte Count 2-0 These bits specify the number of data bytes to be received. After the FSI reception operation ends (when FSIRXI in FSISTR is 1), the RBN value is decremented (-1) each time FSIRDR is read. When all the data bytes have been received, RBN is cleared to B'000. 000: Receives no data 001: Receives one byte of data 010: Receives two bytes of data 011: Receives three bytes of data 100: Receives four bytes of data 101 to 111: Setting prohibited If reception of five bytes or more is specified, FSIRDR is overwritten. 2 to 0 RBN2 RBN1 RBN0 21.3.4 FSI Instruction Register (FSIINS) FSIINS sets an instruction to be sent to the SPI flash memory during command transfer. When LFBUSY is 1, a write to this register by the EC (this LSI) is invalid. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. Initial Value R/W EC R/W Host Description These bits store an instruction to be transmitted to the SPI flash memory. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 Rev. 1.00 Apr. 28, 2008 Page 690 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.5 FSI Instruction Register (FSIRDINS) FSIRDINS sets a read operation instruction to be sent to FSITDR during read operation. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be modified during initialization. Initial Value R/W EC R/W Host Description These bits store a read operation instruction. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.6 FSI Program Instruction Register (FSIPPINS) FSIPPINS sets a program operation instruction to be sent to FSITDR during program operation. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be modified during initialization. Initial Value R/W EC R/W Host Description These bits store a program operation instruction. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.7 FSI Status Register (FSISTR) FSISTR indicates the processing status of the EC (this LSI) and the SPI flash memory transfer. Initial Value 0 R/W EC Host Description FSI Transmit End Interrupt Flag [Setting condition] When write data has been transmitted to the SPI flash memory. [Clearing condition] When this bit is read as 1 and then written with 0. Bit 7 Bit Name FSITEI R/(W)* Rev. 1.00 Apr. 28, 2008 Page 691 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit 6 Bit Name OBF Initial Value 0 R/W EC R Host Description Transmit Data Register Full Indicates whether or not there is data to be written by the EC (this LSI). 0: There is no write data. [Clearing condition] When write data transmission to the SPI flash memory is completed. 1: There is write data. [Setting condition] When the TE bit is set to 1. 5 FSIRXI 0 R FSI Receive End Interrupt Flag Indicates whether or not there is data to be read by the EC (this LSI). 0: There is no read data. [Clearing condition] * * LFBUSY = 0: When all receive data has been read by the EC (when RBN is cleared to 0). LFBUSY = 1: When all receive data has been I/Oread by the host (automatically cleared). 1: There is read data. [Setting condition] When receive data has been transferred to FSIRDR. 4 to 0 Note: * All 0 R/W Reserved The initial value should not be modified. Only 0 can be written to bit 7 to clear it. Rev. 1.00 Apr. 28, 2008 Page 692 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7) FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the SPI flash memory. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should not be set in the processing other than FSICMDI and FSIWI interrupt processing. Initial Value R/W EC R/W Host Description These bits store transmit data. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.9 FSI Receive Data Register (FSIRDR) FSIRDR stores a total of 4 bytes of receive data items continuously sent from the SPI flash memory. This register should not be read in the processing other than FSICMDI interrupt processing. Note that four bytes of receive registers share a single register address. A register to be read will be determined according to the RBN bits in FSIBNR. When RBN = B'000, H'00 is read out. Initial Value R/W EC R Host Description These bits store receive data. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 Rev. 1.00 Apr. 28, 2008 Page 693 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL) FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to convert the host address to the SPI flash memory address. The input range of the host address will be determined based on the host start address set in these registers and the memory size set in FSISR. If a host address to be input is out of the determined range, Sync will not be returned. If FW memory cycle is used, bit 31 to bit 28 in FSIHBARH is set as IDSEL. During FSI operation (in the state where FSIE or FSILIE is set), do not change the setting in this register. * FSIHBARH Initial Value All 0 R/W EC R/W Host Description These bits specify bits [31:24] of the host start address. Bit Bit Name 7 to 0 bit 31 to bit 24 * FSIHBARL Initial Value All 0 R/W EC R/W Host Description These bits specify bits [23:16] of the host start address. The settings by bit 19 to bit 16 do not affect the operation. Bit Bit Name 7 to 0 bit 23 to bit 16 21.3.11 FSI Flash Memory Size Register (FSISR) FSISR sets the size of SPI flash memory. The host input address range will be determined based on the size set in this register. Note that the host input address should not be greater than the SPI flash memory capacity. During FSI operation (in the state where FSIE or FSILIE is set), do not change the setting in this register. Rev. 1.00 Apr. 28, 2008 Page 694 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit Bit Name Initial Value All 0 0 0 R/W EC R/W R/W R/W Host Description Reserved The initial value should not be changed. These bits specify the SPI flash memory size. 00: 1 MB 01: 2 MB 10: 4 MB 11: 8 MB 7 to 2 1 0 FSIMS1 FSIMS0 21.3.12 FSI Command Host Base Address Registers H and L (CMDHBARH and CMDHBARL) CMDHBARH and CMDHBARL set the upper 16 bits of the host start address which is necessary to set a command address. The lower 16 bits of the host start address range from H'F000 to H'F00F. If a host address to be input to CMDHBARH and CMDHBARL is out of the determined range, Sync will not be returned. If FW memory cycle is used, bit 31 to bit 28 in CMDHBARH is set as IDSEL. During FSI operation (in the state where FSIE or FSILIE is set), do not change the setting in this register. * CMDHBARH Initial Value All 0 R/W EC R/W Host Description These bits specify bits [31:24] of the host start address. Bit Bit Name 7 to 0 bit 31 to bit 24 * CMDHBARL Initial Value All 0 R/W EC R/W Host Description These bits specify bits [23:16] of the host start address. Bit Bit Name 7 to 0 bit 23 to bit 16 Rev. 1.00 Apr. 28, 2008 Page 695 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.13 FSI Command Register (FSICMDR) FSICMDR stores command data during FSI command reception. FSICMDR stores command data when the FSICMDI bit in FSILSTR1 is cleared to 0. It does not store command data when the FSICMDI bit is set to 1. Initial Value R/W EC R Host Description These bits store an FSI command. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.14 FSI LPC Command Status Register 1 (FSILSTR1) FSILSTR1 indicates the LPC internal status. Initial Value R/W EC Host Description FSI Command Busy Flag 0: The FSI command execution is completed. [Clearing condition] * When this bit is read as 1 and then written with 0. 1: The FSI command execution is in progress. [Setting condition] * 6 FSICMDI 0 R/W* R When an FSI command is received. FSI Command Interrupt Flag 0:The FSI command interrupt processing is completed. [Clearing condition] * When this bit is read as 1 and then written with 0. 1: The FSI command interrupt processing is in progress. [Setting condition] * When an FSI command is received. Bit 7 Bit Name CMDBUSY 0 R/W* R Rev. 1.00 Apr. 28, 2008 Page 696 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit 5 Bit Name FSIDMYE Initial Value 0 R/W EC R/W Host Description R FSI Dummy Enable 0: Disables FSI dummy. 1: Enables FSI dummy. 4 FSIWBUSY 0 R/W* R FSI Write Busy Flag 0: FSI write transfer is completed. [Clearing condition] * When this bit is read as 1 and then written with 0. 1: FSI write in transferring [Setting condition] * SPI flash memory write is received when FLDCT=0. 3 FSIWI 0 R/W* R FSI Write Interrupt Flag 0: FSI write interrupt is completed. [Clearing condition] * Read FSIWI=1 and then write 0. 1: FSI write interrupt is in progress. [Setting condition] * SPI flash memory write is received when FLDCT=0. 2 FLBUSY 0 R R LPC-SPI Direct Transfer Busy Flag Indicates an LPC-SPI direct transfer status. 0: Direct transfer is completed. 1: During direct transfer 1, 0 Note: * All 0 R/W R Reserved The initial value should not be modified. Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 697 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.15 FSI LPC Command Status Register 2 (FSILSTR2) FSILSTR2 indicates the LPC internal status. Initial Value All 0 0 R/W EC R/W R Host Description Reserved The initial value should not be modified. 4 FSIDWBUSY FSI Direct Write Busy Flag Indicates a FSI write transfer status during LPCSPI direct transfer. 0: FSI write transfer is completed. 1: During FSI write transfer 3 FSIDRBUSY 0 R FSI Direct Read Busy Flag Indicates a FSI read transfer status during LPCSPI direct transfer. 0: FSI read transfer is completed. 1: During FSI read transfer 2 to 0 SIZE2 SIZE1 SIZE0 0 0 1 R R R Transfer Byte Count Monitor Indicates the number of transferred bytes when data is received in the LPC/FW memory cycles. When the Byte/Page-Program or AAI-Program instruction is executed from the EC CPU, the number of transferred bytes can be confirmed by these bits. 001: LPC/FW memory cycle (byte transfer) 010: FW memory cycle (word transfer) 100: FW memory cycle transfer (longword transfer) When a transfer is made in units other than byte/word/longword, the previous value is retained. Note: This bit is not set to the value other than above. Bit Bit Name 7 to 5 Rev. 1.00 Apr. 28, 2008 Page 698 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) FSIGPR1 to FSIGPRF store data such as the result of FSI command interrupt processing. * FSIGPR1 to FSIGPRF Initial Value R/W EC R/W Host Description R These bits store results of FSI command interrupt processing. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.17 FSI LPC Control Register (SLCR) SLCR enables or disables the LPC host interface function of the FSI, FSI interrupt enable bit, and FSI operation mode control bit. R/W EC R/W Host Description FSI LPC Interface Enable Enables or disables the LPC host interface function of the FSI. When disabled, address-matching is not performed and Sync is not returned. 0: Disables the LPC host interface function. 1: Enables the LPC host interface function. 6 FSICMDIE 0 R/W FSI Command Interrupt Enable 0: Disables the FSI command interrupt. 1: Enables the FSI command interrupt. 5 FSIWIE 0 R/W FSI Write Interrupt Enable 0: Disables the FSI write interrupt. 1: Enables the FSI write interrupt. Bit 7 Bit Name FSILIE Initial Value 0 Rev. 1.00 Apr. 28, 2008 Page 699 of 994 REJ09B0452-0100 Section 21 FSI Interface Bit 4 Bit Name FLDCT Initial Value 0 R/W EC R/W Host Description FSI LPC Direct Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: LPC-SPI indirect transfer 1: LPC-SPI direct transfer 3 FLWAIT 0 R/W FSI LPC Wait Selects access mode in SPI flash memory write. For details, see section 21.4.6, SPI Flash Memory Write Operation Mode. 0: No wait cycle is inserted. 1: Wait cycles can be inserted. 2 to 0 All 0 R/W Reserved The initial value should not be modified. 21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL) FSIAR stores an SPI flash memory address. If the host address matches FSIHBAR, the FSIAR value is updated. FSIAR value is not updated by command access. * FSIARH Initial Value All 0 R/W EC R Host Description These bits store bits [23:16] of the SPI flash memory address. Bit Bit Name 7 to 0 bit 23 to bit 16 * FSIARM Initial Value All 0 R/W EC R Host Description These bits store bits [15:8] of the SPI flash memory address. Bit Bit Name 7 to 0 bit 15 to bit 8 Rev. 1.00 Apr. 28, 2008 Page 700 of 994 REJ09B0452-0100 Section 21 FSI Interface * FSIARL Initial Value R/W EC R Host Description These bits store bits [7:0] of the SPI flash memory address. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL) FSIWDR stores data to be written to the SPI flash memory. If the host address matches FSIHBAR during LPC/FW memory write cycle, the FSIWDR value will be updated. FSIHBAR value is not updated by command access. * FSIWDRHH Initial Value All 0 R/W EC R Host Description These bits store bits [31:24] of the SPI flash memory write data Bit Bit Name 7 to 0 bit 31 to bit 24 * FSIWDRHL Initial Value All 0 R/W EC R Host Description These bits store bits [23:16] of the SPI flash memory write data. Bit Bit Name 7 to 0 bit 23 to bit 16 Rev. 1.00 Apr. 28, 2008 Page 701 of 994 REJ09B0452-0100 Section 21 FSI Interface * FSIWDRLH Initial Value All 0 R/W EC R Host Description These bits store bits [15:8] of the SPI flash memory write data. Bit Bit Name 7 to 0 bit 15 to bit 8 * FSIWDRLL Initial Value R/W EC R Host Description These bits store bits [7:0] of the SPI flash memory write data. Bit Bit Name 7 to 0 bit 7 to bit 0 All 0 Rev. 1.00 Apr. 28, 2008 Page 702 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.4 21.4.1 Operation LPC/FW Memory Cycles In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0 synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error occurrence; while the FSI in this LSI always returns B'0000 (Ready) or B'0110 (Long wait). The FSI becomes busy if the received address matches an address in the host accessible range set in the registers (FSIHBARH, FSIHBARL, FSISR, and CMDHBAR), and outputs a turn-around signal to return to the idle state. Table 21.4 LPC Memory Read/Write Cycles State Counts Content 1 2 3 4 5 6 7 8 9 10 11 12 13 Start Cycle type/ direction Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Turn-around (recovery) Turn-around Wait* LPC Memory Read Cycles Driven by Host Host Host Host Host Host Host Host Host Host Host None Slave Value (3 to 0) 0000 0100 bit 31 to bit 28 bit 27 to bit 24 bit 23 to bit 20 bit 19 to bit 16 bit 15 to bit 12 bit 11 to bit 8 bit 7 to bit 4 bit 3 to bit 0 1111 ZZZZ 0110 LPC Memory Write Cycles Content Start Cycle type/ direction Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Data 1 Data 2 Turn-around (recovery) Driven by Host Host Host Host Host Host Host Host Host Host Host Host Host Value (3 to 0) 0000 0110 bit 31 to bit 28 bit 27 to bit 24 bit 23 to bit 20 bit 19 to bit 16 bit 15 to bit 12 bit 11 to bit 8 bit 7 to bit 4 bit 3 to bit 0 bit 3 to bit 0 bit 7 to bit 4 1111 Rev. 1.00 Apr. 28, 2008 Page 703 of 994 REJ09B0452-0100 Section 21 FSI Interface LPC Memory Read Cycles State Counts Content Driven by Value (3 to 0) 14 15 16 17 18 Note: * Synchronization LPC Memory Write Cycles Content Turn-around Wait* Synchronization Driven by None Slave Slave Slave None Value (3 to 0) ZZZZ 0110 0000 1111 ZZZZ Slave Slave Slave Slave None 0000 bit 3 to bit 0 bit 7 to bit 4 1111 ZZZZ Data 1 Data 2 Turn-around (recovery) Turn-around Turn-around (recovery) Turn-around The number of wait cycles depends on the system. Table 21.5 FW Memory Read/Write Cycles (Byte Transfer) State Counts Content 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Start FW Memory Read Cycles Driven by Host Value (3 to 0) 1101 ID3 to ID0 bit 27 to bit 24 bit 23 to bit 20 bit 19 to bit 16 bit 15 to bit 12 bit 11 to bit 8 bit 7 to bit 4 bit 3 to bit 0 0000 1111 ZZZZ 0110 0000 bit 3 to bit 0 bit 7 to bit 4 Content Start FW Memory Write Cycles Driven by Host Value (3 to 0) 1110 ID3 to ID0 bit 27 to bit 24 bit 23 to bit 20 bit 19 to bit 16 bit 15 to bit 12 bit 11 to bit 8 bit 7 to bit 4 bit 3 to bit 0 0000 bit 3 to bit 0 bit 7 to bit 4 1111 ZZZZ 0110 0000 Device select Host Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Size Turn-around (recovery) Turn-around Wait* Synchronization Device select Host Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Size Data 1 Data 2 Turn-around (recovery) Turn-around Wait* Synchronization Host Host Host Host Host Host Host Host Host None Slave Slave Slave Slave Host Host Host Host Host Host Host Host Host Host Host None Slave Slave Data 1 Data 2 Rev. 1.00 Apr. 28, 2008 Page 704 of 994 REJ09B0452-0100 Section 21 FSI Interface State Counts Content 17 18 Note: * FW Memory Read Cycles Driven by Slave None Value (3 to 0) 1111 ZZZZ FW Memory Write Cycles Content Turn-around (recovery) Turn-around Driven by Slave None Value (3 to 0) 1111 ZZZZ Turn-around (recovery) Turn-around The number of wait cycles depends on the system clock. The FSI supports byte, word, and longword transfers of FW memory read and write cycles. In word transfer, the least address bit is fixed to B'0; while in longword transfer, the lower 2 bits are fixed to B'00. When longword transfers of FW memory write cycles are used, the maximum operating frequency of the system clock is 10 MHz. 21.4.2 SPI Flash Memory Transfer The SPI flash memory transfer is performed using FSIDO and FSIDI synchronously with FSICK. The initial value of FSICK can be either fixed to high or low through programming. FSISS FSICK FSIDO FSIDI Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB LSB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB LSB Figure 21.2 Example of SPI Flash Memory Transfer Rev. 1.00 Apr. 28, 2008 Page 705 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.4.3 Flash Memory Instructions Table 21.6 lists the flash memory instructions (INS). Table 21.6 List of Instructions (INS) Instruction Name WREN WRDI RDSR WRSR READ Fast-Read Byte-Program Page-Program AAI-Program Sector-Erase Block-Erase Chip/Bulk-Erase RDID EWSR DP (DEEP POWER DOWN) RES Description Sets write-enable Resets write-enable Reads status register Writes status register Reads SPI flash memory Fast-reads SPI flash memory Byte-programs SPI flash memory Page-programs SPI flash memory Address auto increment program Sector erasure Block erasure Chip/bulk erasure Reads manufacturing ID and product ID Enables status register write Deep power-down Releases deep power-down Rev. 1.00 Apr. 28, 2008 Page 706 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI) The FSI supports direct transfer between the host and SPI flash memory. If the host address input in LPC/FW memory write cycle matches the host address set in FSIHBARH, FSIHBARL, or FSISR, the FSI memory cycle starts. In LPC/FW memory write cycle, the FSI supports three types of instructions: Byte/Page-Program instructions and AAI-Program instruction. In LPC/FW memory read cycle, the FSI supports two types of instructions: Read instruction and Fast-Read instruction. In the case that LPC-SPI direct transfer is selected in Byte-Program, Page-Program, or AAI-Program instruction execution, set FLDCT of SLCR to 1. The FSI reads the data with LPCSPI direct transfer regardless of the status of FLDCT in Read and Fast-Read instruction execution. (1) FSI Address Conversion The host address can be converted into the SPI flash memory address by setting FSIHBARH, FSIHBARL, and FSISR. The host address space ranges from H'0000_0000 to H'FFFF_FFFF. The SPI flash memory address space ranges from H'00_0000 to H'FF_FFFF. Figure 21.3 shows an example of the FSI memory address conversion. FSIHBAR: H'231F FSISR: H'00 (1 MB) SPI flash memory H'231F_0000* H'00_0000 1 MB 1MB 1 MB H'232E_FFFF Host addresses SPI addresses H'0F_FFFF Note: * The upper 16 bits of the host address are set to the value in the FSIHBAR register. Figure 21.3 FSI Address Conversion Example As shown in figure 21.3, if an address ranging from H'231F_0000 to H'232E_FFFF is accessed in LPC/FW memory write cycle, the SPI flash memory is accessed. If a host address to be input is out of the determined range, Sync will not be returned. During an SPI flash memory access, a long wait cycle will be inserted to the LPC bus cycle. In an LPC memory cycle, one-byte transfer is enabled. In an FW memory cycle, a byte, word, and a longword transfer are enabled. Rev. 1.00 Apr. 28, 2008 Page 707 of 994 REJ09B0452-0100 Section 21 FSI Interface (2) Byte/Page-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively. Then, the SPI flash memory address, the write data, and the Byte/Page-Program instruction which is stored in FSIPPINS in advance are transferred to FSITDR. After SYNC (long wait) has been returned, the TE bit in FSICR2 is set, starting the Byte/Page-Program instruction execution. When the transmission has been completed, SYNC (Ready) and TAR are returned to the host. To execute the Byte-Program instruction, byte transfer access in LPC memory write cycle or FW memory write cycle should be performed. Figure 21.4 shows an example of data transfer to FSITDR. Figure 21.5 shows the Page-Program instruction execution timing. FSIWDR[31:0] H'67_45_23_01 FSIWDR[31:24] FSIWDR[23:16] FSIWDR[15:8] FSIWDR[7:0] H'67 H'45 H'23 H'01 H'70 H'4A H'06 H'02 FSITDR0 FSITDR7 FSITDR6 FSIAR[23:0] H'06_4A_70 FSIPPINS[7:0] H'02 FSIAR[7:0] FSIAR[15:8] FSIAR[23:16] FSIDO FSISFR Figure 21.4 Data Transfer to FSITDR (Example) Rev. 1.00 Apr. 28, 2008 Page 708 of 994 REJ09B0452-0100 Section 21 FSI Interface LCLK LFRAME LAD[3:0] ST CT ADDR DATA TAR WAIT SY TAR FSIAR[23:0] FSIWDR[31:0] FSIPPINS[7:0] FSICR2 TE bit FSITDR7 to FSITDR0 FSISTR OBF bit H'67-45-23-01-70-4A-06-02 H'02 H'06-4A-70 H'67-45-23-01 FSISS FSICK (CPOS = CPHS = 0) FSIDO H'02->06->4A->70->01->23->45->67 Figure 21.5 Page-Program Instruction Execution Timing Rev. 1.00 Apr. 28, 2008 Page 709 of 994 REJ09B0452-0100 Section 21 FSI Interface (3) AAI-Program Instruction If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR, respectively. Then, the flash memory address, write data, and the AAI-Program instruction which is stored in FSI hardware in advance are transferred to FSITDR. After SYNC (long wait) has been returned, the transmit enable signal TE is set, and AAI-Program instruction execution starts. In the first byte, the instruction, address, and data in this order are transmitted to the SPI flash memory. In the second and the following bytes, an instruction and data in this order are transmitted to the SPI flash memory. When the transmission has been completed, SYNC (Ready) and TAR are returned to the host. To execute the AAI-Program instruction, byte transfer access in LPC memory write cycle or FW memory write cycle should be performed. To return to the AAI-Program instruction (first byte), clear the AAIE bit once or perform initialization of the FSI internal sequencer in SRES of FSICR1. After the Read instruction or the LPC-SPI command is transferred during the AAI-Program instruction execution, the FSI internal sequencer is initialized to return to the AAI-Program Instruction (first byte). Figures 21.6 and 21.7 show AAI-Program execution timings. LCLK LFRAME LAD[3:0] ST CT ADDR DATA TAR WAIT SY TAR FSIAR[23:0] FSIWDR[31:0] FSICR2 TE bit FSITDR7 to FSITDR0 FSISTR OBF bit H'01-70-4A-06-AF H'06-4A-70 H'01 FSISS FSICK (CPOS = CPHS = 0) FSIDO H'AF->06->4A->70->01 Figure 21.6 AAI-Program Instruction Execution Timing (First Byte) Rev. 1.00 Apr. 28, 2008 Page 710 of 994 REJ09B0452-0100 Section 21 FSI Interface LCLK LFRAME LAD[3:0] CT ADDR DATA TAR WAIT SY TAR FSIAR[23:0] FSIWDR[31:0] FSICR2 TE bit FSITDR7 to FSITDR0 FSISTR OBF bit H'23-AF H'06-4A-70 H'23 FSISS FSICK (CPOS = CPHS =0) FSIDO H'AF->23 Figure 21.7 AAI-Program Instruction Execution Timing (Second and Following Bytes) (4) Read Instructions If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI flash memory address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has been returned, the RE bit in FSICR2 is set, and Read instruction execution starts. The read data is then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready), read data, and TAR are returned to the host. Figure 21.8 shows an example of data transfer to FSIRDR. Figure 21.9 shows the Read instruction execution timing. Rev. 1.00 Apr. 28, 2008 Page 711 of 994 REJ09B0452-0100 Section 21 FSI Interface Internal register H'67_45_23_01 First receive data H'01 FSIRDR3 Second receive data H'23 Third receive data Fourth receive data H'45 H'67 FSIRDR0 FSIAR[23:0] H'06_4A_70 FSIRDINS[7:0] H'03 FSIAR[7:0] FSIAR[15:8] FSIAR[23:16] H'70 H'4A H'06 H'03 FSITDR3 FSITDR0 FSIDI FSISFR FSIDO Figure 21.8 Data Transfer to FSIRDR (Example) LCLK LFRAME LAD[3:0] ST CT ADDR TAR WAIT SY DATA TAR FSIAR[23:0] FSIRDINS[7:0] FSICR2 RE bit FSITDR7 to FSITDR0 FSISTR FSIRXI bit FSIRDR3 to FSIRDR0 H'01->23->45->67 H'70-4A-06-03 H'03 H'06-4A-70 FSISS FSICK (CPOS = CPHS =0) FSIDO FSIDI H'02->06->4A->70 H'01->23->45->67 Figure 21.9 Read Instruction Execution Timing Rev. 1.00 Apr. 28, 2008 Page 712 of 994 REJ09B0452-0100 Section 21 FSI Interface (5) Fast-Read Instruction If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is set to 1, the host address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has been returned, the RE bit in FSICR2 is set, and Fast-Read instruction execution starts. The read data is then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready), read data, and TAR are returned to the host. Figure 21.10 shows the Fast-Read Instruction Execution Timing. LCLK LFRAME LAD[3:0] ST CT ADDR TAR WAIT ST DATA TAR FSIAR[23:0] FSIRDINS[7:0] FSICR2 RE bit FSITDR7 to FSITDR0 FSISTR FSIRXI bit FSIRDR3 to FSIRDR0 H'01-23-45-67 H'70-4A-06-03 H'06-4A-70 H'0B FSISS FSICK (CPOS = CPHS =0) FSIDO FSIDI H'02->06->4A->70->Dummy H'01->23->45->67 Figure 21.10 Fast-Read Instruction Execution Timing Rev. 1.00 Apr. 28, 2008 Page 713 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer) The FSI supports instructions other than Byte/Page-Program instructions, AAI-Program instruction, Read instruction, and Fast-Read instruction by using an LPC-SPI command transfer. (1) FSI Command Space Specific host address space can be used as FSI command space according to the CMDHBAR settings. Figure 21.11 shows an example of FSI command space settings. CMDHBAR: H'EFFF H'EFFF_0000 H'EFFF_F000 CMD0 CMD1 CMD0 CMD1 H'EFFF_F00F CMDE CMDF CMDE CMDF H'EFFF_FFFF Host addresses FSI command area Note: * The upper 16 bits of the host address are set to the value in the CMDHBAR register. Figure 21.11 FSI Command Space Settings (Example) As shown in figure 21.11, a host address ranging from H'EFFF_F000 to H'EFFF_F00F is used as the FSI command space while the CMDHBAR register is set to H'EFFF. Rev. 1.00 Apr. 28, 2008 Page 714 of 994 REJ09B0452-0100 Section 21 FSI Interface (2) FSI Command Write If an LPC/FW memory write cycle for the FSI command space occurs, the FSI performs the FSIFLASH command write operation. Figure 21.12 shows an example of FSI Command write operation. CMDHBAR: H'EFFF H'EFFF_0000* FSICMDR[7:0] H'EFFF_F000 CMD0 CMD1 Command data (H'00 to H'FF) FSICMDI H'EFFF_F00F CMDE CMDF B'0 B'1 B'1 Interrupt requests FSICMDIE H'EFFF_FFFF Host address CMDBUSY B'0 B'1 Note: * The upper 16 bits of the host address are set to the value in the CMDHBAR register. Figure 21.12 FSI Command Write Operation (Example) As shown in figure 21.12, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is accessed in LPC/FW memory write cycle while the CMDHBAR register is set to H'EFFF, the write data is stored in FSICMDR, and then the CMDBUSY and FSICMDI flags in FSILSTR1 are set to 1. In this case, an interrupt is requested according to the FSICMDIE state. Sync is not returned if the host address to be input is out of the determined range. In FSI command write, no wait cycle will be inserted to the LPC bus cycle. If the CMDBUSY flag is set to 1, Sync is not returned during the operations other than FSI command read. Rev. 1.00 Apr. 28, 2008 Page 715 of 994 REJ09B0452-0100 Section 21 FSI Interface (3) FSI Command Read Figure 21.13 shows an example of FSI command read. CMDHBAR: H'EFFF H'EFFF_0000 H'EFFF_F000 CMD0 CMD1 FSILSTR1 FSIGPR1 FSIGPR2 to D H'EFFF_F00F CMDE CMDF FSIGPRE FSIGPRF H'EFFF_FFFF Host address Note: * The upper 16 bits of the host address are set to the value in the CMDHBAR register. Figure 21.13 FSI Command Read (Example) As shown in figure 21.13, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is accessed in LPC/FW memory read cycle while the CMDHBAR register is set to H'EFFF, the FSILSTR1 or data in FSIGPR1 to FSIGPRF is returned. Sync is not returned if the host address to be input is out of the determined range. In FSI command read, no wait cycle will be inserted to the LPC bus cycle. Before reading the FSIGPR, ensure that the CMDBUSY bit in FSILSTR1 has been cleared to 0. Rev. 1.00 Apr. 28, 2008 Page 716 of 994 REJ09B0452-0100 Section 21 FSI Interface (4) FSI Dummy Write Figure 21.14 shows an example of FSI dummy write. FSI Dummy Write FSIHBAR: H'231F FSISR: H'00 (1 MB) CMDHBAR: H'EFFF FSIDMYE B'1 FSIWDR[31:0] H'2325_4A76 H'73 Host address H'0000_0073 FSIAR[23:0] H'06_4A76 Byte-Program FSIDMYE B'0 SPI Flash memory FSIWDR[31:0] H'232E_1BC3 H'D4 Host address H'0000_00D4 FSIAR[23:0] H'0F_1BC3 H'D4 H'0F_1BC3 Flash memory address Figure 21.14 FSI Dummy Write (Example) As shown in figure 21.14, if an LPC/FW memory write cycle occurs while the FSIDMYE bit in FSILSTR1 is 1, the FSI does not access the SPI flash memory but stores the SPI flash memory address and write data in FSIAR and FSIWDR, respectively. Rev. 1.00 Apr. 28, 2008 Page 717 of 994 REJ09B0452-0100 Section 21 FSI Interface (5) FSI Command Usage Example 1 (SPI Flash Memory Erasure) The FSI commands enable the execution of several instructions for the SPI flash memory. Figure 21.15 shows an example of executing the SPI flash memory erasure instruction. FSIHBAR: H'231F FSISR: H'00 (1 MB) CMDHBAR: H'EFFF STEP1 H'EFFF_F000 CMD0 (H'10) Host address FSICMDR[7:0] Command data (H'10) FSICMDI B'0 B'1 FSIDMDIE B'1 FSIDMYE B'0 B'1 Interrupt requests STEP2 H'2325_4A76 Dummy data Host address FSIAR[23:0] H'06_4A76 FSIDMYE B'1 FSICMDR[7:0] Command data (H'11) STEP3 H'EFFF_F000 CMD0 (H'11) Host address FSICMDI B'0 B'1 FSICMDIE B'1 FSIDMYE B'1 B'0 Interrupt requests Figure 21.15 SPI Flash Memory Erasure (Example) In flash memory erasure, the SPI flash memory address is stored in FSIAR and an erasure instruction for the SPI flash memory is executed by an SPI command. The flash memory address storage in FSIAR is performed by writing data to the sector or block address to be erased via the host. To distinguish the SPI flash memory erasure from the SPI flash memory programming, the erasure is performed in the following sequence using the FSIDMYE. Rev. 1.00 Apr. 28, 2008 Page 718 of 994 REJ09B0452-0100 Section 21 FSI Interface STEP1 FSIDMYE FSICMDI CMDBUSY STEP2 STEP3 Written by the CPU Cleared by the CPU Cleared by the CPU Cleared by the CPU Cleared by the CPU Cleared by the CPU LPC_ADDR FSIAR[23:0] H'EFFF_F000 H'2325_4A76 H'06_4A76 H'EFFF_F000 TE TBN FSITDR3 to FSITDR1 FSIINS OBF FSITEI Written by the CPU Written by the CPU H'4 Written by the CPU H'76-4A-06 Written by the CPU H'52 Automatically cleared H'00 (Automatically cleared) Cleared by the CPU FSISS FSICK FSIDO H'52->76->4A-> 06 Figure 21.16 Execution Timing of SPI Flash Memory Step 1: 1. Write an erasure setting command (Host). 2. Generate an FSICMDI interrupt request. 3. Set the FSIDMYE bit in FSILSTR1 to 1 and clear the FSICMDI and CMDBUSY bits in FSILSTR1 to 0. 4. Complete the interrupt processing. 5. Check that the FSIDMYE bit in FSILSTR1 is set to 1 and that the CMDBUSY and FSICMDI bits in FSILSTR1 are cleared to 0 (Host). Step 2: 1. Perform a dummy write to the sector or block address to be erased (Host). 2. Store the SPI flash memory address and write data in the FSIAR register and FSIWDR register, respectively*. Note: * Use the data stored in FSIWDR if necessary on the user side. Step 3: 1. Write an erasure setting command (Host). 2. Generate an FSICMDI interrupt request. 3. Clear the FSICMDI bit in FSILSTR1 to 0. Rev. 1.00 Apr. 28, 2008 Page 719 of 994 REJ09B0452-0100 Section 21 FSI Interface 4. Execute the SPI flash memory erasure instruction. Set the TE bit in FSICR2 to 1. Set the TBN bit in FSIBNR to 4-byte transfer. Write the FSI address stored in FSIAR to FSITDR1 to FSITDR3. Write the erasure instruction to FSIINS (start the SPI flash memory erasure instruction execution). 5. Complete the interrupt processing. 6. Generate an FSITEI interrupt request. 7. Clear the FSIDMYE and CMDBUSY bits in FSILSTR1 to 0. 8. Complete the interrupt processing. 9. Check that the FSIDMYE, CMDBUSY, and FSICMDI bits in FSILSTR1 are cleared to 0 (Host). (6) FSI Command Usage Example 2 (SPI Flash Memory Status Read) Figure 21.17 shows an example of the execution timing of the SPI flash memory status read instruction. STEP1 FSIDMYE FSICMDI CMDBUSY Cleared by the CPU STEP2 STEP3 Cleared by the CPU LPC_ADDR H'EFFF_F000 RE TBN RBN FSIINS Written by the CPU Written by the CPU H'1 Written by the CPU H'1 Written by the CPU H'05 Automatically cleared H'00 (Automatically cleared) H'00 (Automatically cleared) FSIRXI Automatically cleared FSISS FSICK FSIDO FSIDI H'05 H'07 Figure 21.17 Execution Timing of SPI Flash Memory Status Read Instruction The SPI flash memory status read instruction is executed in the following sequence. Rev. 1.00 Apr. 28, 2008 Page 720 of 994 REJ09B0452-0100 Section 21 FSI Interface Step 1: 1. 2. 3. 4. Write a status read setting command (Host). Generate an FSICMDI interrupt request. Clear the FSICMDI bit in FSILSTR1 to 0. Check that the CMDBUSY bit in FSILSTR1 is set to 1 and that the FSICMDI bit in FSILSTR1 is cleared to 0 (Host). Step 2: 1. Perform the SPI flash memory status read instruction. Set the RE bit in FSICR2 to 1. Set the TBN bit in FSIBNR to 1-byte transfer and set the RBN bit in FSIBNR to 1-byte reception. Write the status read instruction to FSIINS (start the SPI flash memory status read instruction execution). 2. Complete the interrupt processing. Step 3: 1. 2. 3. 4. 5. 6. Generate an FSIRXI interrupt request. Write read data stored in FSIRDR to SPIGPR. Clear the CMDBUSY bit in FSILSTR1 to 0. Complete the interrupt processing Check that the CMDBUSY and FSICMDI bits in FSILSTR1 are cleared to 0 (Host). Read the SPI flash memory status from FSIGPR (Host). Rev. 1.00 Apr. 28, 2008 Page 721 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.4.6 SPI Flash Memory Write Operation Mode The write operation to the SPI flash memory in the LPC/FW memory write cycles can be classified into the following four operation modes, depending or the state of FLDCT and FLWAIT. Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles Operation Mode Mode 1 FLDCT 0 FLWAIT 0 Selected Register FSIWBUSY 1 FSIWI 1 Operation Control the write operation to the SPI flash memory by the EC CPU. No wait cycle is inserted to the LPC bus. Confirm by FSIWBUSY whether or not a write transfer has been completed. Control the write operation to the SPI flash memory by the EC CPU. Wait cycles are inserted to the LPC bus. Provision of wait cycles can be canceled by clearing FSIWBUSY. Control the write operation to the SPI flash memory by the FSI. No wait cycle is inserted to the LPC bus. Confirm by LFBUSY whether or not a write transfer has been completed. Control the write operation to the SPI flash memory by the FSI. Wait cycles are inserted to the LPC bus. Provision of wait cycles can be canceled by clearing LFBUSY. Mode 2 0 1 FSIWBUSY 1 FSIWI 1 Mode 3 1 0 LFBUSY 1 (Automatically cleared) Mode 4 1 1 LFBUSY 1 (Automatically cleared) Rev. 1.00 Apr. 28, 2008 Page 722 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.5 Reset Conditions The FSI supports the LPC shut-down mode. The range of initialization in each mode is shown in table 21.8. Table 21.8 Range of Initialization of FSI in Each Mode Register Name FSIHBARH/ FSIHBARL FSISR Bits 7 to 0 Bits 7 to 0 System Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized LPC Reset Retained Retained Retained Retained Initialized Retained Retained Initialized Retained Retained Retained Retained LPC Shutdown Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained LPC Abort Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained FSI Reset Retained Retained Retained Retained Initialized Retained Retained Initialized Retained Retained Retained Retained CMDHBARH/ Bits 7 to 0 CMDHBARL FSICMDR FSILSTR1 Bits 7 to 0 Bits 7, 6, 4, and 3 Bits 5 and 2 to 0 FSILSTR2 Bits 7 to 5 Bits 4 and 3 Bits 2 to 0 SPIGPR1 to SPIGPRF SLCR FSIARH/ FSIARM/ FSIARL FSIWDRHH/ FSIWDRHL/ FSIWDRLH/ FSIWDRLL Bits 7 to 0 Bits 7 to 0 Bits 7 to 0 Bits 7 to 0 Initialized Retained Retained Retained Retained LPC internal sequencer Initialized Initialized Initialized Initialized Retained Rev. 1.00 Apr. 28, 2008 Page 723 of 994 REJ09B0452-0100 Section 21 FSI Interface Register Name FSICR1 FSICR2 Bits 7 to 0 Bits 7 and 6 Bits 5 to 0 FSIBNR Bits 7 to 4 Bit 3 Bits 2 to 0 FSIINS FSIRDINS FSIPPINS FSISTR Bits 7 to 0 Bits 7 to 0 Bits 7 to 0 Bit 7 Bits 6 and 5 Bits 4 to 0 FSITDR7 to FSITDR0 FSIRDR Bits 7 to 0 Bits 7 to 0 System Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized LPC Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Retained Retained Retained Retained LPC Shutdown Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained LPC Abort Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained FSI Reset Retained Initialized Retained Initialized Retained Initialized Retained Retained Retained Initialized Initialized Retained Retained Retained Initialized FSI internal sequencer Rev. 1.00 Apr. 28, 2008 Page 724 of 994 REJ09B0452-0100 Section 21 FSI Interface 21.6 Interrupt Sources The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read transfer. FSICMDI is a command receive interrupt in host FSI command write. FSIWI is a write receive interrupt in the case of write from the host to the SPI flash memory. Setting the corresponding enable bit to 1 enables the relevant interrupt request to be issued. Table 21.9 FSI Interrupt Sources Interrupt Name FSII FSITEI FSIRXI LFSII FSICMDI FSIWI Interrupt Source Transmit end Receive data full FSI command reception FSI write reception Interrupt Enable Bit FSITEIE FSIRXIE FSICMDIE FSIWIE 21.7 21.7.1 Usage Note Longword Transfer in FW Memory Write Cycles When longword transfers of FW memory write cycles are used, the maximum operating frequency of the system clock is 10 MHz. Rev. 1.00 Apr. 28, 2008 Page 725 of 994 REJ09B0452-0100 Section 21 FSI Interface Rev. 1.00 Apr. 28, 2008 Page 726 of 994 REJ09B0452-0100 Section 22 A/D Converter Section 22 A/D Converter This LSI includes one unit (unit 0) of successive-approximation-type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. Figure 22.1 shows a block diagram for unit 0. 22.1 * * * * Features * * * * * 10-bit resolution Input channels: Sixteen channels Conversion cycle: 40 cycles (A/D conversion clock) Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on one to four channels or continuous A/D conversion on one to eight channels A/D conversion clocks specifiable (, /2, /4, or /8) Eight data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Three kinds of A/D conversion start Software Conversion start trigger from 16-bit timer pulse unit (TPU) or 8-bit timer (TMR) Interrupt source A/D conversion end interrupt (ADI) request can be generated Rev. 1.00 Apr. 28, 2008 Page 727 of 994 REJ09B0452-0100 Section 22 A/D Converter Module data bus Bus interface ADDRG ADDRC ADDRD ADDRH ADCSR ADDRA ADDRB ADDRE ADDRF Internal data bus AVCC AVref AVSS 10-bit D/A Successive approximation register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 + - Comparator Multiplexer ADCR /2 Control circuit /4 /8 Sample-andhold circuit ADI interrupt signal Conversion start trigger from TPU or 8-bit timer [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C ADDRD: ADDRE: ADDRF: ADDRG: ADDRH: A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H Figure 22.1 Block Diagram of A/D Converter Rev. 1.00 Apr. 28, 2008 Page 728 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.2 Input/Output Pins Table 22.1 summarizes the pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The AVref pin is a reference voltage pin for the A/D converter. The sixteen analog input pins are divided into two channel sets: analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0 and analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1. Table 22.1 Pin Configuration Pin Name Symbol I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Channel set 1 analog input Function Analog block power supply Analog block ground Reference voltage for A/D converter Channel set 0 analog input Analog power supply AVCC pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 AVSS AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Rev. 1.00 Apr. 28, 2008 Page 729 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.3 Register Descriptions The A/D converter has the following registers. Table 22.2 Register Configuration Register Name A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register Abbreviation ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR R/W R R R R R R R R R/W R/W Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC11 Data Bus Width 16 16 16 16 16 16 16 16 8 8 Rev. 1.00 Apr. 28, 2008 Page 730 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers which store a conversion result for each channel are shown in table 22.3. The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0. The data bus between the CPU and the A/D converter is sixteen bits wide. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Table 22.3 Analog Input Channels and Corresponding ADDR Analog Input Channel Channel Set 0 (CH3 = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 A/D Data Register to Store A/D Conversion Results ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH Rev. 1.00 Apr. 28, 2008 Page 731 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D converter operation. Bit 7 Bit Name ADF Initial Value R/W 0 Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all channels specified in scan mode [Clearing condition] When 0 is written after reading ADF = 1 6 5 ADIE ADST 0 0 R/W R/W A/D Interrupt Enable Enables ADI interrupt by ADF when this bit is set to 1. A/D Start When this bit is cleared to 0, A/D conversion stops and enters wait state. When this bit is set to 1 by a conversion start trigger from software, TPU, or TMR, A/D conversion starts. This bit remains set to 1 during A/D conversion. In single mode, this bit is automatically cleared to 0 when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by a reset, or software. 4 0 Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Apr. 28, 2008 Page 732 of 994 REJ09B0452-0100 Section 22 A/D Converter Bit 3 2 1 0 Bit Name CH3 CH2 CH1 CH0 Initial Value R/W 0 0 0 0 R/W R/W R/W R/W Description Channel Select 3 to 0 Select analog input channels with the SCANE and SCANS bits in ADCRS. The input channel setting must be made when conversion is halted (ADST = 0). When SCANE = 0 When SCANE = 1 and SCANS = X and SCANS = 0 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100: AN12 1101: AN13 1110: AN14 1111: AN15 0000: AN0 0001: AN0, AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4, AN5 0110: AN4 to AN6 0111: AN4 to AN7 1000: AN8 1001: AN8, AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: AN12 1101: AN12, AN13 When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0, AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1000: AN8 1001: AN8, AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: AN8 to AN12 1101: AN8 to AN13 1110: AN12 to AN14 1110: AN8 to AN14 1111: AN12 to AN15 1111: AN8 to AN15 [Legend] X: Don't care Note: * Only 0 can be written to clear the flag. Rev. 1.00 Apr. 28, 2008 Page 733 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit 7 6 Bit Name Initial Value R/W Description TRGS1 TRGS0 0 0 R/W Timer Trigger Select 1 and 0 R/W Enable the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by conversion trigger from TPU 10: A/D conversion start by conversion trigger from TMR 11: Setting prohibited 5 4 SCANE SCANS 0 0 R/W Scan Mode R/W Select the A/D conversion operating mode. 0X: Single mode 10: Scan mode Continuous A/D conversion on 1 to 4 channels 11: Scan mode Continuous A/D conversion on 1 to 8 channels 3 2 CKS1 CKS0 0 0 R/W Clock Select 1 and 0 R/W These bits select the clock (ADCLK)* used in A/D conversion. Set these bits while the ADST bit in ADCSR is 0, then set the conversion mode. 00: 01: /2 10: /4 00: /8 1 ADSTCLR 0 R/W A/D Start Clear Sets the automatic clearing of the ADST bit in scan mode. 0: Disables the automatic clearing of the ADST bit in scan mode 1: Automatically clears the bit when A/D conversion of all of the selected channels are completed 0 0 R Reserved This bit is always read as 0 and cannot be modified. [Legend] X: Don't care Note: * Set the clock so that ADCLK 10 MHz. Rev. 1.00 Apr. 28, 2008 Page 734 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. First, select the clock used in A/D conversion. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same time the operating mode or analog input channel is changed. 22.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by software, the TMR, or the TPU. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters wait state. When the ADST bit is cleared to 0 during A/D conversion, the conversion stops and the A/D converter enters wait state. Rev. 1.00 Apr. 28, 2008 Page 735 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.4.2 Scan Mode In scan mode, A/D conversion is performed sequentially on the specified channels (max. four channels or eight channels). Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by software, the TPU, or the TMR, A/D conversion starts on the first channel in the selected channel set. 2. Continuous A/D conversion on up to four channels (SCANE = 1 and SCANS = 0) or continuous A/D conversion on up to eight channels (SCANE = 1 and SCANS = 1) can be selected. When continuous A/D conversion on four channels is selected, A/D conversion starts from the following channels: AN0 when CH3 = 0 and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, AN8 when CH3 = 1 and CH2 = 0, and AN12 when CH3 = 1 and CH2 = 1. When continuous A/D conversion on eight channels is selected, A/D conversion starts from the following channels: AN0 when CH3 = 0 and CH2 = 0 and AN8 when CH3 = 1 and CH2 = 0. 3. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 4. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion from the first channel in the channel set starts again. 5. The ADST bit is not automatically cleared to 0 so steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. After this, setting the ADST bit to 1 starts A/D conversion from the first channel again. 6. When the ADST bit is automatically cleared on completion of the A/D conversion of all of the selected channels with the ADSTCLR bit in ADCR set to 1, A/D conversion stops and enters the wait state. Rev. 1.00 Apr. 28, 2008 Page 736 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 22.2 shows the A/D conversion timing. Table 22.4 indicates the A/D conversion time. As indicated in figure 22.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of write to ADCSR. The total conversion time therefore varies within the ranges indicated in table 22.4. In scan mode, the values shown in table 22.4 become those for the first conversion time. The second and subsequent conversion times are listed in table 22.5. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 22.2 A/D Conversion Timing Rev. 1.00 Apr. 28, 2008 Page 737 of 994 REJ09B0452-0100 Section 22 A/D Converter Table 22.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time CKS0 = 1 CKS1 = 1 CKS0 = 0 CKS0 = 1 Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tD tSPL tCONV (4) 44 15 (5) 45 (6) 8x 30 (9) 8x (10) 16x 60 (17) 16x (18) 32x 120 (33) 32x Note: Values in the table indicate the number of states. Table 22.5 A/D Conversion Time (Scan Mode) CKS1 0 0 1 1 CKS0 0 1 0 0 Conversion Time (State) 40 (fixed) 80 (fixed) 160 (fixed) 320 (fixed) Rev. 1.00 Apr. 28, 2008 Page 738 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. If the ADF bit in ADCSR has been set to 1 after A/D conversion ends and the ADIE bit is set to 1, an ADI interrupt request is enabled. Table 22.6 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF 22.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 22.3). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from the minimum voltage value B'00 0000 0000 (H'000) to B'00 0000 0001 (H'001) (see figure 22.4). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristics when the digital output changes from B'11 1111 1110 (H'3FE) to B'11 1111 1111 (H'3FF) (see figure 22.4). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 22.4). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 1.00 Apr. 28, 2008 Page 739 of 994 REJ09B0452-0100 Section 22 A/D Converter Digital output H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 22.3 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 22.4 A/D Conversion Accuracy Definitions Rev. 1.00 Apr. 28, 2008 Page 740 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.7 22.7.1 Usage Notes Module Stop Mode Setting The A/D converter operation can be enabled or disabled using the module stop control register. With the initial setting, the A/D converter is stopped. Register access is enabled by canceling module stop mode. For details, see section 26, Power-Down Modes. 22.7.2 Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/s or greater) (see figure 22.5). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. This LSI Sensor output impedance Up to 5 k Sensor input Low-pass filter C Up to 0.1 F Cin = 10 pF A/D converter equivalent circuit 10 k 20 pF Figure 22.5 Example of Analog Input Circuit Rev. 1.00 Apr. 28, 2008 Page 741 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect the absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board, so acting as antennas. 22.7.4 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pins (AN0 to AN15) during A/D conversion should be in the range AVss ANn AVref (n = 0 to 15). * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc = Vcc 0.3 V and AVss = Vss. If the A/D converter is not used, set AVcc = Vcc and AVss = Vss. * AVref pin range The reference voltage of the AVref pin should be in the range AVref AVcc. 22.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input pins (AN0 to AN15), analog reference voltage (AVref), and analog power supply voltage (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. Rev. 1.00 Apr. 28, 2008 Page 742 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage of the analog input pins (AN0 to AN15) and analog reference voltage pin (AVref) due to an abnormal voltage such as an excessive surge should be connected between AVcc and AVss, as shown in figure 22.6. Also, the bypass capacitors connected to AVcc and AVref, and the filter capacitors connected to AN0 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref Rin*2 *1 *1 0.1 F 100 AN0 to AN15 AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 22.6 Example of Analog Input Protection Circuit Rev. 1.00 Apr. 28, 2008 Page 743 of 994 REJ09B0452-0100 Section 22 A/D Converter Table 22.7 Analog Pin Specifications Item Analog input capacitance Permissible signal-source impedance Min. Max. 20 5 Unit pF k 10 k AN0 to AN15 20 pF To A/D converter Note: Values are reference values. Figure 22.7 Analog Input Pin Equivalent Circuit 22.7.7 Module Stop Mode Setting When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to the current as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable A/D conversion. Rev. 1.00 Apr. 28, 2008 Page 744 of 994 REJ09B0452-0100 Section 22 A/D Converter 22.7.8 Note on Activation of the A/D Converter by an External Trigger When starting of the A/D converter by an external trigger* is in use, any of the following actions (1. to 3.) may lead to a situation where stopping of the A/D converter is not possible. Note: * External trigger: Conversion-start trigger from the peripheral modules (TMU and TPU) 1. Changing the value of the ADST bit in ADCSR from 0 to 1 2. Changing from the activation by external trigger setting to the external-trigger-disabled setting 3. Changing the scan-mode setting (changing the setting of the SCANE and ADSTCLR bits to switch from continuous scan mode to single mode or one-cycle scan mode) If any of the above points is applicable, please make settings in accord with the instructions below. If 1. is applicable: Do not set the ADST bit in ADCSR to 1. If 2. or 3. is applicable: Be sure to invalidate the external trigger input before changing the setting from activation by the external trigger to disabling of the external trigger or changing the scan-mode setting (changing the setting of the SCANE and ADSTCLR bits) while activation by the external trigger is in use. Setting the TRGS1 and TRGS0 bits in ADCR according to the procedure overleaf invalidates the external trigger input. See figure 22.8 for details of the procedure in cases where 2. or 3. is applicable. Rev. 1.00 Apr. 28, 2008 Page 745 of 994 REJ09B0452-0100 Section 22 A/D Converter Extaernal trigger shut off? No ADCR.TRGS1 = 0 ADCR.TRGS0 = 0 (to invalidate the external trigger)* ADCSR.ADST = 0 Yes Change the scan mode change the extaernal trigger setting* Note * Overwrite the TRGS1 and TRGS0 bits settings at the same time (in a byte unit). Figure 22.8 Procedure for Changing Modes when Starting of the A/D Converter by an External Trigger has been Selected Rev. 1.00 Apr. 28, 2008 Page 746 of 994 REJ09B0452-0100 Section 23 RAM Section 23 RAM This LSI has 8 Kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU for both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 1.00 Apr. 28, 2008 Page 747 of 994 REJ09B0452-0100 Section 23 RAM Rev. 1.00 Apr. 28, 2008 Page 748 of 994 REJ09B0452-0100 Section 24 Flash Memory Section 24 Flash Memory The flash memory has the following features. Figure 24.1 is a block diagram of the flash memory. 24.1 * Size Features ROM Size 160 kbytes ROM Address H'000000 to H'027FFF (mode 2) Product Classification H8S/2117R R4F2117R * Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the parameters. * Programming/erasing time Programming time: 1 ms (typ) for 128-byte simultaneous programming, 7.8 s per byte Erasing time: 600 ms (typ) per 1 block (64 kbytes) * Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) * Two on-board programming modes Boot mode: Using the on-chip SCI-1, the user MAT can be programmed/erased. In boot mode, the bit rate between the host and this LSI can be adjusted automatically. User program mode: Using a desired interface, the user MAT can be programmed/erased. * Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT can be programmed/erased. * Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection. Rev. 1.00 Apr. 28, 2008 Page 749 of 994 REJ09B0452-0100 Section 24 Flash Memory Internal address bus Internal data bus (16 bits) FCCS Module bus FPCS FECS FKEY FTDAR FMATS Flash memory Control unit Memory MAT unit User MAT: 160 kbytes User boot MAT: 8 kbytes Mode pins Operating mode [Legend] FCCS: Flash code control/status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FMATS: Flash MAT select register RAMER: Flash transfer destination address register Note: To read/write the registers above, the FLSHE bit in the serial timer control register (STCR) must be set to 1. Figure 24.1 Block Diagram of Flash Memory 24.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 24.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user program mode, user boot mode, and programmer mode. The differences between boot mode, user program mode, user boot mode, and programmer mode are shown in table 24.1. Rev. 1.00 Apr. 28, 2008 Page 750 of 994 REJ09B0452-0100 Section 24 Flash Memory RES = 0 Reset state Programmer mode setting RE m od e Programmer mode Us er End of programming/ erasure User mode Start of programming/ erasure User program mode RE d mo S e = R = ES 0 se g ttin Bo ot S = 0 = S RE de mo ot bo ing er sett Us 0 0 se tti ng User boot mode On-board programming mode Boot mode Figure 24.2 Mode Transition of Flash Memory Table 24.1 Differences between Boot Mode, User Program Mode, and Programmer Mode Item Boot Mode User Program Mode On-board programming * User MAT Programmer User Boot Mode Mode On-board programming * User MAT PROM programmer * * O O Via any device User MAT O O Via any device User boot MAT*2 User MAT User boot MAT Programming/ On-board erasing environment programming Programming/ * erasing enable MAT * All erasure Block division erasure Program data transfer User MAT User boot MAT 1 O (Automatic) O* O (Automatic) x Via programmer From host via SCI Reset initiation MAT Embedded program storage area Transition to user mode Changing mode Changing FLSHE bit and reset setting Changing mode and reset Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 24.8.2, User Program Mode. Rev. 1.00 Apr. 28, 2008 Page 751 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.3 Flash Memory MAT Configuration This LSI's flash memory is configured by the 160-Kbyte user MAT and 8-Kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed only in boot mode and programmer mode. 160K bytes Address H'027FFF Figure 24.3 Flash Memory Configuration The size of the user MAT is different from that of the user boot MAT. An address that exceeds the size of the 8-Kbyte user boot MAT should not be accessed. If the attempt is made, data is read as an undefined value. Rev. 1.00 Apr. 28, 2008 Page 752 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.4 Block Structure Figure 24.4 shows the 160-kbyte block structure. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames indicates the addresses. The 160-kbyte user MAT is divided into one 64-kbyte block, two 32-kbyte blocks, and eight 4-kbyte blocks. The user MAT can be erased in these block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002 H'027F80 H'027F81 H'027F82 Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F H'027FFF EB0 4 kbytes EB1 4 kbytes EB2 4 kbytes EB3 4 kbytes EB4 4 kbytes EB5 4 kbytes EB6 4 kbytes EB7 4 kbytes EB8 32 kbytes EB9 64 kbytes EB10 32 kbytes Figure 24.4 Block Structure of the User MAT Rev. 1.00 Apr. 28, 2008 Page 753 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode is made by the user. Figure 24.5 shows the procedure for creating the procedure program. For details, see section 24.8.2, User Program Mode. Start procedure program for programming/erasing Select on-chip program to be downloaded and specify destination Download on-chip program by setting FKEY and SCO bit in FCCS Execute initialization (downloaded program execution) Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) Programming/erasing completed? Yes End procedure program No Figure 24.5 Procedure for Creating Procedure Program Rev. 1.00 Apr. 28, 2008 Page 754 of 994 REJ09B0452-0100 Section 24 Flash Memory (1) Selection of On-Chip Program to be Downloaded This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR). (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. (3) Initialization of Programming/Erasing A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasing The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasing. Rev. 1.00 Apr. 28, 2008 Page 755 of 994 REJ09B0452-0100 Section 24 Flash Memory (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively. 24.6 Input/Output Pins The flash memory is controlled through the input/output pins shown in table 24.2. Table 24.2 Pin Configuration Abbreviation RES MD2, MD1 TxD1 RxD1 I/O Input Input Output Input Function Reset Set operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) Rev. 1.00 Apr. 28, 2008 Page 756 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.7 Register Descriptions The flash memory has the following registers and parameters. Table 24.3 Register Configuration Register Name Flash code control status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register Note: * Abbreviation R/W FCCS FPCS FECS FKEY FMATS FTDAR R/W* R/W R/W R/W R/W R/W Initial Value H'80 H'00 H'00 H'00 H'00 H'00 Address H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE Data Bus Width 8 8 8 8 8 8 Bits other than the SCO bit are read-only bits. The SCO bit is a write-only bit and is always read as 0. Table 24.4 Parameter Configuration Register Name Download path fail result parameter Flash path/fail parameter Flash program/erase frequency parameter Flash multipurpose address area parameter Flash multipurpose data destination parameter Flash erase block select parameter Note: * Abbreviation R/W DPFR FPFR FPEFEQ FMPAR FMPDR FEBS R/W* R/W R/W R/W R/W R/W Initial Value Address Data Bus Width 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Undefined On-chip RAM* Undefined R0L of CPU Undefined ER0 of CPU Undefined ER1 of CPU Undefined ER0 of CPU Undefined ER0 of CPU One byte of the start address on the on-chip RAM specified by FTDAR Rev. 1.00 Apr. 28, 2008 Page 757 of 994 REJ09B0452-0100 Section 24 Flash Memory There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT. The correspondence between operating modes and registers/parameters for use is shown in table 24.5. Table 24.5 Registers/Parameters and Target Modes Register/Parameter Programming/ erasing interface registers FCCS FPCS FECS FKEY FMATS FTDAR Programming/ erasing interface parameters DPFR FPFR FPEFEQ FMPAR FMPDR FEBS InitialiDownload zation O O O O O O O O Programming O O* O O O 1 Erasure O O* O O 1 Read O*2 Notes: 1. Programming and erasure of the user MAT in user boot mode require settings. 2. A setting may be required depending on the combination of the startup mode and the MAT to be read. Rev. 1.00 Apr. 28, 2008 Page 758 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. Bit 7 6 5 4 Initial Bit Name Value FLER 1 0 0 0 R/W R R R R Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] * At a power-on reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasing. When the flash memory is read during programming/erasing (including a vector read and an instruction fetch). When the SLEEP instruction is executed during programming/erasing (including software standby mode). Description Reserved These are read-only bits and cannot be modified. * Rev. 1.00 Apr. 28, 2008 Page 759 of 994 REJ09B0452-0100 Section 24 Flash Memory Bit 3 to 1 0 Initial Bit Name Value SCO All 0 0 R/W R (R)/W* Description Reserved These are read-only bits and cannot be modified. Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY, and this operation must be executed in the onchip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bankswitching of the program storage area is executed. 0: Download of the programming/erasing program is not requested. [Clearing condition] * When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied) * * H'A5 is written to FKEY Setting of this bit is executed in the on-chip RAM Note: * This is a write-only bit. This bit is always read as 0. Rev. 1.00 Apr. 28, 2008 Page 760 of 994 REJ09B0452-0100 Section 24 Flash Memory (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit 7 to 1 0 Initial Bit Name Value PPVS All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Program Pulse Verify Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected. (3) Flash Erase Code Select Register (FECS) FECS selects the erasing program to be downloaded. Bit 7 to 1 0 Initial Bit Name Value EPVB All 0 0 R/W R R/W Description Reserved These are read-only bits and cannot be modified. Erase Pulse Verify Block Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected. Rev. 1.00 Apr. 28, 2008 Page 761 of 994 REJ09B0452-0100 Section 24 Flash Memory (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. Only when H'5A is written can programming/erasing of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasing cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'A5, the software protection state is entered.) H'00: Initial value Rev. 1.00 Apr. 28, 2008 Page 762 of 994 REJ09B0452-0100 Section 24 Flash Memory (5) Flash MAT Select Register (FMATS) FMATS specifies whether the user MAT or user boot MAT is selected. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description MAT Select The user MAT is selected when a value other than H'AA is written, and the user boot MAT is selected when H'AA is written. The MAT is switched by writing a value in FMATS. To switch the MAT, make sure to follow section 24.10, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user program mode even if the user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or programmer mode.) H'AA: User boot MAT is selected (user MAT is selected when the value of these bits is other than H'AA). Initial value when initiated in user boot mode. H'00: Initial value when initiated in a mode other than user boot mode (user MAT is selected). [Programmable condition] Execution state in the on-chip RAM Note: * The initial value is 1 in user boot mode and 0 in a mode other than user boot mode. Rev. 1.00 Apr. 28, 2008 Page 763 of 994 REJ09B0452-0100 Section 24 Flash Memory (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit 7 Initial Bit Name Value TDER 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'01 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H'00 to H'01. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'02 and H'FF and download has stopped. 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W H'01: Transfer Destination Address Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'01, and up to 3 kbytes can be specified as the start address of the on-chip RAM. H'00: H'FFD080 is specified as the start address. H'FFD880 is specified as the start address. H'02 to H'7F: Setting prohibited. (Specifying a value from H'02 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.) Rev. 1.00 Apr. 28, 2008 Page 764 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a power-on reset or a transition to software standby mode. Since registers of the CPU except for R0L are saved in the stack area during download of an onchip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0L. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 24.6 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 24.6 Parameters and Target Modes Parameter DPFR FPFR FPEFEQ FMPAR FMPDR FEBS Download Initialization Programming Erasure R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Allocation On-chip RAM* R0L of CPU ER0 of CPU ER1 of CPU ER0 of CPU ER0 of CPU O * O O O O O O O Note: A single byte of the start address of the on-chip RAM specified by FTDAR (a) Download Control The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The onchip RAM area to download the on-chip program is the 4-kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value. Rev. 1.00 Apr. 28, 2008 Page 765 of 994 REJ09B0452-0100 Section 24 Flash Memory (b) Initialization before Programming/Erasing The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. (c) Programming When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 24.8.2, User Program Mode. (d) Erasure When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 10 as the erase block number. For details on the erasing procedure, see section 24.8.2, User Program Mode. Rev. 1.00 Apr. 28, 2008 Page 766 of 994 REJ09B0452-0100 Section 24 Flash Memory (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. Bit 7 to 3 2 Initial Bit Name Value SS R/W R/W Description Unused These bits return 0. Source Select Error Detect Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal 1 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5) 0 SF R/W Success/Fail Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs) Rev. 1.00 Apr. 28, 2008 Page 767 of 994 REJ09B0452-0100 Section 24 Flash Memory (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. Bit 7 to 2 1 Bit Name FQ Initial Value R/W R/W Description Unused These bits return 0. Frequency Error Detect Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) Rev. 1.00 Apr. 28, 2008 Page 768 of 994 REJ09B0452-0100 Section 24 Flash Memory (b) Programming FPFR indicates the return value of the programming result. Bit 7 6 Bit Name MD Initial Value R/W R/W Description Unused Returns 0. Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state see section 24.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. Also an attempt to write the user MAT when the FMATS value is H'AA and the user boot MAT is selected leads to a programming execution error. In that case, both the user MAT and user boot MAT are not rewritten. Writing to the user boot MAT must be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) 4 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'5A) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 Unused Returns 0. Rev. 1.00 Apr. 28, 2008 Page 769 of 994 REJ09B0452-0100 Section 24 Flash Memory Bit 2 Initial Bit Name Value WD R/W R/W Description Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal 1 WA R/W 0 SF R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * An area other than flash memory * The specified address is not aligned with the 128byte boundary (lower eight bits of the address are other than H'00 and H'80) 0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal Success/Fail Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) Rev. 1.00 Apr. 28, 2008 Page 770 of 994 REJ09B0452-0100 Section 24 Flash Memory (c) Erasure FPFR indicates the return value of the erasure result. Bit 7 6 Initial Bit Name Value MD R/W R/W Description Unused Returns 0. Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state see section 24.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be erased (FLER = 1) 5 EE R/W Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. Also an attempt to erase the user MAT when the FMATS value is H'AA and the user boot MAT is selected leads to an erasure execution error. In that case, both the user MAT and user boot MAT are not erased. Erasure of the user boot MAT must be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally 4 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) Rev. 1.00 Apr. 28, 2008 Page 771 of 994 REJ09B0452-0100 Section 24 Flash Memory Bit 3 Initial Bit Name Value EB R/W R/W Description Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1 0 SF R/W Unused These bits return 0. Success/Fail Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) Rev. 1.00 Apr. 28, 2008 Page 772 of 994 REJ09B0452-0100 Section 24 Flash Memory (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 20 MHz. Bit Initial Bit Name Value R/W R/W Description Unused These bits should be cleared to 0. 15 to 0 F15 to F0 Frequency Set These bits set the operating frequency of the CPU. The setting value must be calculated as follows: 1. Round off the operating frequency expressed in MHz unit at the third decimal place to make it into two decimal places. 2. Multiply the rounded number by 100 and convert the result into binary and write it to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 20.000 MHz, the setting value is as follows: 1. Round 20.000 off at the third decimal place as 20.00. 2. Convert 20.00 x 100 = 2000 into a binary number and set B'0000 0111 1101 0000 (H'07D0) in ER0. 31 to 16 Rev. 1.00 Apr. 28, 2008 Page 773 of 994 REJ09B0452-0100 Section 24 Flash Memory (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR. Bit 31 to 0 Initial Bit Name Value MOA31 to MOA0 R/W R/W Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0. (5) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR. Bit 31 to 0 Initial Bit Name Value MOD31 to MOD0 R/W R/W Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address. Rev. 1.00 Apr. 28, 2008 Page 774 of 994 REJ09B0452-0100 Section 24 Flash Memory (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Settable values range from 0 to 10 (H'00000000 to H'0000000A). A value of 0 corresponds to block EB0 and a value of 10 corresponds to block EB10. Do not set a value outside the range from 0 to 10. Bit 31 to 8 7 to 0 Initial Bit Name Value EBS7 to EBS0 R/W Description Unused These bits should be set to 0. Undefined R/W These bits specify the erase block number from 0 to 10. A value of 0 corresponds to block EB0 and 10 corresponds to block EB10. Do not set a value outside the range from 0 to 10 (from H'00 to H'0A). Undefined R/W Rev. 1.00 Apr. 28, 2008 Page 775 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.8 On-Board Programming Mode When the mode pins (MD1 and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. Table 24.7 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see figure 24.2. Table 24.7 On-Board Programming Mode Setting Mode Setting Boot mode User program mode User boot mode MD2 1 0 1 MD1 0 1 0 NMI 1 0/1 0 24.8.1 Boot Mode Boot mode executes programming/erasing of the user MAT and the user boot MAT by means of the control command and program data transmitted from the externally connected host via the onchip SCI_1. In boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in boot mode is shown in figure 24.6. Interrupts are ignored in boot mode. Configure the user system so that interrupts do not occur. This LSI Software for analyzing control commands (on-chip) Control command, program data RxD1 SCI_1 TxD1 On-chip RAM Flash memory Host Programming tool and program data Response Figure 24.6 System Configuration in Boot Mode Rev. 1.00 Apr. 28, 2008 Page 776 of 994 REJ09B0452-0100 Section 24 Flash Memory (1) Serial Interface Setting by Host The SCI_1 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_1 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 24.8. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 24.7 Automatic-Bit-Rate Adjustment Operation Table 24.8 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host 9,600 bps 19,200 bps System Clock Frequency of This LSI 8 to 20 MHz 8 to 20 MHz Rev. 1.00 Apr. 28, 2008 Page 777 of 994 REJ09B0452-0100 Section 24 Flash Memory (2) State Transition Diagram The state transition after boot mode is initiated is shown in figure 24.8. (Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Bit rate adjustment H'55 rece ption Boot mode initiation (reset by boot mode) 1. 2. Wait for inquiry setting command Inquiry command reception Inquiry command response Processing of inquiry setting command 3. All user MAT and user boot MAT erasure 4. Wait for programming/erasing command Read/check command reception Command response Processing of read/check command (Programming completion) (Erasure completion) (Erasure selection command reception) (Erase-block specification) (Erasure selection command reception) (Program data transmission) Wait for erase-block data Wait for program data Figure 24.8 Boot Mode State Transition Diagram Rev. 1.00 Apr. 28, 2008 Page 778 of 994 REJ09B0452-0100 Section 24 Flash Memory 1. After boot mode is initiated, the bit rate of the SCI_1 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When reprogramming an erase block including an area on which the programming end command is issued, erase the erase block. An example of the erase block is shown in figure 24.9. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT and user boot MAT, and acquisition of current status information. Memory read of the user MAT and user boot MAT can only read the data programmed after all user MAT and user boot MAT have automatically been erased. No other data can be read. EB5 EB6 Programming end area EB7 Before reprogramming erase blocks EB6 and EB7 on which the programming end command is issued, erase the blocks (EB6 and EB7). EB8 Figure 24.9 Example of Erase Block Including Programmed Area Rev. 1.00 Apr. 28, 2008 Page 779 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The programming/erasing flow is shown in figure 24.10. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state must not be made during programming/erasing. A transition to the reset state during programming/erasing may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. Programming/erasing start 1. Programming/erasing is executed only in the on-chip RAM. 2. After programming/erasing is finished, protect the flash memory by the hardware protection. 3. Make sure that the program data do not overlap with the download destination specified by FTDAR. When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 24.10 Programming/Erasing Flow Rev. 1.00 Apr. 28, 2008 Page 780 of 994 REJ09B0452-0100 Section 24 Flash Memory (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 24.11 shows the area of the on-chip program to be downloaded. DPFR (Return value: 1 byte) System use area (15 bytes) Area to be downloaded (size: 3 kbytes) Unusable area during programming/erasing Programming/ programming end/ erasing program entry Initialization program entry Initialization + programming + programming end program or Initialization + erasing program FTDAR setting + 3 kbytes Area that can be used by user H'FFEFFF FTDAR setting + address 16 FTDAR setting FTDAR setting + address 32 Figure 24.11 RAM Map when Programming/Erasing is Executed Rev. 1.00 Apr. 28, 2008 Page 781 of 994 REJ09B0452-0100 Section 24 Flash Memory (2) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 24.12. Start programming procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 Disable interrupts and bus master operation other than CPU Set FKEY to H'5A 2. Set parameters to ER1 and ER0 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 1. 8. 9. Set SCO to 1 after initializing VBR and execute download Download 2. 10. Clear FKEY to 0 3. Programming 11. 12. No Clear FKEY and programming error processing 13. DPFR = 0? Yes Set the FPEFEQ parameter Initialization 4. No Download error processing FPFR = 1? Yes 5. No 6. Required data programming is completed? Yes 7. No Initialization error processing End programming procedure program Clear FKEY to 0 Initialization JSR FTDAR setting + 32 FPFR = 0? Yes 14. 1 Figure 24.12 Programming Procedure in User Program Mode Rev. 1.00 Apr. 28, 2008 Page 782 of 994 REJ09B0452-0100 Section 24 Flash Memory The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area. The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. H'A5 is written to FKEY. Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Particular processing that is accompanied by bank switching as described below is performed when download is executed. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1. The user-MAT space is switched to the on-chip program storage area. After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM. FPCS, FECS, and the SCO bit in FCCS are cleared to 0. The return value is set in the DPFR parameter. The values of general registers of the CPU are held. During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested. Rev. 1.00 Apr. 28, 2008 Page 783 of 994 REJ09B0452-0100 Section 24 Flash Memory 3. 4. 5. 6. To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. FKEY is cleared to H'00 for protection. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 32 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 24.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU). Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps. MOV.L #DLTOP+32,ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call initialization routine The general registers other than R0L are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM. Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. Rev. 1.00 Apr. 28, 2008 Page 784 of 994 REJ09B0452-0100 Section 24 Flash Memory 7. The return value in the initialization program, the FPFR parameter is determined. 8. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. 9. FKEY must be set to H'5A and the user MAT must be prepared for programming. 10. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0. Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary. Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. 11. Programming is executed. The entry point of the programming program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps. MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine The general registers other than R0L are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. Rev. 1.00 Apr. 28, 2008 Page 785 of 994 REJ09B0452-0100 Section 24 Flash Memory 12. The return value in the programming program, the FPFR parameter is determined. 13. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 14. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev. 1.00 Apr. 28, 2008 Page 786 of 994 REJ09B0452-0100 Section 24 Flash Memory (3) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.13. Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR 1 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'5A Set FKEY to H'A5 Download Set SCO to 1 and execute download Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 1 ? Yes 2. Clear FKEY to 0 Erasing 3. 4. No DPFR = 0? Yes Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes 1 No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Yes Clear FKEY to 0 5. Initialization 6. No Initialization error processing End erasing procedure program Figure 24.13 Erasing Procedure in User Program Mode The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM and user MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. For the downloaded on-chip program area, see figure 24.11. Rev. 1.00 Apr. 28, 2008 Page 787 of 994 REJ09B0452-0100 Section 24 Flash Memory One erasure processing erases one block. For details on block divisions, refer to figure 24.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 24.8.2 (2), Programming Procedure in User Program Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps. MOV.L #DLTOP+16, ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call erasing routine The general registers other than R0L are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 s. * * * Rev. 1.00 Apr. 28, 2008 Page 788 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.8.3 User Boot Mode This LSI has user boot mode that is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 24.7. When the reset start is executed in user boot mode, the built-in check routine runs. The user MAT and user boot MAT states are checked by this check routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to FMATS because the execution target MAT is the user boot MAT. (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 24.14 shows the procedure for programming the user MAT in user boot mode. Rev. 1.00 Apr. 28, 2008 Page 789 of 994 REJ09B0452-0100 Section 24 Flash Memory Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 MAT switchover Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Set FKEY to H'A5 Download Set SCO to 1 and execute download User-MAT selection state Clear FKEY to 0 Programming Set parameters to ER0 and ER1 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 FPFR = 0? DPFR = 0? No Yes Download error processing Initialization Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? Yes No No Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT MAT switchover End erasing procedure program 1 User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 24.14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 24.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After the programming procedure completes, switch the MATs again to return to the first state. Rev. 1.00 Apr. 28, 2008 Page 790 of 994 REJ09B0452-0100 Section 24 Flash Memory MAT switching is enabled by writing a specific value to FMATS. Note, however, that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 24.10, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processing made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 24.15 shows the procedure for erasing the user MAT in user boot mode. Rev. 1.00 Apr. 28, 2008 Page 791 of 994 REJ09B0452-0100 Section 24 Flash Memory Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR Set FKEY to H'A5 1 MAT switchover Set FMATS to value other than H'AA to select user MAT User-boot-MAT selection state Download Set SCO to 1 and execute download Set FKEY to H'A5 User-MAT selection state Clear FKEY to 0 Set FEBS parameter Programming JSR FTDAR setting + 16 FPFR = 0? DPFR = 0? No Yes Download error processing Erasing Initialization Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0? Yes No No Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Disable interrupts and bus master operation other than CPU Set FMATS to H'AA to select user boot MAT End erasing procedure program MAT switchover 1 User-boot-MAT selection state Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 24.15 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 24.15. MAT switching is enabled by writing a specific value to FMATS. Note, however, that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined. Perform MAT switching in accordance with the description in section 24.10, Switching between User MAT and User Boot MAT. Rev. 1.00 Apr. 28, 2008 Page 792 of 994 REJ09B0452-0100 Section 24 Flash Memory Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM and user MAT) is shown in section 24.8.4, Storable Areas for On-Chip Program and Program Data. 24.8.4 Storable Areas for On-Chip Program and Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied. * The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use. * Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area. * Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs. * In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing starts (download result is determined). * The flash memory is not accessible during programming/erasing. Programming/erasing is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory. * After programming/erasing starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 s when the operating mode is changed and the reset start executed on completion of programming/erasing. Transitions to the reset state are inhibited during programming/erasing. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 s is needed before the reset signal is released. * Switching of the MATs by FMATS should be required when programming/erasong of the user MAT is operated in user boot mode. The program that switches the MATs should be executed from the on-chip RAM. (For details, see section 24.10, Switching between User MAT and User Boot MAT.) Make sure you know which MAT is currently selected when witching them. * When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. Rev. 1.00 Apr. 28, 2008 Page 793 of 994 REJ09B0452-0100 Section 24 Flash Memory In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 24.9 to 24.13. Table 24.9 Executable Memory MAT Operating Mode Processing Contents Programming Erasing Note: * User Program Mode See table 24.10. See table 24.11. Programming/Erasing is possible to the User Mat. User boot Mode* See table 24.12 See table 24.13 Table 24.10 Usable Area for Programming in User Program Mode Storable/Executable Area Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY Note: * On-Chip RAM User MAT O O O O O O O O O O O O O O O O O O O x* O O x O O O O x O O x O O x x x x x Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Transferring the program data to the on-chip RAM beforehand enables this area to be used. Rev. 1.00 Apr. 28, 2008 Page 794 of 994 REJ09B0452-0100 Section 24 Flash Memory Table 24.11 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY On-Chip RAM O O O O O O O O O O O O O O O O O O User MAT O O x O O O O x O O x O O x x x x x Rev. 1.00 Apr. 28, 2008 Page 795 of 994 REJ09B0452-0100 Section 24 Flash Memory Table 24.12 Usable Area for Programming in User Boot Mode Storable/Executable Area User Boot MAT x* x x x x x x x x x* x x 2 1 Selected MAT User Boot MAT Embedded Program Storage MAT Item Storage area for program data Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts On-chip RAM User MAT Switching MATs by FMATS Writing H'5A to FKEY Setting programming parameter Programming Determination of programming result Programming error processing FKEY clearing Switching MATs by FMATS Notes: 1. Transferring the data to the on-chip RAM in advance enables this area to be used. 2. Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00 Apr. 28, 2008 Page 796 of 994 REJ09B0452-0100 Section 24 Flash Memory Table 24.13 Usable Area for Erasure in User Boot Mode Storable/Executable Area User Boot On-chip RAM MAT x x x x x x x x x* x x Selected MAT User Boot MAT Embedded Program Storage MAT Item User MAT Selecting on-chip program to be downloaded Writing H'A5 to FKEY Writing 1 to SCO in FCCS (download) FKEY clearing Determination of download result Download error processing Setting initialization parameter Initialization Determination of initialization result Initialization error processing NMI handling routine Disabling interrupts Switching MATs by FMATS Writing H'5A to FKEY Setting erasure parameter Erasure Determination of erasure result Erasing error processing FKEY clearing Switching MATs by FMATS Note: * Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00 Apr. 28, 2008 Page 797 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasing is indicated by the FPFR parameter. Table 24.14 Hardware Protection Function to be Protected Item Reset protection Description * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Download O Programming/ Erasing O * Rev. 1.00 Apr. 28, 2008 Page 798 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program and using the key code. Table 24.15 Software Protection Function to be Protected Item Description Download Programming/ Erasing O Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. Protection by FKEY The programming/erasing protection state is entered because download and programming/erasing are disabled unless the required key code is written in FKEY. O O 24.9.3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasing of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered. * When an interrupt request, such as NMI, occurs during programming/erasing. * When the flash memory is read from during programming/erasing (including a vector read or an instruction fetch). * When a SLEEP instruction is executed (including software-standby mode) during programming/erasing. Rev. 1.00 Apr. 28, 2008 Page 799 of 994 REJ09B0452-0100 Section 24 Flash Memory Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100s has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 24.16 shows transitions to and from the error protection state. Programming/erasing mode Read disabled Programming/erasing enabled FLER = 0 RES = 0 Reset (hardware protection) Read disabled Programming/erasing disabled FLER = 0 Er (S ror oc oft cu wa rre d by RE S= 0 re Error occurrence sta nd RES = 0 Programming/erasing interface register is in its initial state. ) Error-protection mode Read enabled Programming/erasing disabled FLER = 1 Software standby mode Error-protection mode (software standby) Read disabled Programming/erasing disabled FLER = 1 Programming/erasing interface register is in its initial state. Cancel software standby mode Figure 24.16 Transitions to Error Protection State Rev. 1.00 Apr. 28, 2008 Page 800 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.10 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because both of these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2. To ensure that switching has finished and access is made to the newly switched MAT, execute four NOP instructions in the same on-chip RAM immediately after writing to FMATS (this prevents access to the flash memory during MAT switching). 3. If an interrupt has occurred during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching between MATs. In addition, configure the system so that NMI interrupts do not occur during MAT switching. 4. After the MATs have been switched, take care because the interrupt vector table will also have been switched. 5. Memory sizes of the user MAT and user boot MAT are different. Do not access a user boot MAT in a space of 8 kbytes or more. If access goes beyond the 8-kbyte space, the values read are undefined. Figure 24.17 Switching between User MAT and User Boot MAT Rev. 1.00 Apr. 28, 2008 Page 801 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.11 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 24.16 can be used to write programs to the on-chip ROM without any limitation. Table 24.16 Device Types Supported in Programmer Mode Target Memory MAT User MAT User boot MAT Note: * Size 256 kbytes* 8 kbytes Device Type FZTAT256V3A FZTATUSBTV3A For the R4F2117R model, 160 kbytes of ROM space is available when the user MAT is selected. If programming is performed in programmer mode, H'FF data must be written to address H'28000 to H'3FFFF with 256-kbyte capacity setting. 24.12 Standard Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs serial communication using the host and onchip SCI_1. The serial communication interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communication with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rateadjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs before the transition. Rev. 1.00 Apr. 28, 2008 Page 802 of 994 REJ09B0452-0100 Section 24 Flash Memory 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 24.18. Reset Bit-rate-adjustment state Inquiry/ response wait Transition to programming/erasing Response Inquiry Operations for inquiry and selection Operations for response Operations for erasing user MATs Programming/ erasing wait Programming Operations for programming Erasing Operations for erasing Operations for checking Checking Figure 24.18 Boot Program States Rev. 1.00 Apr. 28, 2008 Page 803 of 994 REJ09B0452-0100 Section 24 Flash Memory (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 24.19. Host Boot program H'00 (30 times maximum) Measuring the 1-bit length H'00 (completion of adjustment) H'55 H'E6 (boot response) (H'FF (error)) Figure 24.19 Bit-Rate-Adjustment Sequence (2) Communications Protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. Rev. 1.00 Apr. 28, 2008 Page 804 of 994 REJ09B0452-0100 Section 24 Flash Memory 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of four bytes of data. One-byte command or one-byte response n-byte Command or n-byte response Command or response Data Size Command or response Checksum Error response Error code Error response 128-byte programming Address Command Memory read response Size Response Data Checksum Data (n bytes) Checksum Figure 24.20 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Data (n bytes): Detailed data of a command or response * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read Rev. 1.00 Apr. 28, 2008 Page 805 of 994 REJ09B0452-0100 Section 24 Flash Memory (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 24.17 lists the inquiry and selection commands. Table 24.17 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Supported device inquiry Device selection Clock mode inquiry Clock mode selection Division ratio inquiry Description Inquiry regarding device codes Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequency-divided clock types, the number of division ratios and the values of each division Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the a number of user boot MATs and the start and last addresses of each MAT Inquiry regarding the a number of user MATs and the start and last addresses of each MAT Inquiry regarding the number of blocks and the start and last addresses of each block Inquiry regarding the unit of program data Selection of new bit rate Erasing of user MATs or user boot MATs, and entry to programming/erasing state Inquiry into the operated status of the boot program H'23 H'24 H'25 H'26 H'27 H'3F H'40 H'4F Operating clock frequency inquiry User boot MAT information inquiry User MAT information inquiry Block for erasing information Inquiry Programming unit inquiry New bit rate selection Transition to programming/erasing state Boot program status inquiry Rev. 1.00 Apr. 28, 2008 Page 806 of 994 REJ09B0452-0100 Section 24 Flash Memory The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. Command H'20 * Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Number of characters ... SUM Size Number of devices Product name Device code * Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. Rev. 1.00 Apr. 28, 2008 Page 807 of 994 REJ09B0452-0100 Section 24 Flash Memory (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 4 * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR * Error response, H'90, (one byte): Error response to the device selection command ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 * Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode ... SUM * Response, H'31, (one byte): Response to the clock-mode inquiry * Size (one byte): Amount of data that represents the number of modes and modes * Number of clock modes (one byte): The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode. * Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (one byte): Checksum Rev. 1.00 Apr. 28, 2008 Page 808 of 994 REJ09B0452-0100 Section 24 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM * * * * Command, H'11, (one byte): Selection of clock mode Size (one byte): Amount of data that represents the modes Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum H'06 Response * Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR * Error response, H'91, (one byte) : Error response to the clock mode selection command * ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. Rev. 1.00 Apr. 28, 2008 Page 809 of 994 REJ09B0452-0100 Section 24 Flash Memory (e) Division Ratio Inquiry The boot program will return the supported division ratios in response to the inquiry. Command H'22 * Command, H'22, (one byte): Inquiry regarding division ratio Response H'32 Number of division ratios ... SUM Size Division ratio Number of types ... * Response, H'32, (one byte): Response to the division ratio inquiry * Size (one byte): The total amount of data that represents the number of types, the number of division ratios, and the division ratios * Number of types (one byte): The number of supported divided clock types (e.g. when there are two divided clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of division ratios (one byte): The number of division ratios for each type (e.g. the number of division ratios to which the main clock can be set and the peripheral clock can be set.) * Division ratio (one byte) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of division ratios returned is the same as the number of division ratios and as many groups of data are returned as there are types. * SUM (one byte): Checksum Rev. 1.00 Apr. 28, 2008 Page 810 of 994 REJ09B0452-0100 Section 24 Flash Memory (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 * Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Number of operating clock frequencies Maximum value of operating clock frequency Minimum value of operating clock frequency ... SUM * Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (one byte): Checksum Rev. 1.00 Apr. 28, 2008 Page 811 of 994 REJ09B0452-0100 Section 24 Flash Memory (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 * Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 ... SUM Size Number of areas Last address area Start address area * Response, H'34, (one byte): Response to the user boot MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user boot MAT areas When the user boot MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area * Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum Rev. 1.00 Apr. 28, 2008 Page 812 of 994 REJ09B0452-0100 Section 24 Flash Memory (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 * Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 ... SUM Size Number of areas Last address area Start address area * Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area * Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 * Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 ... SUM Size Number of blocks Block last address Block start address * Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block start address (four bytes): Start address of a block Rev. 1.00 Apr. 28, 2008 Page 813 of 994 REJ09B0452-0100 Section 24 Flash Memory * Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 * Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming. * SUM (one byte): Checksum (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Number of division ratios SUM Size Division ratio 1 Bit rate Division ratio 2 Input frequency * Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The total number of bytes that represents the bit rate, input frequency, number of division ratios, and division ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) Rev. 1.00 Apr. 28, 2008 Page 814 of 994 REJ09B0452-0100 Section 24 Flash Memory * Number of division ratios (one byte): The number of division ratios to which the device can be set. There are usually two division ratios, which are the main and peripheral module operating frequencies. * Division ratio 1 (one byte): The value of division ratios for the main operating frequency Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Division ratio 2 (one byte): The value of division ratios for the peripheral frequency (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error Response H'BF ERROR * Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Division ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. Rev. 1.00 Apr. 28, 2008 Page 815 of 994 REJ09B0452-0100 Section 24 Flash Memory (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Division ratio The received value of the division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, a division ratio error is generated. 3. Operating frequency error Operating frequency is calculated from the received value of the input frequency and the division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06 * Response, H'06, (one byte): Response to confirmation of a new bit rate Rev. 1.00 Apr. 28, 2008 Page 816 of 994 REJ09B0452-0100 Section 24 Flash Memory The sequence of new bit-rate selection is shown in figure 24.21. Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Boot program Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Setting a new bit rate Figure 24.21 New Bit-Rate Selection Sequence (5) Transition to Programming/Erasing State The boot program will transfer the erasing program and erase the data in the user MATs first , then the data in the user boot MATs. On completion of this erasure, ACK will be returned and the program will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Command H'40 * Command, H'40, (one byte): Transition to programming/erasing state Response H'06 * Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs and the user boot MATs have been erased by the transferred erasing program. Error Response H'C0 H'51 * Error response, H'C0, (one byte): Error response to the bland check of the user boot MATs * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. Rev. 1.00 Apr. 28, 2008 Page 817 of 994 REJ09B0452-0100 Section 24 Flash Memory (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx * Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command (7) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the division-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on division ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and the user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. Rev. 1.00 Apr. 28, 2008 Page 818 of 994 REJ09B0452-0100 Section 24 Flash Memory (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 24.18 lists the programming/erasing commands. Table 24.18 Programming/Erasing Commands Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4F Command Name User boot MAT programming selection User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check Boot program status inquiry Description Transfers the user boot MAT programming program Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks the blank data of the user boot MAT Checks the blank data of the user MAT Inquires into the boot program's status Rev. 1.00 Apr. 28, 2008 Page 819 of 994 REJ09B0452-0100 Section 24 Flash Memory 1. Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command. After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 24.22. Host Programming selection (H'42, H'43) Boot program Transfer of the programming program ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming Figure 24.22 Programming Sequence Rev. 1.00 Apr. 28, 2008 Page 820 of 994 REJ09B0452-0100 Section 24 Flash Memory 2. Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 24.23. Host Preparation for erasure (H'48) Boot program Transfer of erasure program ACK Repeat Erasure (Erasure block number) ACK Erasure (H'FF) ACK Erasure Figure 24.23 Erasure Sequence Rev. 1.00 Apr. 28, 2008 Page 821 of 994 REJ09B0452-0100 Section 24 Flash Memory 3. Programming/Erasing State Information (a) User Boot MAT Programming Selection The boot program will transfer a program for user boot MAT programming selection. The data is programmed to the user boot MATs by the transferred program for programming. Command H'42 * Command, H'42, (one byte): User boot MAT programming selection Response H'06 * Response, H'06, (one byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C2 ERROR * Error response: H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) User MAT Programming Selection The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming. Command H'43 * Command, H'43, (one byte): User-program programming selection Response H'06 * Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR * Error response : H'C3 (1 byte): Error response to user-program programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) Rev. 1.00 Apr. 28, 2008 Page 822 of 994 REJ09B0452-0100 Section 24 Flash Memory (c) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user MATs in response to 128-byte programming. Command H'50 Data ... SUM Address ... * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'00010000) * Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Rev. 1.00 Apr. 28, 2008 Page 823 of 994 REJ09B0452-0100 Section 24 Flash Memory Command H'50 Address SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (d) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 * Command, H'48, (one byte): Erasure selection Response H'06 * Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR * ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) Rev. 1.00 Apr. 28, 2008 Page 824 of 994 REJ09B0452-0100 Section 24 Flash Memory (e) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR * Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size, (one byte): The number of bytes that represents the block number This is fixed to 1. * Block number (one byte): H'FF Stop code for erasure * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 1.00 Apr. 28, 2008 Page 825 of 994 REJ09B0452-0100 Section 24 Flash Memory (f) Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read address SUM Read size * Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum Response H'52 Data SUM Read size ... * * * * Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (1 byte): Checksum H'D2 ERROR Error Response * Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. Rev. 1.00 Apr. 28, 2008 Page 826 of 994 REJ09B0452-0100 Section 24 Flash Memory (g) User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT. Command H'4A * Command, H'4A, (one byte): Sum check for user boot MAT Response H'5A Size Checksum of MAT SUM * Response, H'5A, (one byte): Response to the sum check of the user boot MAT * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of MAT (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (h) User-Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B * Command, H'4B, (one byte): Sum check for user program Response H'5B Size Checksum of user program SUM * Response, H'5B, (one byte): Response to the sum check of the user program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted Rev. 1.00 Apr. 28, 2008 Page 827 of 994 REJ09B0452-0100 Section 24 Flash Memory (i) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C * Command, H'4C, (one byte): Blank check for user boot MATs Response H'06 * Response, H'06, (one byte): Response to the blank check for user boot MATs If the contents of all user boot MATs are blank (H'FF), the boot program will return ACK. Error Response H'CC H'52 * Error Response, H'CC, (one byte): Error response to the blank check of user boot MATs. * Error code, H'52, (one byte): Erasure has not been completed. (j) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D * Command, H'4D, (one byte): Blank check for user MATs Response H'06 * Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52 * Error Response, H'CD, (one byte): Error response to the blank check of user MATs. * Error code, H'52, (one byte): Erasure has not been completed. Rev. 1.00 Apr. 28, 2008 Page 828 of 994 REJ09B0452-0100 Section 24 Flash Memory (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F * Command, H'4F, (one byte): Response H'5F Size Inquiry regarding boot program's state ERROR SUM Status * * * * Response, H'5F, (one byte): Response to boot program state inquiry Size (one byte): The number of bytes. This is fixed to 2. Status (one byte): State of the boot program ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (one byte): Sum check Table 24.19 Status Codes Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device selection wait Clock mode selection wait Bit rate selection wait Programming/erasing state transition wait (bit rate selection is completed) Programming state for erasure Programming/erasing selection wait (erasure is completed) Program data receive wait Erase block specification wait (erasure is completed) Rev. 1.00 Apr. 28, 2008 Page 829 of 994 REJ09B0452-0100 Section 24 Flash Memory Table 24.20 Error Codes Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No error Sum check error Program size error Device code mismatch error Clock mode mismatch error Bit rate selection error Input frequency error Division ratio error Operating frequency error Block number error Address error Data length error Erasure error Erasure incomplete error Programming error Selection processing error Command error Bit-rate-adjustment confirmation error Rev. 1.00 Apr. 28, 2008 Page 830 of 994 REJ09B0452-0100 Section 24 Flash Memory 24.13 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 256-Kbyte on-chip flash memory and 3.3 V programming voltage. Use only the specified socket adapter. 5. Do not power off the Vcc power supply (including the removal of the chip from the PROM programmer) during programming/erasing in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input, the reset must be released after the reset input period of at least 100s. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset input period (period of RES = 0) of at least 100s. Transition to the reset state during programming/erasing is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100s. 7. At powering on the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. If data other than H'FF (4 bytes) is written to the key code area (H'00003C to H'00003F) of the flash memory, reading cannot be performed in programmer mode. (In this case, data is read as H'00. Rewrite is possible after erasing the data.) For reading in programmer mode, make sure to write H'FF to the entire key code area. Rev. 1.00 Apr. 28, 2008 Page 831 of 994 REJ09B0452-0100 Section 24 Flash Memory 12. If data other than H'FF is to be written to the key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and version of program. 13. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 200 s at the maximum. 14. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8/H8S microcomputer. 15. Unlike a conventional F-ZTAT H8/H8S microcomputers, measures against a program crash are not taken by WDT while programming/erasing and downloading a programming/erasing program. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. In this case, the interrupt generation period should take into consideration time to program/erase the flash memory. 16. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 after immediately setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. 17. The contents of some registers are not saved in a programming/programming end/erasing program. When needed, save registers in the procedure program. Rev. 1.00 Apr. 28, 2008 Page 832 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator Section 25 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (), internal clock, bus master clock, and subclock (SUB). The clock pulse generator consists of an oscillator, duty correction circuit, system clock select circuit, subclock input circuit, and subclock waveform forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator. EXTAL XTAL Oscillator Duty correction circuit System clock select circuit Bus master clock to CPU EXCL (ExEXCL) Subclock input circuit Subclock waveform forming circuit SUB WDT_1 count clock, CIR sampling clock System clock to pin Internal clock to on-chip peripheral modules Figure 25.1 Block Diagram of Clock Pulse Generator The subclock input is controlled by software according to the EXCLE bit and the EXCLS bit in the port control register (PTCNT0) settings in the low power control register (LPWRCR). For details on LPWRCR, see section 26.1.2, Low-Power Control Register (LPWRCR). For details on PTCNT0, see section 7.3.1, Port Control Register 0 (PTCNT0). Rev. 1.00 Apr. 28, 2008 Page 833 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator 25.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 25.1.1 Connecting Crystal Resonator Figure 25.2 shows a typical method for connecting a crystal resonator. An appropriate damping resistance Rd, given in table 25.1 should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 25.3 shows an equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 25.2 should be used. The frequency of the crystal resonator should be the same as that of the system clock (). CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 25.2 Typical Connection to Crystal Resonator Table 25.1 Damping Resistor Values Frequency (MHz) Rd () 8 200 10 0 12 0 16 0 20 0 CL L XTAL Rs EXTAL AT-cut parallel-resonance crystal resonator C0 Figure 25.3 Equivalent Circuit of Crystal Resonator Rev. 1.00 Apr. 28, 2008 Page 834 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator Table 25.2 Crystal Resonator Parameters Frequency (MHz) RS (max) () C0 (max) (pF) 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 25.1.2 External Clock Input Method Figure 25.4 shows a typical method of inputting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode or watch mode. External clock input conditions are shown in table 25.3. The frequency of the external clock should be the same as that of the system clock (). EXTAL XTAL External clock input Open (a) Example of external clock input when XTAL pin is left open EXTAL XTAL External clock input (b) Example of external clock input when an inverted clock is input to XTAL pin Figure 25.4 Example of External Clock Input Rev. 1.00 Apr. 28, 2008 Page 835 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator Table 25.3 External Clock Input Conditions VCC = 3.0 to 3.6 V Item External clock input pulse width low level External clock input pulse width high level External clock rising time External clock falling time Clock pulse width low level Symbol tEXL tEXH tEXr tEXf tCL Min. 20 20 0.4 0.4 Max. 5 5 0.6 0.6 Unit Test Conditions ns ns ns ns tcyc tcyc Figure 28.4 Figure 25.5 Clock pulse width high level tCH tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 25.5 External Clock Input Timing The oscillator and duty correction circuit can adjust the waveform of the external clock input that is input from the EXTAL pin. When a specified clock signal is input to the EXTAL pin, internal clock signal output is determined after the external clock output stabilization delay time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset signal should be set to low to maintain the reset state. Table 25.4 shows the external clock output stabilization delay time. Figure 25.6 shows the timing of the external clock output stabilization delay time. Rev. 1.00 Apr. 28, 2008 Page 836 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator Table 25.4 External Clock Output Stabilization Delay Time Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Min. 500 Max. Unit s Remarks Figure 25.6 External clock output stabilization delay tDEXT* time Note: * tDEXT includes a RES pulse width (tRESW). VCC 3.0 V EXTAL (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 25.6 Timing of External Clock Output Stabilization Delay Time Rev. 1.00 Apr. 28, 2008 Page 837 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator 25.2 Duty Correction Circuit The duty correction circuit generates the system clock () by correcting the duty of the clock output from the oscillator. 25.3 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL or ExEXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL or ExEXCL pin. Figure 25.7 shows the relationship of subclock input from the EXCL pin and the ExEXCL pin. When using a pin to input the subclock, specify input for the pin by clearing the DDR bit of the pin to 0. The EXCL pin is specified as an input pin by clearing the EXCLS bit in PTCNT0 to 0. The ExEXCL pin is specified as an input pin by setting the EXCLS bit in PTCNT0 to 1. The subclock input is enabled by setting the EXCLE bit in LPWRCR to 1. EXCLS (PTCNT0) EXCLE (LPWRCR) P96/EXCL Subclock PE0/ExEXCL Figure 25.7 Subclock Input from EXCL Pin and ExEXCL Pin Subclock input conditions are shown in table 25.5. When the subclock is not used, subclock input should not be enabled. Table 25.5 Subclock Input Conditions VCC = 3.0 to 3.6 V Item Subclock input pulse width low level Subclock input pulse width high level Subclock input rising time Subclock input falling time Symbol tEXCLL tEXCLH tEXCLr tEXCLf Min. Typ. 15.26 15.26 Max. 10 10 Unit s s ns ns Test Conditions Figure 25.8 Rev. 1.00 Apr. 28, 2008 Page 838 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator tEXCLH tEXCLL EXCL VCC x 0.5 tEXCLr tEXCLf Figure 25.8 Subclock Input Timing 25.4 Subclock Waveform Forming Circuit To remove noise from the subclock input at the EXCL (ExEXCL) pin, the subclock waveform forming circuit samples the subclock using a divided clock. The sampling frequency is set by the NESEL bit in LPWRCR. The subclock is not sampled in watch mode. 25.5 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator to which the XTAL and EXTAL pins are connected is selected as a system clock () when returning from high-speed mode, sleep mode, the reset state, or standby mode. In watch mode, a subclock input from the EXCL (ExEXCL) pin is selected as a system clock when the EXCLE bit in LPWRCR is 1. At this time, on-chip peripheral modules such as WDT_1 and interrupt controller operate on the SUB clock. The count clock and sampling clock for each timer are divided SUB clocks. Rev. 1.00 Apr. 28, 2008 Page 839 of 994 REJ09B0452-0100 Section 25 Clock Pulse Generator 25.6 25.6.1 Usage Notes Notes on Resonator Since all kinds of characteristics of the resonator are closely related to the board design by the user, use the example of resonator connection in this document for only reference; be sure to use an resonator that has been sufficiently evaluated by the user. Consult with the resonator manufacturer about the resonator circuit ratings that vary depending on the stray capacitances of the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not exceed the maximum rating. 25.6.2 Notes on Board Design When using a crystal resonator, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator to prevent inductive interference with correct oscillation as shown in figure 25.9. Prohibited CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 25.9 Note on Board Design of Oscillator Section Rev. 1.00 Apr. 28, 2008 Page 840 of 994 REJ09B0452-0100 Section 26 Power-Down Modes Section 26 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has four power-down operating modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. * Medium-speed mode System clock frequency for the CPU operation can be selected as /2, /4, /8, /16 or /32. * Sleep mode The CPU stops but on-chip peripheral modules continue operating. * Watch mode The CPU stops, but on-chip peripheral module WDT_1 and CIR continue operating. * Software standby mode The clock pulse generator stops, and the CPU and on-chip peripheral modules stop operating. * Module stop mode Independently of above operating modes, on-chip peripheral modules that are not used can be stopped individually. 26.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR). For details on the PSS bit in TSCR_1 (WDT_1), see TCSR_1 in section 13.3.5, Timer Control/Status Register (TCSR). Table 26.1 Register Configuration Register Name Standby control register Low power control register Abbreviation SBYCR LPWRCR R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'00 H'00 H'3F H'FF H'FC H'FF H'FF84 H'FF85 H'FF86 H'FF87 H'FE7E H'FE7F Data Bus Width 8 8 8 8 8 8 Module stop control register H MSTPCRH Module stop control register L MSTPCRL Module stop control register A MSTPCRA Module stop control register B MSTPCRB Rev. 1.00 Apr. 28, 2008 Page 841 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. When the SLEEP instruction is executed in highspeed mode or medium-speed mode: 0: Shifts to sleep mode 1: Shifts to software standby mode or watch mode Note that the SSBY bit is not changed even if a mode transition is made by an interrupt. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 On canceling software standby mode or watch mode, these bits select the wait time for clock stabilization from clock oscillation start. Select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. Table 26.2 shows the relationship between the STS2 to STS0 values and wait time. With an external clock, an arbitrary wait time can be selected. For normal cases, the minimum value is recommended. 3 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 842 of 994 REJ09B0452-0100 Section 26 Power-Down Modes Bit 2 1 0 Bit Name SCK2 SCK1 SCK0 Initial Value 0 0 0 R/W R/W R/W R/W Description System Clock Select 2 to 0 These bits select a clock for the bus master in highspeed mode or medium-speed mode. When making a transition to watch mode, these bits must be cleared to B'000. 000: High-speed mode 001: Medium-speed clock: /2 010: Medium-speed clock: /4 011: Medium-speed clock: /8 100: Medium-speed clock: /16 101: Medium-speed clock: /32 11X: Setting prohibited [Legend] X: Don't care Table 26.2 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 0 0 0 0 1 1 1 Note: 0 0 1 1 0 0 1 0 1 0 1 0 1 0/1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved* 20 MHz 0.4 0.8 1.6 3.3 6.6 13.1 10 MHz 0.8 1.6 3.3 6.6 13.1 26.2 8 MHz 1.0 2.0 4.1 8.2 16.4 32.8 Unit ms Recommended specification * Setting prohibited. Rev. 1.00 Apr. 28, 2008 Page 843 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 6 5 Bit Name DTON LSON NESEL Initial Value 0 0 0 R/W R/W R/W R/W Description Direct Transfer On Flag The initial value should not be changed. Low-Speed On Flag The initial value should not be changed. Noise Elimination Sampling Frequency Select Selects the frequency by which the subclock (SUB) input from the EXCL or ExEXCL pin is sampled using the clock () generated by the system clock pulse generator. Clear this bit to 0 when is 5 MHz or more. The initial value should not be changed. 0: Sampling using /32 clock 1: Sampling using /4 clock (not allowed) 4 EXCLE 0 R/W Subclock Input Enable Enables or disables subclock input from the EXCL or ExEXCL pin. 0: Disables subclock input from the EXCL or ExEXCL pin 1: Enables subclock input from the EXCL or ExEXCL pin 3 to 0 All 0 R/W Reserved The initial value should not be changed. Rev. 1.00 Apr. 28, 2008 Page 844 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.1.3 Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. * MSTPCRH Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Reserved The initial value should not be changed. Reserved The initial value should not be changed. 8-bit timers (TMR_0 and TMR_1) 14-bit PWM timer (PWMX) Reserved The initial value should not be changed. A/D converter 8-bit timers (TMR_X and TMR_Y) * MSTPCRL Bit 7 6 5 4 3 2 Bit Name Initial Value R/W MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Serial communication interface 1 (SCI_1) Serial communication interface 2 (SCI_2) I2C bus interface channel 0 (IIC_0) I2C bus interface channel 1 (IIC_1) Keyboard buffer control unit_0 (PS2_0) Keyboard buffer control unit_1 (PS2_1) Keyboard buffer control unit_2 (PS2_2) 1 0 MSTP1 MSTP0 1 1 R/W R/W 16-bit timer pulse unit (TPU) LPC interface (LPC) Rev. 1.00 Apr. 28, 2008 Page 845 of 994 REJ09B0452-0100 Section 26 Power-Down Modes * MSTPCRA Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value R/W MSTPA7 1 MSTPA6 1 MSTPA5 1 MSTPA4 1 MSTPA3 1 MSTPA2 1 MSTPA1 0 MSTPA0 0 * R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Duty period measurement timer_0 (TDP_0) Duty period measurement timer_1 (TDP_1) Duty period measurement timer_2 (TDP_2) CIR interface (CIR) FSI interface (FSI)* 14-bit PWM timer (PWMX) Reserved The initial value should not be changed. Before accessing registers of the FSI interface, clear bit 0 in MSTPCRL (MSTP0) and bit 2 in MSTPCRA (MSTPA2) to 0. * MSTPCRB Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W MSTPB7 1 MSTPB6 1 MSTPB5 1 MSTPB4 1 MSTPB3 1 MSTPB2 1 MSTPB1 1 MSTPB0 1 R/W R/W R/W R/W R/W R/W R/W R/W Corresponding Module Reserved The initial value should not be changed. Reserved The initial value should not be changed. Keyboard buffer control unit_3 (PS2_3) I2C bus interface_2 (IIC_2) Serial communication interface with FIFO (SCIF) Cycle measurement timer_2 (TCM_2) Cycle measurement timer_3 (TCM_3) Cycle measurement timer_0 (TCM_0) Cycle measurement timer_1 (TCM_1) 8-bit PWMU timer_A (TWMU_A) 8-bit PWMU timer_B (TWMU_B) Rev. 1.00 Apr. 28, 2008 Page 846 of 994 REJ09B0452-0100 Section 26 Power-Down Modes The PWMX sets operation or stop by a combination of bits as follows: MSTPCRH: MSTP11 0 0 1 1 MSTPCRA: MSTPA1 0 1 0 1 Function 14-bit PWM timer (PWMX) operates. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. 14-bit PWM timer (PWMX) stops. Note: The MSTP11 bit in MSTPCRH is a module stop bit of the PWMX. Rev. 1.00 Apr. 28, 2008 Page 847 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.2 Mode Transitions and LSI States Figure 26.1 shows the possible mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The RES input causes a mode transition from any state to the reset state. Table 26.3 shows the LSI internal states in each operating mode. Reset state RES pin = Low Program halt state Program execution state RES pin = High SSBY = 0, LSON = 0 SLEEP instruction Any interrupt Sleep mode (main clock) High-speed mode (main clock) SLEEP instruction External interrupt*2 SLEEP instruction SSBY = 1, PSS = 0, LSON = 0 Software standby mode SCK2 to SCK0 = 0 SCK2 to SCK0 0 Interrupt*1 LSON bit = 0 SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) Medium-speed mode : Transition after exception processing : Power-down mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. 1. NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and WDT_1, PS2 and CIR interrupts 2. NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and PS2 interrupts Figure 26.1 Mode Transition Diagram Rev. 1.00 Apr. 28, 2008 Page 848 of 994 REJ09B0452-0100 Section 26 Power-Down Modes Table 26.3 LSI Internal States in Each Operating Mode Function System clock pulse generator Subclock input CPU Instruction execution Registers External interrupts NMI IRQ0 to IRQ15 KIN0 to KIN15 WUE8 to WUE15 On-chip peripheral modules WDT_1 CIR WDT_0 TMR_0, TMR_1 TPU TCM_0 to 3 TDP_0 to 2 TMR_X, TMR_Y SCIF IIC_0 to 2 LPC FSI PS2_0 to 3 PWMU PWM PWMX SCI_1, SCI_2 A/D converter RAM I/O Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Retained Retained Retained Retained Medium-speed operation/functioning Functioning Functioning/ stopped (reset) Stopped (reset) Stopped (reset) Functioning/ stopped (retained) Functioning Functioning Functioning Functioning Subclock operation Stopped (retained) Stopped (retained) Functioning Functioning High Speed Functioning Functioning Functioning Medium Speed Functioning Functioning Medium-speed operation Sleep Functioning Functioning Stopped Retained Functioning Functioning Module Stop Watch Functioning Functioning Functioning Stopped Functioning Stopped Retained Functioning Software Standby Stopped Stopped Stopped Retained Functioning Note: Stopped (retained) means that the internal register values are retained and the internal state is operation suspended. Stopped (reset) means that the internal register values and the internal state are initialized. In module stop mode, only modules for which a stop setting has been made are stopped (reset or retained). Rev. 1.00 Apr. 28, 2008 Page 849 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.3 Medium-Speed Mode The operating mode changes to medium-speed mode as soon as the current bus cycle ends by the settings of the SCK2 to SCK0 bits in SBYCR. The operating clock can be selected from /2, /4, /8, /16, or /32. On-chip peripheral functions other than the bus masters and the PS2 operate on the system clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in four states, and internal I/O registers in eight states. A transition is made from medium-speed mode to high-speed mode at the end of the current bus cycle by clearing all of bits SCK2 to SCK0 to 0. If the SLEEP instruction is executed when the SSBY bit in SBYCR is 0 and the LSON bit in LPWRCR is 0, a transition is made to sleep mode. When sleep mode is canceled by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to 1, the LSON bit in LPWRCR set to 0, and the PSS bit in TCSR (WDT_1) set to 0, operation shifts to software standby mode. When software standby mode is canceled by an external interrupt, medium-speed mode is restored. When the RES pin is driven low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies to a reset caused by an overflow of the watchdog timer. Figure 26.2 shows the timing of medium-speed mode. Medium-speed mode , peripheral module clock Bus master clock Internal address bus Internal write signal SBYCR SBYCR Figure 26.2 Timing of Medium-Speed Mode Rev. 1.00 Apr. 28, 2008 Page 850 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the on-chip peripheral modules do not. The contents of the CPU's internal registers are retained. Sleep mode is cleared by any interrupt or the RES pin input. When an interrupt occurs, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the interrupt is disabled, or interrupts other than NMI have been masked by the CPU. When the RES pin is driven low and sleep mode is cleared, a transition is made to the reset state. After the specified reset input time has elapsed, driving the RES pin high causes the CPU to start reset exception handling. 26.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of on-chip peripheral modules other than the SCI, PWMU, PWMX, and A/D converter are retained as long as the prescribed voltage is supplied. Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15, KIN0 to KIN15, or WUE8 to WUE15), PS2 interrupt, or RES pin input. When an external interrupt request signal is input, system clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding enable bit to 1. When clearing software standby mode with a KIN0 to KIN15 or WUE8 to WUE15 interrupt, enable the input. In these cases, ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ15 is generated. In the case of an IRQ0 to IRQ15 interrupt, software standby mode is not cleared if the corresponding enable bit is cleared to 0 or if the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE8 to WUE15 interrupt, software standby mode is not cleared if the input is disabled or if the interrupt has been masked by the CPU. Rev. 1.00 Apr. 28, 2008 Page 851 of 994 REJ09B0452-0100 Section 26 Power-Down Modes When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. Figure 26.2 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge of the NMI pin. Oscillator NMI NMIEG SSBY Software standby mode NMI exception (power-down mode) handling NMIEG = 1 SSBY = 1 Oscillation SLEEP instruction stabilization time tOSC2 NMI exception handling Figure 26.3 Software Standby Mode Application Example Rev. 1.00 Apr. 28, 2008 Page 852 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.6 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and on-chip peripheral modules other than CIR and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their values before transition as long as the prescribed voltage is supplied. Watch mode is cleared by an interrupt (WOVI1, NMI, IRQ0 to IRQ15, KIN0 to KIN15, or WUE8 to WUE15), PS2 interrupt, CIR interrupt, or RES pin input. When an interrupt occurs, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ15 interrupt, watch mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE8 to WUE15 interrupt, watch mode is not cleared if the input is disabled or the interrupt has been masked by the CPU. In the case of an interrupt from an on-chip peripheral module, watch mode is not cleared if the interrupt enable register has been set to disable the reception of that interrupt or the interrupt has been masked by the CPU. When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling. Rev. 1.00 Apr. 28, 2008 Page 853 of 994 REJ09B0452-0100 Section 26 Power-Down Modes 26.7 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cleared and module operation resumes at the end of the bus cycle. In module stop mode, the internal states of on-chip peripheral modules other than the SCI, PWM, PWMX, and A/D converter are retained. After the reset state is cancelled, all on-chip peripheral modules are in module stop mode. While an on-chip peripheral module is in module stop mode, its registers cannot be read from or written to. 26.8 26.8.1 Usage Notes I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, while a high level is output or the pull-up MOS is on, the current consumption is not reduced by the amount of current to support the high level output. 26.8.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. Rev. 1.00 Apr. 28, 2008 Page 854 of 994 REJ09B0452-0100 Section 27 List of Registers Section 27 List of Registers The list of registers gives information on the on-chip register addresses, how the register bits are configured, the register states in each operating mode, the register selection condition, and the register address of each module. The information is given as shown below. 1. * * * * * Register addresses (address order) Registers are listed from the lower allocation addresses. For the addresses of 16 bits, the MSB is described. Registers are classified by functional modules. The access size is indicated. H8S/2140B Group compatible register addresses or extended register addresses are selected depending on the RELOCATE bit in system control register 3 (SYSCR3). When the extended register addresses are selected, the some register addresses of ICC_1, TMR_Y, PWMX_0, and PORT are changed. Therefore, the selection with other module registers that share the same addresses with these registers is not necessary. 2. Register bits * Bit configurations of the registers are described in the same order as the register addresses in section 27.1, Register Addresses (Address Order). * Reserved bits are indicated by in the bit name column. * The bit number in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * Each line covers eight bits, and 16-bit register is shown as 2 lines, respectively. 3. Register states in each operating mode * Register states are described in the same order as the register addresses in section 27.1, Register Addresses (Address Order). * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, see the section on that on-chip peripheral module. 4. Register selection conditions * Register selection conditions are described in the same order as the register addresses in section 27.1, Register Addresses (Address Order). * For register selection conditions, see section 3.2.2, System Control Register (SYSCR), section 3.2.3, Serial Timer Control Register (STCR), section 26.1.3, Module Stop Control Registers H, L, A, and B (MSTPCRH, MSTPCRL, MSTPCRA, MSTPCRB), or register descriptions for each module. 5. Register addresses (classification by type of module) * The register addresses are described by modules * The register addresses are described in channel order when the module has multiple channels. Rev. 1.00 Apr. 28, 2008 Page 855 of 994 REJ09B0452-0100 Section 27 List of Registers 27.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits. The number of access states indicates the number of states based on the specified reference clock. Register Name Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Port 1 input data register Port 2 input data register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 3 input data register Port 4 input data register Port 3 pull-up MOS control register Abbreviation P1DDR P2DDR P1DR P2DR P1PIN P2PIN P1PCR P2PCR P3DDR P4DDR P3DR P4DR P3PIN P4PIN P3PCR Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F900 (PORTS = 1) H'F901 (PORTS = 1) H'F902 (PORTS = 1) H'F903 (PORTS = 1) H'F904 (Read) (PORTS = 1) H'F905 (Read) (PORTS = 1) H'F906 (PORTS = 1) H'F907 (PORTS = 1) H'F910 (PORTS = 1) H'F911 (PORTS = 1) H'F912 (PORTS = 1) H'F913 (PORTS = 1) H'F914 (Read) (PORTS = 1) H'F915 (Read) (PORTS = 1) H'F916 (PORTS = 1) Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 856 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F920 (PORTS = 1) H'F921 (PORTS = 1) H'F922 (PORTS = 1) H'F923 (PORTS = 1) H'F924 (Read) (PORTS = 1) H'F925 (Read) (PORTS = 1) H'F92B (PORTS = 1) H'F92D (PORTS = 1) H'F92F (PORTS = 1) H'F931 (PORTS = 1) H'F933 (PORTS = 1) H'F934 (Read) (PORTS = 1) H'F935 (Read) (PORTS = 1) H'F940 (PORTS = 1) H'F942 (PORTS = 1) H'F944 (Read) (PORTS = 1) H'F946 (PORTS = 1) H'F950 (PORTS = 1) Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port 5 input data register Port 6 input data register Abbreviation P5DDR P6DDR P5DR P6DR P5PIN P6PIN Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Port 6 noise canceler enable register P6NCE Port 6 noise canceler decision control register Port 6 noise cancel cycle setting register Port 8 data direction register Port 8 data register Port 7 input data register Port 8 input data register Port 9 data direction register Port 9 data register Port 9 input data register Port 9 pull-up MOS control register Port A data direction register P6NCMC P6NCCS P8DDR P8DR P7PIN P8PIN P9DDR P9DR P9PIN P9PCR PADDR Rev. 1.00 Apr. 28, 2008 Page 857 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F951 (PORTS = 1) H'F952 (PORTS = 1) H'F953 (PORTS = 1) H'F954 (Read) (PORTS = 1) H'F955 (Read) (PORTS = 1) H'F957 (PORTS = 1) H'F960 (PORTS = 1) H'F961 (PORTS = 1) H'F962 (PORTS = 1) H'F963 (PORTS = 1) H'F964 (Read) (PORTS = 1) H'F965 (Read) (PORTS = 1) H'F966 (PORTS = 1) H'F967 (PORTS = 1) H'F968 (PORTS = 1) H'F969 (PORTS = 1) H'F96A (PORTS = 1) H'F96C (PORTS = 1) H'F96E (PORTS = 1) Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port B data direction register Port A output data register Port B output data register Port A input data register Port B input data register Port B pull-up MOS control register Port C data direction register Port D data direction register Port C output data register Port D output data register Port C input data register Port D input data register Port C pull-up MOS control register Port D pull-up MOS control register Port C Nch-OD control register Port D Nch-OD control register Abbreviation PBDDR PAODR PBODR PAPIN PBPIN PBPCR PCDDR PDDDR PCODR PDODR PCPIN PDPIN PCPCR PDPCR PCNOCR PDNOCR Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Port C noise canceler enable register PCNCE Port C noise canceler decision control register Port C noise cancel cycle setting register PCNCMC PCNCCS Rev. 1.00 Apr. 28, 2008 Page 858 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'F971 (PORTS = 1) H'F973 (PORTS = 1) H'F974 (Read) (PORTS = 1) H'F975 (Read) (PORTS = 1) H'F977 (PORTS = 1) H'F979 (PORTS = 1) H'F980 (PORTS = 1) H'F981 (PORTS = 1) H'F982 (PORTS = 1) H'F983 (PORTS = 1) H'F984 (Read) (PORTS = 1) H'F985 (Read) (PORTS = 1) H'F987 (PORTS = 1) H'F988 (PORTS = 1) H'F989 (PORTS = 1) H'F98A (PORTS = 1) H'F98C (PORTS = 1) H'F98E (PORTS = 1) Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port F data direction register Port F output data register Port E input data register Port F input data register Port F pull-up MOS control register Port F Nch-OD control register Port G data direction register Port H data direction register Port G output data register Port H output data register Port G input data register Port H input data register Port H pull-up MOS control register Port G Nch-OD control register Port H Nch-OD control register Abbreviation PFDDR PFODR PEPIN PFPIN PFPCR PFNOCR PGDDR PHDDR PGODR PHODR PGPIN PHPIN PHPCR PGNOCR PHNOCR Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Port G noise canceler enable register PGNCE Port G noise canceler decision control register Port G noise cancel cycle setting register PGNCMC PGNCCS Rev. 1.00 Apr. 28, 2008 Page 859 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 8 8 8 8 H'F990 H'F991 H'F992 H'F993 H'F994 (Read) H'F995 (Read) H'F997 H'F998 H'F999 H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA48 H'FA4A H'FA4B H'FA4C H'FA4D H'FA4E H'FA4F H'FA50 H'FA51 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port I data direction register Port J data direction register Port I output data register Port J output data register Port I input data register Port J input data register Port J pull-up MOS control register Port I Nch-OD control register Port J Nch-OD control register Receive control register 1 Receive control register 2 Receive status register Interrupt enable register Bit rate register Receive data register 0 to 7 Header minimum high-level period register Header maximum high-level period register Header minimum low-level period register Header maximum low-level period register Abbreviation PIDDR PJDDR PIODR PJODR PIPIN PJPIN PJPCR PINOCR PJNOCR CCR1 CCR2 CSTR CEIR BRR CIRRDR0 to CIRRDR7 HHMIN HHMAX HLMIN HLMAX Module PORT PORT PORT PORT PORT PORT PORT PORT PORT CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR Data level 0 minimum period register DT0MIN Data level 0 maximum period register DT0MAX Data level 1 minimum period register DT1MIN Data level 1 maximum period register Repeat header minimum low-level period register Repeat header maximum low-level period register DT1MAX RMIN RMAX Rev. 1.00 Apr. 28, 2008 Page 860 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 H'FB40 H'FB42 H'FB44 H'FB46 H'FB48 H'FB4A H'FB4C H'FB4D H'FB4E H'FB4F H'FB50 H'FB60 H'FB62 H'FB64 H'FB66 H'FB68 H'FB6A H'FB6C H'FB6D H'FB6E H'FB6F H'FB70 H'FB80 H'FB82 H'FB84 H'FB86 Data Width 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name TDP timer counter_0 TDP pulse width upper limit register_0 TDP pulse width lower limit register_0 TDP cycle upper limit register_0 TDP input capture register_0 TDP input capture buffer register_0 TDP status register_0 TDP control register 1_0 TDP interrupt enable register_0 TDP control register 2_0 TDP cycle lower limit register_0 TDP timer counter_1 TDP pulse width upper limit register_1 TDP pulse width lower limit register_1 TDP cycle upper limit register_1 TDP input capture register_1 TDP input capture buffer register_1 TDP status register_1 TDP control register 1_1 TDP interrupt enable register_1 TDP control register 2_1 TDP cycle lower limit register_1 TDP timer counter_2 TDP pulse width upper limit register_2 TDP pulse width lower limit register_2 TDP cycle upper limit register_2 Abbreviation TDPCNT_0 TDPWDMX_0 TDPWDMN_0 TDPPDMX_0 TDPICR_0 TDPICRF_0 TDPCSR_0 TDPCR1_0 TDPIER_0 TDPCR2_0 TDPPDMN_0 TDPCNT_1 TDPWDMX_1 TDPWDMN_1 TDPPDMX_1 TDPICR_1 TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 TDPPDMN_1 TDPCNT_2 TDPWDMX_2 TDPWDMN_2 TDPPDMX_2 Module TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_2 TDP_2 TDP_2 TDP_2 Rev. 1.00 Apr. 28, 2008 Page 861 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 16 16 8 8 8 8 16 16 16 16 16 8 8 8 H'FB88 H'FB8A H'FB8C H'FB8D H'FB8E H'FB8F H'FB90 H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBCC H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FBDC H'FBE0 H'FBE2 H'FBE4 H'FBE6 H'FBE8 H'FBE9 H'FBEA H'FBEC H'FBF0 H'FBF2 Data Width 16 16 8 8 8 8 16 16 16 16 16 8 8 8 16 16 16 16 16 8 8 8 16 16 16 16 16 8 8 8 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name TDP input capture register_2 TDP input capture buffer register_2 TDP status register_2 TDP control register 1_2 TDP interrupt enable register_2 TDP control register 2_2 TDP cycle lower limit register_2 TCM timer counter_0 TCM cycle upper limit register TCM input capture register_0 TCM input capture buffer register_0 TCM status register_0 TCM control register_0 TCM interrupt enable register_0 TCM cycle lower limit register_0 TCM timer counter_1 TCM cycle upper limit register_0 TCM input capture register_1 TCM input capture buffer register_1 TCM status register_1 TCM control register_1 TCM interrupt enable register_1 TCM cycle lower limit register_1 TCM timer counter_2 TCM cycle upper limit register_2 TCM input capture register_2 TCM input capture buffer register_2 TCM status register_2 TCM control register_2 TCM interrupt enable register_2 TCM cycle lower limit register_2 TCM timer counter_3 TCM cycle upper limit register_3 Abbreviation TDPICR_2 TDPICRF_2 TDPCSR_2 TDPCR1_2 TDPIER_2 TDPCR2_2 TDPPDMN_2 TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 Module TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_3 TCM_3 TCMMINCM_0 16 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 16 16 16 16 8 8 8 TCMMINCM_1 16 TCMCNT_2 TCMMLCM_2 TCMICR_2 TCMICRF_2 TCMCSR_2 TCMCR_2 TCMIER_2 16 16 16 16 8 8 8 TCMMINCM_2 16 TCMCNT_3 TCMMLCM_3 16 16 Rev. 1.00 Apr. 28, 2008 Page 862 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 16 16 8 8 8 H'FBF4 H'FBF6 H'FBF8 H'FBF9 H'FBFA H'FBFC H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC11 H'FC20 H'FC20 H'FC20 H'FC21 H'FC21 H'FC22 H'FC22 H'FC23 H'FC24 H'FC25 Data Width 16 16 8 8 8 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name TCM input capture register_3 TCM input capture buffer register_3 TCM status register_3 TCM control register_3 TCM interrupt enable register_3 TCM cycle lower limit register_3 A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register A/D control register Receive buffer register Transmitter holding register Divisor latch L Interrupt enable register Divisor latch H Interrupt identification register FIFO control register Line control register Modem control register Line status register Abbreviation TCMICR_3 TCMICRF_3 TCMCSR_3 TCMCR_3 TCMIER_3 Module TCM_3 TCM_3 TCM_3 TCM_3 TCM_3 TCM_3 TCMMINCM_3 16 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter A/D 16 converter SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 863 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FC26 H'FC27 H'FC28 H'FC50 H'FC51 H'FC52 H'FC53 H'FC54 H'FC55 H'FC56 H'FC57 H'FC58 H'FC59 H'FC5A H'FC5B H'FC5C H'FC5D H'FC5E H'FC5F H'FC60 H'FC61 H'FC62 H'FC63 H'FC64 H'FC65 H'FC66 H'FC67 H'FC68 H'FC69 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Modem status register Scratch pad register SCIF control register FSI access host base address register H FSI access host base address register L FSI flash memory size register FSI command host base address register H FSI command host base address register L FSI command register FSILPC command status register 1 FSI general-purpose register 1 FSI general-purpose register 2 FSI general-purpose register 3 FSI general-purpose register 4 FSI general-purpose register 5 FSI general-purpose register 6 FSI general-purpose register 7 FSI general-purpose register 8 FSI general-purpose register 9 FSI general-purpose register A FSI general-purpose register B FSI general-purpose register C FSI general-purpose register D FSI general-purpose register E FSI general-purpose register F FSILPC control register FSI address register H FSI address register M FSI address register L Abbreviation FMSR FSCR SCIFCR FSIHBARH FSIHBARL FSISR CMDHBARH CMDHBARL FSICMDR FSILSTR1 FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL Module SCIF SCIF SCIF FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI Rev. 1.00 Apr. 28, 2008 Page 864 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FC6A H'FC6B H'FC6C H'FC6D H'FC6E H'FC90 H'FC91 H'FC92 H'FC93 H'FC94 H'FC95 H'FC96 H'FC98 H'FC99 H'FC9A H'FC9B H'FC9C H'FC9D H'FC9E H'FC9F H'FCA0 H'FD00 H'FD01 H'FD02 H'FD03 H'FD04 H'FD05 H'FD06 H'FD07 H'FD08 H'FD09 H'FD0A Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name FSI write data register HH FSI write data register HL FSI write data register LH FSI write data register LL FSILPC command status register 2 FSI control register 1 FSI control register 2 FSI byte count register FSI instruction register FSI read instruction register FSI program instruction register FSI status register FSI transmit data register 0 FSI transmit data register 1 FSI transmit data register 2 FSI transmit data register 3 FSI transmit data register 4 FSI transmit data register 5 FSI transmit data register 6 FSI transmit data register 7 FSI receive data register PWM duty setting register 0_A PWM prescaler register 0_A PWM duty setting register 1_A PWM prescaler register 1_A PWM duty setting register 2_A PWM prescaler register 2_A PWM duty setting register 3_A PWM prescaler register 3_A PWM duty setting register 4_A PWM prescaler register 4_A PWM duty setting register 5_A Abbreviation FSIWDRHH FSIWDRHL FSIWDRLH FSIWDRLL FSILSTR2 FSICR1 FSICR2 FSIBNR FSIINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR Module FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI PWMREG0_A 8 PWMPRE0_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMREG1_A 8 PWMPRE1_A 8 PWMREG2_A 8 PWMPRE2_A 8 PWMREG3_A 8 PWMPRE3_A 8 PWMREG4_A 8 PWMPRE4_A 8 PWMREG5_A 8 Rev. 1.00 Apr. 28, 2008 Page 865 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 H'FD0B H'FD0C H'FD0D H'FD0E H'FD0F H'FD10 H'FD11 H'FD12 H'FD13 H'FD14 H'FD15 H'FD16 H'FD17 H'FD18 H'FD19 H'FD1A H'FD1B H'FD1C H'FD1D H'FD1E H'FD1F H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A H'FDC0 H'FDC1 H'FDC2 H'FDC3 Data Width Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name PWM prescaler register 5_A PWM control register A_A PWM control register B_A PWM control register C_A PWM control register D_A PWM duty setting register 0_B PWM prescaler register 0_B PWM duty setting register 1_B PWM prescaler register 1_B PWM duty setting register 2_B PWM prescaler register 2_B PWM duty setting register 3_B PWM prescaler register 3_B PWM duty setting register 4_B PWM prescaler register 4_B PWM duty setting register 5_B PWM prescaler register 5_B PWM control register A_B PWM control register B_B PWM control register C_B PWM control register D_B Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter _1 Timer general register A_1 Timer general register B_1 LPC channel 1 address register H LPC channel 1 address register L LPC channel 2 address register H LPC channel 2 address register L Abbreviation PWMPRE5_A Module PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_A 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 PWMU_B 8 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 LPC LPC LPC LPC 8 8 8 8 8 16 16 16 8 8 8 8 PWMCONA_A 8 PWMCONB_A 8 PWMCONC_A 8 PWMCOND_A 8 PWMREG0_B 8 PWMPRE0_B 8 PWMREG1_B 8 PWMPRE1_B 8 PWMREG2_B 8 PWMPRE2_B 8 PWMREG3_B 8 PWMPRE3_B 8 PWMREG4_B 8 PWMPRE4_B 8 PWMREG5_B 8 PWMPRE5_B 8 PWMCONA_B 8 PWMCONB_B 8 PWMCONC_B 8 PWMCOND_B 8 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 LADR1H LADR1L LADR2H LADR2L 8 8 8 8 8 16 16 16 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 866 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FDC4 H'FDC5 H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FDDB H'FE00 (PORTS = 0) H'FE01 (PORTS = 0) H'FE02 (PORTS = 0) H'FE03 (PORTS = 0) H'FE04 (PORTS = 0) H'FE05 (PORTS = 0) H'FE06 (PORTS = 0) H'FE07 (PORTS = 0) H'FE08 (PORTS = 0) H'FE0C (Read) (PORTS = 0) H'FE0C (Write) (PORTS = 0) H'FE0D (PORTS = 0) H'FE0E (PORTS = 0) H'FE10 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name SCIF address register H SCIF address register L LPC channel 4 address register H LPC channel 4 address register L Input data register 4 Output data register 4 Status register 4 Host interface control register 4 SERIRQ control register 2 SERIRQ control register 3 Abbreviation SCIFADRH SCIFADRL LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 SIRQCR3 Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Port 6 noise canceler enable register P6NCE Port 6 noise canceler decision control register Port 6 noise cancel cycle setting register P6NCMC P6NCCS Port C noise canceler enable register PCNCE Port C noise canceler decision control register Port C noise cancel cycle setting register PCNCMC PCNCCS Port G noise canceler enable register PGNCE Port G noise canceler decision control register Port G noise cancel cycle setting register Port H input data register Port H data direction register Port H output data register Port H Nch-OD control register Port control register 0 PGNCMC PGNCCS PHPIN PHDDR PHODR PHNOCR PTCNT0 Rev. 1.00 Apr. 28, 2008 Page 867 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE11 H'FE12 H'FE14 (PORTS = 0) H'FE16 (PORTS = 0) H'FE19 (PORTS = 0) H'FE1C (PORTS = 0) H'FE1D (PORTS = 0) H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 H'FE33 H'FE34 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port control register 1 Port control register 2 Port 9 pull-up MOS control register Port G Nch-OD control register Port F Nch-OD control register Port C Nch-OD control register Port D Nch-OD control register Bidirectional data register 0MW Bidirectional data register 0SW Bidirectional data register 1 Bidirectional data register 2 Bidirectional data register 3 Bidirectional data register 4 Bidirectional data register 5 Bidirectional data register 6 Bidirectional data register 7 Bidirectional data register 8 Bidirectional data register 9 Bidirectional data register 10 Bidirectional data register 11 Bidirectional data register 12 Bidirectional data register 13 Bidirectional data register 14 Bidirectional data register 15 Input data register 3 Output data register 3 Status register 3 Host interface control register 5 LPC channel 3 address register H Abbreviation PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 HICR5 LADR3H Module PORT PORT PORT PORT PORT PORT PORT LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC Rev. 1.00 Apr. 28, 2008 Page 868 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3C H'FE3B H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE45 H'FE46 (PORTS = 0) H'FE47 (Read) (PORTS = 0) H'FE47 (Write) (PORTS = 0) H'FE49 (PORTS = 0) Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name LPC channel 3 address register L SERIRQ control register 0 SERIRQ control register 1 Input data register 1 Output data register 1 Status register 1 Input data register 2 SERIRQ control register 4 Output data register 2 Status register 2 Host interface select register Host interface control register 0 Host interface control register 1 Host interface control register 2 Host interface control register 3 Wakeup event interrupt mask register Port G output data register Port G input data register Port G data direction register Port F output data register Port E input data register Abbreviation LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 IDR2 SIRQCR4 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMR PGODR PGPIN PGDDR PFODR PEPIN Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC INT PORT PORT PORT PORT H'FE4A (Read) PORT (write prohibited) (PORTS = 0) H'FE4B (Read) (PORTS = 0) H'FE4B (Write) (PORTS = 0) H'FE4C (PORTS = 0) H'FE4D (PORTS = 0) PORT PORT PORT PORT Port F input data register Port F data direction register Port C output data register Port D output data register PFPIN PFDDR PCODR PDODR 8 8 8 8 8 8 8 8 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 869 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 H'FE4E (Read) (PORTS = 0) H'FE4E (Write) (PORTS = 0) H'FE4F (Read) (PORTS = 0) H'FE4F (Write) (PORTS = 0) H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FE7D H'FE7E H'FE7F Data Width 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port C input data register Port C data direction register Port D input data register Port D data direction register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter _0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter _2 Timer general register A_2 Timer general register B_2 System control register 3 Module stop control register A Module stop control register B Keyboard matrix interrupt register Pull-up MOS control register Abbreviation PCPIN PCDDR PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA MSTPCRB KMIMR KMPCR Module PORT PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 SYSTEM 8 SYSTEM 8 SYSTEM 8 8 8 H'FE81 INT (RELOCATE = 1) H'FE82 PORT (RELOCATE = 1) Rev. 1.00 Apr. 28, 2008 Page 870 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Keyboard matrix interrupt register A Wake-up sense control register Wake-up input interrupt status register Wake-up enable register Interrupt control register D I C bus control register_2 I C bus status register_2 I C bus control Initialization register_2 I C bus control extended register_2 I C bus data register_2 Second slave address register_2 I C bus mode register_2 Slave address register_2 PWMX(D/A) control register PWMX(D/A) data register AH PWMX(D/A) data register AL PWMX(D/A) data register BH PWMX(D/A) counter H PWMX(D/A) data register BL PWMX(D/A) counter L Flash code control status register Flash program code select register Flash erace code select register Flash key code register Flash MAT select register 2 2 2 2 2 2 Abbreviation KMIMRA WUESCR WUESR WER ICRD ICCR_2 ICSR_2 ICRES_2 ICXR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 DACR DADRAH DADRAL DADRBH DACNTH DADRBL DACNTL FCCS FPCS FECS FKEY FMATS Module H'FE83 INT (RELOCATE = 1) H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8C H'FE8E H'FE8E H'FE8F H'FE8F INT INT INT INT IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 H'FEA0 PWMX (RELOCATE = 1) H'FEA0 PWMX (RELOCATE = 1) H'FEA1 PWMX (RELOCATE = 1) H'FEA6 PWMX (RELOCATE = 1) H'FEA6 PWMX (RELOCATE = 1) H'FEA7 PWMX (RELOCATE = 1) H'FEA7 PWMX (RELOCATE = 1) H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD ROM ROM ROM ROM ROM Rev. 1.00 Apr. 28, 2008 Page 871 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEAE H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 Data Width 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Flash transfer destination address register Timer start register Timer synchro register Keyboard control register 1_0 Keyboard data buffer transmit data register_0 Keyboard control register 1_1 Keyboard data buffer transmit data register_1 Keyboard control register 1_2 Keyboard data buffer transmit data register_2 Timer XY control register Timer control register_Y Timer control/status register_Y Time constant register A_Y Time constant register B_Y Timer counter _Y I C bus data register_1 2 Abbreviation FTDAR TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y ICDR_1 Module ROM TPU common TPU common PS2_0 PS2_0 PS2_1 PS2_1 PS2_2 PS2_2 TMR_XY 8 8 8 8 8 8 8 H'FEC8 TMR_Y (RELOCATE = 1) H'FEC9 TMR_Y (RELOCATE = 1) H'FECA TMR_Y (RELOCATE = 1) H'FECB TMR_Y (RELOCATE = 1) H'FECC TMR_Y (RELOCATE = 1) H'FECE (RELOCATE = 1) IIC_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 I C bus control register_1 I C bus status register_1 2 2 2 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 8 8 8 8 8 H'FECE IIC_1 (RELOCATE = 1) H'FECF IIC_1 (RELOCATE = 1) H'FECF IIC_1 (RELOCATE = 1) H'FED0 IIC_1 (RELOCATE = 1) H'FED1 IIC_1 (RELOCATE = 1) 8 8 8 8 8 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 872 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FED2 H'FED3 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FF88 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Keyboard control register 1_3 Keyboard data buffer transmit data register_3 I C bus control extended register_0 I C bus control extended register_1 Keyboard control register H_0 Keyboard control register L_0 Keyboard data buffer register_0 Serial mode register_1 I C bus control register_1 Bit rate register_1 I C bus status register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 I C bus data register_1 Second slave address register_1 I C bus mode register_1 Slave address register_1 PWMX(D/A) control register PWMX(D/A) data register AH Serial mode register_2 PWMX(D/A) data register AL Bit rate register_2 Serial control register_2 2 2 2 2 2 2 Abbreviation KBCR1_3 KBTR_3 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 SMR_1 ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 DACR DADRAH SMR_2 DADRAL BRR_2 SCR_2 Module PS2_3 PS2_3 IIC_0 IIC_1 PS2_0 PS2_0 PS2_0 SCI_1 H'FF88 IIC_1 (RELOCATE = 0) H'FF89 SCI_1 H'FF89 IIC_1 (RELOCATE = 0) H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 H'FF8E IIC_1 (RELOCATE = 0) H'FF8E IIC_1 (RELOCATE = 0) H'FF8F IIC_1 (RELOCATE = 0) H'FF8F IIC_1 (RELOCATE = 0) H'FFA0 PWMX (RELOCATE = 0) H'FFA0 PWMX (RELOCATE = 0) H'FFA0 SCI_2 H'FFA1 PWMX (RELOCATE = 0) H'FFA1 H'FFA2 SCI_2 SCI_2 Rev. 1.00 Apr. 28, 2008 Page 873 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFA3 H'FFA4 H'FFA5 H'FFA6 Data Width 8 8 8 8 8 8 8 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 PWMX(D/A) counter H PWMX(D/A) data register BH PWMX(D/A) counter L PWMX(D/A) data register BL Timer control/status register_0 Timer control/status register_0 Timer counter _0 Timer counter _0 Port A output data register Port A input data register Port A data direction register Port 1 pull-up MOS control register Port 2 pull-up MOS control register Port 3 pull-up MOS control register Port 1 data direction register Port 2 data direction register Port 1 data register Port 2 data register Abbreviation TDR_2 SSR_2 RDR_2 SCMR_2 DACNTH DADRBH DACNTL DADRBL TCSR_0 TCSR_0 TCNT_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR Module SCI_2 SCI_2 SCI_2 SCI_2 H'FFA6 PWMX (RELOCATE = 0) H'FFA6 PWMX (RELOCATE = 0) H'FFA7 PWMX (RELOCATE = 0) H'FFA7 PWMX (RELOCATE = 0) H'FFA8 (Write) H'FFA8 (Read) H'FFA8 (Write) H'FFA9 (Read) H'FFAA (PORTS = 0) H'FFAB (Read) (PORTS = 0) H'FFAB (Write) (PORTS = 0) H'FFAC (PORTS = 0) H'FFAD (PORTS = 0) H'FFAE (PORTS = 0) H'FFB0 (PORTS = 0) H'FFB1 (PORTS = 0) H'FFB2 (PORTS = 0) H'FFB3 (PORTS = 0) WDT_0 WDT_0 WDT_0 WDT_0 PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Rev. 1.00 Apr. 28, 2008 Page 874 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFB4 (PORTS = 0) H'FFB5 (PORTS = 0) H'FFB6 (PORTS = 0) H'FFB7 (PORTS = 0) H'FFB8 (PORTS = 0) H'FFB9 (PORTS = 0) H'FFBA (PORTS = 0) H'FFBB (PORTS = 0) H'FFBC (PORTS = 0) H'FFBD (Write) (PORTS = 0) H'FFBD (Read) (PORTS = 0) H'FFBE (Read) (PORTS = 0) H'FFBE (Write) (PORTS = 0) H'FFBF (PORTS = 0) H'FFC0 (PORTS = 0) H'FFC1 (PORTS = 0) H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port 3 data direction register Port 4 data direction register Port 3 data register Port 4 data register Port 5 data direction register Port 6 data direction register Port 5 data register Port 6 data register Port B output data register Port 8 data direction register Port B input data register Port 7 input data register Port B data direction register Port 8 data register Port 9 data direction register Port 9 data register Interrupt enable register Serial timer control register System control register Mode control register Bus control register Wait state control register Abbreviation P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR PBPIN P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT INT SYSTEM 8 SYSTEM 8 SYSTEM 8 BSC BSC 8 8 Rev. 1.00 Apr. 28, 2008 Page 875 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD8 H'FFD9 H'FFDE H'FFDE H'FFDF H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFEA (Write) H'FFEA (Read) H'FFEA (Write) H'FFEB (Read) H'FFF0 Data Width 8 8 8 8 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 8 16 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter _0 Timer counter _1 I C bus control register_0 I C bus status register_0 I C bus data register_0 Second slave address register_0 I C bus mode register_0 Slave address register_0 Keyboard control register H_3 Keyboard control register L_3 Keyboard data buffer register_3 Keyboard control register 2_3 Timer control/status register Timer control/status register Timer counter _1 Timer counter _1 Timer control register_X Timer control register_Y Keyboard matrix interrupt register Timer control/status register_X Timer control/status register_Y Pull-up MOS control register 2 2 2 2 Abbreviation TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 KBCRH_3 KBCRL_3 KBBR_3 KBCR2_3 TCSR_1 TCSR_1 TCNT_1 TCNT_1 TCR_X TCR_Y KMIMR TCSR_X TCSR_Y KMPCR Module TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 IIC_0 PS2_3 PS2_3 PS2_3 PS2_3 WDT_1 WDT_1 WDT_1 WDT_1 TMR_X H'FFF0 TMR_Y (RELOCATE = 0) H'FFF1 INT (RELOCATE = 0) H'FFF1 TMR_X H'FFF1 TMR_Y (RELOCATE = 0) H'FFF2 PORT (RELOCATE = 0) Rev. 1.00 Apr. 28, 2008 Page 876 of 994 REJ09B0452-0100 Section 27 List of Registers Number Address of bits 8 8 8 8 8 8 8 8 8 8 8 8 H'FFF2 Data Width 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Input capture register R Time constant register A_Y Input capture register F Time constant register B_Y Keyboard matrix interrupt register A Timer counter _X Timer counter _Y Time constant register C Time constant register A_X Time constant register B_X Timer connection register I Timer connection register S Abbreviation TICRR TCORA_Y TICRF TCORB_Y KMIMRA TCNT_X TCNT_Y TCORC TCORA_X TCORB_X TCONRI TCONRS Module TMR_X H'FFF2 TMR_Y (RELOCATE = 0) H'FFF3 TMR_X H'FFF3 TMR_Y (RELOCATE = 0) H'FFF3 INT (RELOCATE = 0) H'FFF4 TMR_X H'FFF4 TMR_Y (RELOCATE = 0) H'FFF5 H'FFF6 H'FFF7 H'FFFC H'FFFE TMR_X TMR_X TMR_X TMR_X TMR_X, TMR_Y Rev. 1.00 Apr. 28, 2008 Page 877 of 994 REJ09B0452-0100 Section 27 List of Registers 27.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbreviation PIDDR PJDDR PIODR PJODR PIPIN PJPIN PJPCR PINOCR PJNOCR CCR1 CCR2 CSTR CEIR BRR Bit 7 PI7DDR PJ7DDR PI7ODR PJ7ODR PI7PIN PJ7PIN PJ7PCR PI7NOCR Bit 6 PI6DDR PJ6DDR PI6ODR PJ6ODR PI6PIN PJ6PIN PJ6PCR PI6NOCR Bit 5 PI5DDR PJ5DDR PI5ODR PJ5ODR PI5PIN PJ5PIN PJ5PCR PI5NOCR Bit 4 PI4DDR PJ4DDR PI4ODR PJ4ODR PI4PIN PJ4PIN PJ4PCR PI4NOCR Bit 3 PI3DDR PJ3DDR PI3ODR PJ3ODR PI3PIN PJ3PIN PJ3PCR PI3NOCR Bit 2 PI2DDR PJ2DDR PI2ODR PJ2ODR PI2PIN PJ2PIN PJ2PCR PI2NOCR Bit 1 PI1DDR PJ1DDR PI1ODR PJ1ODR PI1PIN PJ1PIN PJ1PCR PI1NOCR Bit 0 PI0DDR PJ0DDR PI0ODR PJ0ODR PI0PIN PJ0PIN PJ0PCR PI0NOCR Module PORT PJ7NOCR PJ6NOCR PJ5NOCR PJ4NOCR PJ3NOCR PJ2NOCR PJ1NOCR PJ0NOCR CIRE TFM1 CIRBUSY BRR7 SRES TFM0 CIRRDRF BRR6 CIRRDR6 RFMBIN3 HHMIN6 FLT0 HHMAX6 HLMIN6 HLMAX6 DT1MIN6 DT1MAX6 DT0MIN6 DT0MAX6 RMIN6 RMAX6 CPHS REPF REPIE BRR5 CIRRDR5 RFMBIN2 HHMIN5 FLTE HHMAX5 HLMIN5 HLMAX5 DT1MIN5 DT1MAX5 DT0MIN5 DT0MAX5 RMIN5 RMAX5 MLS OVRF OVEIE BRR4 CIRRDR4 RFMBIN1 HHMIN4 FLTCK1 HHMAX4 HLMIN4 HLMAX4 DT1MIN4 DT1MAX4 DT0MIN4 DT0MAX4 RMIN4 RMAX4 REPRCVE REND RENDIE BRR3 CIRRDR3 RFMBIN0 HHMIN3 FLTCK0 HHMAX3 HLMIN3 HLMAX3 DT1MIN3 DT1MAX3 DT0MIN3 DT0MAX3 RMIN3 RMAX3 ABF ABIE BRR2 CIRRDR2 HHMIN2 HHMAX2 HLMIN2 HLMAX2 DT1MIN2 DT1MAX2 DT0MIN2 DT0MAX2 RMIN2 RMAX2 CLK1 FRF FREIE BRR1 CIRRDR1 HHMIN9 HHMIN1 HHMAX9 HHMAX1 HLMIN1 HLMAX1 DT1MIN1 DT1MAX1 DT0MIN1 DT0MAX1 RMIN1 RMAX1 CLK0 HEADF HEADFIE BRR0 CIRRDR0 HHMIN8 HHMIN0 HHMAX8 HHMAX0 HLMIN0 HLMAX0 DT1MIN0 DT1MAX0 DT0MIN0 DT0MAX0 RMIN0 RMAX0 CIR CIRRDR0 to 7 CIRRDR7 HHMIN RFMBIN4 HHMIN7 HHMAX FLT1 HHMAX7 HLMIN HLMAX DT1MIN DT1MAX DT0MIN DT0MAX RMIN RMAX HLMIN7 HLMAX7 DT1MIN7 DT1MAX7 DT0MIN7 DT0MAX7 RMIN7 RMAX7 Rev. 1.00 Apr. 28, 2008 Page 878 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TDPCNT_0 Bit 7 bit 15 bit 7 TDPPDMX_0 bit 15 bit 7 TDPPDMN_0 bit 15 bit 7 TDPWDMX_0 bit 15 bit 7 TDPICR_0 bit 15 bit 7 TDPICRF_0 bit 15 bit 7 TDPCSR_0 TDPCR1_0 TDPIER_0 TDPCR2_0 OVF CST OVIE PMMS Bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 Bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 Bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 Bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 ICPF TDPMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 Bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 CMF CKS2 CMIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 Bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 CKSEG CKS1 TDPIPE bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 Bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 TPDMNUDF Module TDP_0 TWDMXOVF TWDMNUDF TPDMXOVF POCTL CPSPE IEDG CKS0 TPDMNIE bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 TDP_1 TWDMXIE TWDMNIE TPDMXIE MCICTL bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 TDPWDMN_0 bit 15 bit 7 TDPCNT_1 bit 15 bit 7 TDPPDMX_1 bit 15 bit 7 TDPPDMN_1 bit 15 bit 7 TDPWDMX_1 bit 15 bit 7 TDPICR_1 bit 15 bit 7 TDPICRF_1 bit 15 bit 7 Rev. 1.00 Apr. 28, 2008 Page 879 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 Bit 7 OVF CST OVIE PMMS Bit 6 Bit 5 Bit 4 Bit 3 ICPF TDPMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 ICPF TDPMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 Bit 2 CMF CKS2 CMIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 CMF CKS2 CMIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 Bit 1 CKSEG CKS1 TDPIPE bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 CKSEG CKS1 TDPIPE bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 Bit 0 TPDMNUDF Module TDP_1 TWDMXOVF TWDMNUDF TPDMXOVF POCTL CPSPE IEDG CKS0 TPDMNIE bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 TPDMNUDF TWDMXIE TWDMNIE TPDMXIE MCICTL bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 TDPWDMN_1 bit 15 bit 7 TDPCNT_2 bit 15 bit 7 TDPPDMX_2 bit 15 bit 7 TDPPDMN_2 bit 15 bit 7 TDPWDMX_2 bit 15 bit 7 TDPICR_2 bit 15 bit 7 TDPICRF_2 bit 15 bit 7 TDPCSR_2 TDPCR1_2 TDPIER_2 TDPCR2_2 OVF CST OVIE PMMS TDP_2 TWDMXOVF TWDMNUDF TPDMXOVF POCTL CPSPE IEDG CKS0 TPDMNIE bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 TCM_0 TWDMXIE TWDMNIE TPDMXIE MCICTL bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 TDPWDMN_2 bit 15 bit 7 TCMCNT_0 bit 15 bit 7 TCMMLCM_0 bit 15 bit 7 TCMICR_0 bit 15 bit 7 TCMICRF_0 bit 15 bit 7 Rev. 1.00 Apr. 28, 2008 Page 880 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TCMCSR_0 TCMCR_0 TCMIER_0 Bit 7 OVF CST OVIE Bit 6 MAXOVF POCTL MAXOVIE bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 MAXOVF POCTL MAXOVIE bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 MAXOVF POCTL MAXOVIE bit 14 bit 6 Bit 5 CMF CPSPE CMIE bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 CMF CPSPE CMIE bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 CMF CPSPE CMIE bit 13 bit 5 Bit 4 CKSEG IEDG TCMIPE bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 CKSEG IEDG TCMIPE bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 CKSEG IEDG TCMIPE bit 12 bit 4 Bit 3 ICPF TCMMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 ICPF TCMMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 ICPF TCMMDS ICPIE bit 11 bit 3 Bit 2 MINUDF CKS2 MINUDIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 MINUDF CKS2 MINUDIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 MINUDF CKS2 MINUDIE bit 10 bit 2 Bit 1 MCICTL CKS1 CMMS bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 MCICTL CKS1 CMMS bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 MCICTL CKS1 CMMS bit 9 bit 1 Bit 0 CKS0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 CKS0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 CKS0 bit 8 bit 0 TCM_2 TCM_1 Module TCM_0 TCMMINCM_0 bit 15 bit 7 TCMCNT_1 bit 15 bit 7 TCMMLCM_1 bit 15 bit 7 TCMICR_1 bit 15 bit 7 TCMICRF_1 bit 15 bit 7 TCMCSR_1 TCMCR_1 TCMIER_1 OVF CST OVIE TCMMINCM_1 bit 15 bit 7 TCMCNT_2 bit 15 bit 7 TCMMLCM_2 bit 15 bit 7 TCMICR_2 bit 15 bit 7 TCMICRF_2 bit 15 bit 7 TCMCSR_2 TCMCR_2 TCMIER_2 OVF CST OVIE TCMMINCM_2 bit 15 bit 7 Rev. 1.00 Apr. 28, 2008 Page 881 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TCMCNT_3 Bit 7 bit 15 bit 7 TCMMLCM_3 bit 15 bit 7 TCMICR_3 bit 15 bit 7 TCMICRF_3 bit 15 bit 7 TCMCSR_3 TCMCR_3 TCMIER_3 OVF CST OVIE Bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 MAXOVF POCTL MAXOVIE bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 ADIE TRGS0 Bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 CMF CPSPE CMIE bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 ADST SCANE Bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 CKSEG IEDG TCMIPE bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 SCANS Bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 ICPF TCMMDS ICPIE bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 CH3 CKS1 Bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 MINUDF CKS2 MINUDIE bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 CH2 CKS0 Bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 MCICTL CKS1 CMMS bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 CH1 Bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 CKS0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 CH0 A/D converter Module TCM_3 TCMMINCM_3 bit 15 bit 7 ADDRA bit 15 bit 7 ADDRB bit 15 bit 7 ADDRC bit 15 bit 7 ADDRD bit 15 bit 7 ADDRE bit 15 bit 7 ADDRF bit 15 bit 7 ADDRG bit 15 bit 7 ADDRH bit 15 bit 7 ADCSR ADCR ADF TRGS1 ADSTCLR Rev. 1.00 Apr. 28, 2008 Page 882 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR FSIHBARH FSIHBARL FSISR CMDHBARH CMDHBARL FSICMDR FSILSTR1 FSILSTR2 FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB Bit 7 bit 7 bit 7 bit 7 bit 7 FIFOE1 Bit 6 bit 6 bit 6 bit 6 bit 6 FIFOE0 Bit 5 bit 5 bit 5 bit 5 bit 5 Bit 4 bit 4 bit 4 bit 4 bit 4 EPS LOOPBACK Bit 3 bit 3 bit 3 bit 3 EDSSI bit 3 INTID2 DMAMODE Bit 2 bit 2 bit 2 bit 2 ELSI bit 2 INTID1 XMITFRST Bit 1 bit 1 bit 1 bit 1 ETBEI bit 1 INTID0 RCVRFRST Bit 0 bit 0 bit 0 bit 0 ERBFI bit 0 INTPEND FIFOE CLS0 DTR DR DCTS bit 0 REGRST bit24 bit16 FSIMS0 bit24 bit16 bit0 SIZE0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 Module SCIF RCVRTRIG1 RCVRTRIG0 DLAB BREAK STICKPARITY PEN OUT2 FE DDCD bit 3 CKSEL1 bit27 bit19 bit27 bit19 bit3 YFSIWI STOP OUT1 PE TERI bit 2 CKSEL0 bit26 bit18 bit26 bit18 bit2 LFBUSY CLS1 RTS OE DDSR bit 1 SCIFRST bit25 bit17 FSIMS1 bit25 bit17 bit1 SIZE1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 THRE DSR bit 5 bit29 bit21 bit29 bit21 bit5 FSIDMYE bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 RXFIFOERR TEMT BI CTS bit 4 OUT2LOOP DCD bit 7 SCIFOE1 bit31 bit23 bit31 bit23 bit7 RI bit 6 SCIFOE0 bit30 bit22 bit30 bit22 bt6 bit28 bit20 bit28 bit20 bit4 FSIWBUS FSIDWBUSY FSI CMDBUSY FSICMDI bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 FSIDRBUSY SIZE2 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 Rev. 1.00 Apr. 28, 2008 Page 883 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL FSIWDRHH FSIWDRHL FSIWDRLH FSIWDRLL FSICR1 FSICR2 FSIBNR FSINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR Bit 7 bit7 bit7 bit7 bit7 FSILE bit23 bit15 bit7 bit31 bit23 bit15 bit7 SRES TE TBN3 bit7 bit7 bit7 FSITEI bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 bit7 Bit 6 bit6 bit6 bit6 bit6 Bit 5 bit5 bit5 bit5 bit5 Bit 4 bit4 bit4 bit4 bit4 Bit 3 bit3 bit3 bit3 bit3 Bit 2 bit2 bit2 bit2 bit2 bit18 bit10 bit2 bit26 bit18 bit10 bit2 CPOS RBN2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 bit2 Bit 1 bit1 bit1 bit1 bit1 bit17 bit9 bit1 bit25 bit17 bit9 bit1 RBN1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 bit1 Bit 0 bit0 bit0 bit0 bit0 bit16 bit8 bit0 bit24 bit16 bit8 bit0 CKSEL RBN0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 bit0 Module FSI FSICMDIE FSIWIE bit22 bit14 bit6 bit30 bit22 bit14 bit6 FSIE RE TBN2 bit6 bit6 bit6 OBF bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit6 bit21 bit13 bit5 bit29 bit21 bit13 bit5 FRDE FSITEIE TBN1 bit5 bit5 bit5 FSIRXI bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 bit5 FSIWDRLL FSICR1 bit20 bit12 bit4 bit28 bit20 bit12 bit4 AAIE FSIRXIE TBN0 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit4 bit19 bit11 bit3 bit27 bit19 bit11 bit3 CPHS bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 bit3 Rev. 1.00 Apr. 28, 2008 Page 884 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 CLK0 Bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 PWM5E Bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 PWM4E PWMSL4 PH2S bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 PWM4E PWMSL4 PH2S Bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 PWM3E PWMSL3 PH1S bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 PWM3E PWMSL3 PH1S Bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 PWM2E PWMSL2 PH0S bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 PWM2E PWMSL2 PH0S Bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 PWM1E PWMSL1 Bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 PWM0E PWMSL0 Module PWMU_A PWMREG0_A bit 7 PWMPRE0_A bit 7 PWMREG1_A bit 7 PWMPRE1_A bit 7 PWMREG2_A bit 7 PWMPRE2_A bit 7 PWMREG3_A bit 7 PWMPRE3_A bit 7 PWMREG4_A bit 7 PWMPRE4_A bit 7 PWMREG5_A bit 7 PWMPRE5_A bit 7 PWMCONA_A CLK1 PWMCONB_A PWMCONC_A PWMCOND_A PH5S PWMREG0_B bit 7 PWMPRE0_B bit 7 PWMREG1_B bit 7 PWMPRE1_B bit 7 PWMREG2_B bit 7 PWMPRE2_B bit 7 PWMREG3_B bit 7 PWMPRE3_B bit 7 PWMREG4_B bit 7 PWMPRE4_B bit 7 PWMREG5_B bit 7 PWMPRE5_B bit 7 PWMCONA_B CLK1 PWMCONB_B PWMCONC_B PWMCOND_B PH5S CNTMD01 PWMSL5 PH4S bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 CLK0 PH3S bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 PWM5E CNTMD45 CNTMD23 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 PWM1E PWMSL1 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 PWM0E PWMSL0 PWMU_B CNTMD01 PWMSL5 PH4S PH3S CNTMD45 CNTMD23 Rev. 1.00 Apr. 28, 2008 Page 885 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 Bit 7 IOB3 TTGE TCFD bit 15 bit 7 TGRA_1 bit 15 bit 7 TGRB_1 bit 15 bit 7 LADR1H LADR1L LADR2H LADR2L SCIFADRH SCIFADRL LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 SIRQCR3 P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE bit 15 bit 7 bit 15 bit 7 bit 15 bit 7 bit 15 bit 7 bit 7 bit 7 DBU47 IEDIR3 Bit 6 CCLR1 IOB2 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 6 bit 6 DBU46 LPC4E IEDIR4 Bit 5 CCLR0 IOB1 TCIEU TCFU bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 5 bit 5 DBU45 IBFIE4 IRQ11E4 Bit 4 CKEG1 IOB0 TCIEV TCFV bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 4 bit 4 DBU44 IRQ10E4 Bit 3 CKEG0 MD3 IOA3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 3 bit 3 C/D4 IRQ9E4 SELIRQ7 P63NCE Bit 2 TPSC2 MD2 IOA2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 2 bit 2 DBU42 IRQ6E4 SELIRQ5 P62NCE Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 1 bit 1 IBF4 SMIE4 SELIRQ4 P61NCE Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 0 bit 0 OBF4 SELIRQ3 P60NCE PORT LPC Module TPU_1 SELIRQ15 SELIRQ14 SELIRQ13 SELIRQ8 P67NCE P66NCE P65NCE P64NCE P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC PC7NCE PC6NCE PC5NCE PC4NCE PC3NCE P6NCCK2 PC2NCE P6NCCK1 PC1NCE P6NCCK0 PC0NCE PC7NCMC PC6NCMC PC5NCMC PC4NCMC PC3NCMC PC2NCMC PC1NCMC PC0NCMC PG7NCE PG6NCE PG5NCE PG4NCE PG3NCE PCNCCK2 PCNCCK1 PCNCCK0 PG2NCE PG1NCE PG0NCE Rev. 1.00 Apr. 28, 2008 Page 886 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation PGNCMC PGNCCS PHPIN PHDDR PHODR PHNOCR PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PG7NCMC PG6NCMC PG5NCMC PG4NCMC PG3NCMC PG2NCMC PG1NCMC PG0NCMC PORT IIC1BS IIC1AS TxD2RS PH5PIN PH5DDR PH5ODR PH4PIN PH4DDR PH4ODR PH3PIN PH3DDR PH3ODR PGNCCK2 PGNCCK1 PGNCCK0 PH2PIN PH2DDR PH2ODR PH1PIN PH1DDR PH1ODR PH0PIN PH0DDR PH0ODR PH5NOCR PH4NOCR PH3NOCR PH2NOCR PH1NOCR PH0NOCR RxD2RS P95PCR TxD1RS P94PCR IIC0BS RxD1RS P93PCR IIC0AS P92PCR PORTS P91PCR EXCLS P90PCR PG7NOCR PG6NOCR PG5NOCR PG4NOCR PG3NOCR PG2NOCR PG1NOCR PG0NOCR PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR PC7NOCR PC6NOCR PC5NOCR PC4NOCR PC3NOCR PC2NOCR PC1NOCR PC0NOCR PD7NOCR PD6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 LPC Rev. 1.00 Apr. 28, 2008 Page 887 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation ODR3 STR3*2 STR3*3 HICR5 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR4 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMR PGODR PGPIN PGDDR PFODR PEPIN PFPIN PFDDR PCODR PDODR PCPIN PCDDR Bit 7 bit 7 IBF3B DBU37 OBEIE bit 15 bit 7 Q/C IRQ11E3 bit 7 bit 7 DBU17 bit 7 bit 7 DBU27 SELSTR3 LPC3E LPCBSY GA20 LFRAME Bit 6 bit 6 OBF3B DBU36 OBEI bit 14 bit 6 UPSEL IRQ10E3 bit 6 bit 6 DBU16 bit 6 bit 6 DBU26 Bit 5 bit 5 MWMF DBU35 bit 13 bit 5 IEDIR IRQ9E3 bit 5 bit 5 DBU15 bit 5 bit 5 DBU25 Bit 4 bit 4 SWMF DBU34 bit 12 bit 4 SMIE3B IRQ6E3 bit 4 bit 4 DBU14 bit 4 bit 4 DBU24 Bit 3 bit 3 C/D3 C/D3 SCIFE bit 11 bit 3 SMIE3A IRQ11E2 bit 3 bit 3 C/D1 SCSIRQ3 bit 3 bit 3 C/D2 SELIRQ6 SDWNE SDWNB IBFIE3 LPCPD Bit 2 bit 2 DBU32 DBU32 bit 10 SMIE2 IRQ10E2 bit 2 bit 2 DBU12 SCSIRQ2 bit 2 bit 2 DBU22 SELSMI PMEE PMEB IBFIE2 PME Bit 1 bit 1 IBF3A IBF3 bit 9 bit 1 IRQ12E1 IRQ9E2 bit 1 bit 1 IBF1 SCSIRQ1 bit 1 bit 1 IBF2 Bit 0 bit 0 OBF3A OBF3 bit 8 TWRE IRQ1E1 IRQ6E2 bit 0 bit 0 OBF1 SCSIRQ0 bit 0 bit 0 OBF2 Module LPC SELIRQ11 SELIRQ10 SELIRQ9 LPC2E CLKREQ LRST CLKRUN LPC1E IRQBSY SDWN SERIRQ FGA20E LRSTB ABRT LRESET SELIRQ12 SELIRQ1 LSMIE LSMIB IBFIE1 LSMI LSCIE LSCIB ERRIE LSCI WUEMR8 PG0ODR PG0PIN PG0DDR PF0ODR PE0PIN PF0PIN PF0DDR PC0ODR PD0ODR PC0PIN PC0DDR INT PORT WUEMR15 WUEMR14 WUEMR13 WUEMR12 WUEMR11 WUEMR10 WUEMR9 PG7ODR PG7PIN PG7DDR PF7ODR PF7PIN PF7DDR PC7ODR PD7ODR PC7PIN PC7DDR PG6ODR PG6PIN PG6DDR PF6ODR PF6PIN PF6DDR PC6ODR PD6ODR PC6PIN PC6DDR PG5ODR PG5PIN PG5DDR PF5ODR PF5PIN PF5DDR PC5ODR PD5ODR PC5PIN PC5DDR PG4ODR PG4PIN PG4DDR PF4ODR PE4PIN PF4PIN PF4DDR PC4ODR PD4ODR PC4PIN PC4DDR PG3ODR PG3PIN PG3DDR PF3ODR PE3PIN PF3PIN PF3DDR PC3ODR PD3ODR PC3PIN PC3DDR PG2ODR PG2PIN PG2DDR PF2ODR PE2PIN PF2PIN PF2DDR PC2ODR PD2ODR PC2PIN PC2DDR PG1ODR PG1PIN PG1DDR PF1ODR PE1PIN PF1PIN PF1DDR PC1ODR PD1ODR PC1PIN PC1DDR Rev. 1.00 Apr. 28, 2008 Page 888 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 Bit 7 PD7PIN PD7DDR CCLR2 IOB3 IOD3 TTGE bit 15 bit 7 TGRA_0 bit 15 bit 7 TGRB_0 bit 15 bit 7 TGRC_0 bit 15 bit 7 TGRD_0 bit 15 bit 7 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 TTGE TCFD bit 15 bit 7 TGRA_2 bit 15 bit 7 TGRB_2 bit 15 bit 7 SYSCR3 MSTPCRA MSTPCRB MSTPA7 MSTPB7 Bit 6 PD6PIN PD6DDR CCLR1 IOB2 IOD2 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 CCLR1 IOB2 bit 14 bit 6 bit 14 bit 6 bit 14 bit 6 EIVS MSTPA6 MSTPB6 Bit 5 PD5PIN PD5DDR CCLR0 BFB IOB1 IOD1 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 CCLR0 IOB1 TCIEU TCFU bit 13 bit 5 bit 13 bit 5 bit 13 bit 5 RELOCATE Bit 4 PD4PIN PD4DDR CKEG1 BFA IOB0 IOD0 TCIEV TCFV bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 CKEG1 IOB0 TCIEV TCFV bit 12 bit 4 bit 12 bit 4 bit 12 bit 4 MSTPA4 MSTPB4 Bit 3 PD3PIN PD3DDR CKEG0 MD3 IOA3 IOC3 TGIED TGFD bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 CKEG0 MD3 IOA3 bit 11 bit 3 bit 11 bit 3 bit 11 bit 3 MSTPA3 MSTPB3 Bit 2 PD2PIN PD2DDR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 TPSC2 MD2 IOA2 bit 10 bit 2 bit 10 bit 2 bit 10 bit 2 MSTPA2 MSTPB2 Bit 1 PD1PIN PD1DDR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 TPSC1 MD1 IOA1 TGIEB TGFB bit 9 bit 1 bit 9 bit 1 bit 9 bit 1 MSTPA1 MSTPB1 Bit 0 PD0PIN PD0DDR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 TPSC0 MD0 IOA0 TGIEA TGFA bit 8 bit 0 bit 8 bit 0 bit 8 bit 0 MSTPA0 MSTPB0 Module PORT TPU_0 TPU_2 SYSTEM MSTPA5 MSTPB5 Rev. 1.00 Apr. 28, 2008 Page 889 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation KMIMR KMPCR KMIMRA WUESCR WUESR WER ICRD ICCR_2 ICSR_2 ICRES_2 ICXR_2 SARX_2 ICDR_2 SAR_2 ICMR_2 DACR DADRA Bit 7 KMIMR7 KM7PCR KMIMR15 Bit 6 KMIMR6 KM6PCR KMIMR14 Bit 5 KMIMR5 KM5PCR KMIMR13 Bit 4 KMIMR4 KM4PCR KMIMR12 Bit 3 KMIMR3 KM3PCR KMIMR11 Bit 2 KMIMR2 KM2PCR KMIMR10 Bit 1 KMIMR1 KM1PCR KMIMR9 Bit 0 KMIMR0 KM0PCR KMIMR8 WUE8SC WUE8F ICRD0 SCP ACKB CLR0 FNC0 FSX ICDR0 FS BC0 CKS DA6 DA6 REGS DACNT0 REGS SCO PPVS EPVB K0 MS0 TDA0 ROM PWMX IIC_2 Module INT PORT INT WUE15SC WUE14SC WUE13SC WUE12SC WUE11SC WUE10SC WUE9SC WUE15F WUEE ICRD7 ICE ESTP STOPIM SVAX6 ICDR7 SVA6 MLS DA13 DA5 WUE14F ICRD6 IEIC STOP HNDS SVAX5 ICDR6 SVA5 WAIT PWME DA12 DA4 DA12 DA4 DACNT6 DACNT9 K6 MS6 TDA6 WUE13F ICRD5 MST IRTR ICDRF SVAX4 ICDR5 SVA4 CKS2 DA11 DA3 DA11 DA3 DACNT5 DACNT10 K5 MS5 TDA5 WUE12F ICRD4 TRS AASX ICDRE SVAX3 ICDR4 SVA3 CKS1 DA10 DA2 DA10 DA2 DACNT4 DACNT11 FLER K4 MS4 TDA4 WUE11F ICRD3 ACKE AL CLR3 ALIE SVAX2 ICDR3 SVA2 CKS0 OEB DA9 DA1 DA9 DA1 DACNT3 DACNT12 K3 MS3 TDA3 WUE10F ICRD2 BBSY AAS CLR2 ALSL SVAX1 ICDR2 SVA1 BC2 OEA DA8 DA0 DA8 DA0 DACNT2 DACNT13 K2 MS2 TDA2 WUE9F ICRD1 IRIC ADZ CLR1 FNC1 SVAX0 ICDR1 SVA0 BC1 OS DA7 CFS DA7 CFS DACNT1 K1 MS1 TDA1 DADRB DA13 DA5 DACNTH DACNTL FCCS FPCS FECS FKEY FMATS FTDAR DACNT7 DACNT8 K7 MS7 TDER Rev. 1.00 Apr. 28, 2008 Page 890 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 KBCR1_3 KBTR_3 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 Bit 7 KBTS KBT7 KBTS KBT7 KBTS KBT7 CMIEB CMFB bit 7 bit 7 bit 7 ICDR7 SVAX6 MLS SVA6 ICE ESTP KBTS KBT7 STOPIM STOPIM KBIOE KBE KB7 KBIOE KBE KB7 Bit 6 PS KBT6 PS KBT6 PS KBT6 CMIEA CMFA bit 6 bit 6 bit 6 ICDR6 SVAX5 WAIT SVA5 IEIC STOP PS KBT6 HNDS HNDS KCLKI KCLKO KB6 KCLKI KCLKO KB6 Bit 5 KCIE KBT5 KCIE KBT5 KCIE KBT5 CKSX OVIE OVF bit 5 bit 5 bit 5 ICDR5 SVAX4 CKS2 SVA4 MST IRTR KCIE KBT5 ICDRF ICDRF KDI KDO KB5 KDI KDO KB5 Bit 4 KTIE KBT4 KTIE KBT4 KTIE KBT4 CKSY CCLR1 ICIE bit 4 bit 4 bit 4 ICDR4 SVAX3 CKS1 SVA3 TRS AASX KTIE KBT4 ICDRE ICDRE KBFSEL KB4 KBFSEL KB4 Bit 3 KBT3 KBT3 KBT3 CCLR0 OS3 bit 3 bit 3 bit 3 ICDR3 SVAX2 CKS0 SVA2 ACKE AL KBT3 ALIE ALIE KBIE RXCR3 KB3 TXCR3 KBIE RXCR3 KB3 TXCR3 Bit 2 CST2 SYNC2 KCIF KBT2 KCIF KBT2 KCIF KBT2 CKS2 OS2 bit 2 bit 2 bit 2 ICDR2 SVAX1 BC2 SVA1 BBSY AAS KCIF KBT2 ALSL ALSL KBF RXCR2 KB2 TXCR2 KBF RXCR2 KB2 TXCR2 Bit 1 CST1 SYNC1 KBTE KBT1 KBTE KBT1 KBTE KBT1 CKS1 OS1 bit 1 bit 1 bit 1 ICDR1 SVAX0 BC1 SVA0 IRIC ADZ KBTE KBT1 FNC1 FNC1 PER RXCR1 KB1 TXCR1 PER RXCR1 KB1 TXCR1 Bit 0 CST0 SYNC0 KTER KBT0 KTER KBT0 KTER KBT0 CKS0 OS0 bit 0 bit 0 bit 0 ICDR0 FSX BC0 FS SCP ACKB KTER KBT0 FNC0 FNC0 KBS RXCR0 KB0 TXCR0 KBS RXCR0 KB0 TXCR0 PS2_1 IIC_0 IIC_1 PS2_0 PS2_3 IIC_1 TMR_XY TMR_Y Module TPU common PS2 Rev. 1.00 Apr. 28, 2008 Page 891 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 ICRES_0 ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR PCSR SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1* 1 Bit 7 KBIOE KBE KB7 ICRA7 ICRB7 ICRC7 IRQ7F IRQ7SCB IRQ3SCB CMF A23 A15 A7 IRQ15E IRQ15F Bit 6 KCLKI KCLKO KB6 ICRA6 ICRB6 ICRC6 IRQ6F IRQ7SCA IRQ3SCA A22 A14 A6 IRQ14E IRQ14F Bit 5 KDI KDO KB5 ICRA5 ICRB5 ICRC5 IRQ5F IRQ6SCB IRQ2SCB A21 A13 A5 IRQ13E IRQ13F Bit 4 KBFSEL KB4 ICRA4 ICRB4 ICRC4 IRQ4F IRQ6SCA IRQ2SCA A20 A12 A4 IRQ12E IRQ12F Bit 3 KBIE RXCR3 KB3 TXCR3 CLR3 ICRA3 ICRB3 ICRC3 IRQ3F IRQ5SCB IRQ1SCB A19 A11 A3 IRQ11E IRQ11F Bit 2 KBF RXCR2 KB2 TXCR2 CLR2 ICRA2 ICRB2 ICRC2 IRQ2F IRQ5SCA IRQ1SCA A18 A10 A2 IRQ10E IRQ10F Bit 1 PER RXCR1 KB1 TXCR1 CLR1 ICRA1 ICRB1 ICRC1 IRQ1F IRQ4SCB IRQ0SCB A17 A9 A1 IRQ9E IRQ9F Bit 0 KBS RXCR0 KB0 TXCR0 CLR0 ICRA0 ICRB0 ICRC0 IRQ0F IRQ4SCA IRQ0SCA BIE A16 A8 IRQ8E IRQ8F Module PS2_2 IIC_0 INT IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB ISS15 ISS7 SSBY DTON MSTP15 MSTP7 C/A (GM) ISS14 STS2 LSON MSTP14 MSTP6 CHR (BLK) bit 6 RIE bit 6 ISS13 PWCKXB STS1 NESEL MSTP13 MSTP5 PE (PE) bit 5 TE bit 5 ISS12 PWCKXA STS0 EXCLE MSTP12 MSTP4 O/E (O/E) bit 4 RE bit 4 ISS11 MSTP11 MSTP3 STOP (BCP1) bit 3 MPIE bit 3 IRQ9SCA ISS10 SCK2 MSTP10 MSTP2 MP (BCP0) bit 2 TEIE bit 2 IRQ8SCB ISS9 SCK1 MSTP9 MSTP1 CKS1 (CKS1) bit 1 CKE1 bit 1 IRQ8SCA ISS8 PWCKXC SCK0 MSTP8 MSTP0 CKS0 (CKS0) bit 0 CKE0 bit 0 SCI_1 PWMX SYSTEM BRR_1 SCR_1 TDR_1 bit 7 TIE bit 7 Rev. 1.00 Apr. 28, 2008 Page 892 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation SSR_1* 1 Bit 7 TDRE (TDRE) Bit 6 RDRF (RDRF) bit 6 CHR (BLK) bit 6 RIE bit 6 RDRF (RDRF) bit 6 WT/IT bit 6 PA6ODR PA6PIN PA6DDR P16PCR P26PCR P36PCR P16DDR P26DDR P16DR P26DR P36DDR P46DDR P36DR P46DR P66DDR P66DR Bit 5 ORER (ORER) bit 5 PE (PE) bit 5 TE bit 5 ORER (ORER) bit 5 TME bit 5 PA5ODR PA5PIN PA5DDR P15PCR P25PCR P35PCR P15DDR P25DDR P15DR P25DR P35DDR P45DDR P35DR P45DR P65DDR P65DR Bit 4 FER (ERS) bit 4 O/E (O/E) bit 4 RE bit 4 FER (ERS) bit 4 bit 4 PA4ODR PA4PIN PA4DDR P14PCR P24PCR P34PCR P14DDR P24DDR P14DR P24DR P34DDR P44DDR P34DR P44DR P64DDR P64DR Bit 3 PER (PER) bit 3 SDIR STOP (BCP1) bit 3 MPIE bit 3 PER (PER) bit 3 SDIR RST/NMI bit 3 PA3ODR PA3PIN PA3DDR P13PCR P23PCR P33PCR P13DDR P23DDR P13DR P23DR P33DDR P43DDR P33DR P43DR P63DDR P63DR Bit 2 TEND (TEND) bit 2 SINV MP (BCP0) bit 2 TEIE bit 2 TEND (TEND) bit 2 SINV CKS2 bit 2 PA2ODR PA2PIN PA2DDR P12PCR P22PCR P32PCR P12DDR P22DDR P12DR P22DR P32DDR P42DDR P32DR P42DR P52DDR P62DDR P52DR P62DR Bit 1 MPB (MPB) bit 1 CKS1 (CKS1) bit 1 CKE1 bit 1 MPB (MPB) bit 1 CKS1 bit 1 PA1ODR PA1PIN PA1DDR P11PCR P21PCR P31PCR P11DDR P21DDR P11DR P21DR P31DDR P41DDR P31DR P41DR P51DDR P61DDR P51DR P61DR Bit 0 MPBT (MPBT) bit 0 SMIF CKS0 (CKS0) bit 0 CKE0 bit 0 MPBT (MPBT) bit 0 SMIF CKS0 bit 0 PA0ODR PA0PIN PA0DDR P10PCR P20PCR P30PCR P10DDR P20DDR P10DR P20DR P30DDR P40DDR P30DR P40DR P50DDR P60DDR P50DR P60DR Module SCI_1 RDR_1 SCMR_1 SMR_2* 1 bit 7 C/A (GM) SCI_2 BRR_2 SCR_2 TDR_2 SSR_2* 1 bit 7 TIE bit 7 TDRE (TDRE) RDR_2 SCMR_2 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR bit 7 OVF bit 7 PA7ODR PA7PIN PA7DDR P17PCR P27PCR P37PCR P17DDR P27DDR P17DR P27DR P37DDR P47DDR P37DR P47DR P67DDR P67DR WDT_0 PORT Rev. 1.00 Apr. 28, 2008 Page 893 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 Bit 7 PB7ODR PB7PIN P77PIN PB7DDR P97DDR P97DR IRQ7E IICX2 EXPE CMIEB CMIEB CMFB CMFB bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 ICE ESTP ICDR7 SVAX6 MLS SVA6 Bit 6 PB6ODR PB6PIN P86DDR P76PIN PB6DDR P86DR P96DDR P96DR IRQ6E IICX1 ICIS0 CMIEA CMIEA CMFA CMFA bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 IEIC STOP ICDR6 SVAX5 WAIT SVA5 Bit 5 PB5ODR PB5PIN P85DDR P75PIN PB5DDR P85DR P95DDR P95DR IRQ5E IICX0 INTM1 BRSTRM ABW OVIE OVIE OVF OVF bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 MST IRTR ICDR5 SVAX4 CKS2 SVA4 Bit 4 PB4ODR PB4PIN P84DDR P74PIN PB4DDR P84DR P94DDR P94DR IRQ4E IICE INTM0 BRSTS1 AST CCLR1 CCLR1 ADTE bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 TRS AASX ICDR4 SVAX3 CKS1 SVA3 Bit 3 PB3ODR PB3PIN P83DDR P73PIN PB3DDR P83DR P93DDR P93DR IRQ3E FLSHE XRST BRSTS0 WMS1 CCLR0 CCLR0 OS3 OS3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 ACKE AL ICDR3 SVAX2 CKS0 SVA2 Bit 2 PB2ODR PB2PIN P82DDR P72PIN PB2DDR P82DR P92DDR P92DR IRQ2E IICS NMIEG MDS2 WMS0 CKS2 CKS2 OS2 OS2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 BBSY AAS ICDR2 SVAX1 BC2 SVA1 Bit 1 PB1ODR PB1PIN P81DDR P71PIN PB1DDR P81DR P91DDR P91DR IRQ1E ICKS1 KINWUE MDS1 IOS1 WC1 CKS1 CKS1 OS1 OS1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 IRIC ADZ ICDR1 SVAX0 BC1 SVA0 Bit 0 PB0ODR PB0PIN P80DDR P70PIN PB0DDR P80DR P90DDR P90DR IRQ0E ICKS0 RAME MDS0 IOS0 WC0 CKS0 CKS0 OS0 OS0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 SCP ACKB ICDR0 FSX BC0 FS IIC_0 TMR_0, TMR_1 BSC INT SYSTEM Module PORT Rev. 1.00 Apr. 28, 2008 Page 894 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation KBCRH_3 KBCRL_3 KBBR_3 KBCR2_3 TCSR_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI TCONRS Bit 7 KBIOE KBE KB7 OVF bit 7 CMIEB CMFB bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 TMRX/Y Bit 6 KCLKI KCLKO KB6 WT/IT bit 6 CMIEA CMFA bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 Bit 5 KDI KDO KB5 TME bit 5 OVIE OVF bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 Bit 4 KBFSEL KB4 PSS bit 4 CCLR1 ICF bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 ICST Bit 3 KBIE RXCR3 KB3 TXCR3 RST/NMI bit 3 CCLR0 OS3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 Bit 2 KBF RXCR2 KB2 TXCR2 CKS2 bit 2 CKS2 OS2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 Bit 1 PER RXCR1 KB1 TXCR1 CKS1 bit 1 CKS1 OS1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 Bit 0 KBS RXCR0 KB0 TXCR0 CKS0 bit 0 CKS0 OS0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 TMR_X, TMR_Y TMR_X WDT_1 Module PS2_3 Notes: 1. In normal mode and smart card interface mode, bit names differ in part. ( ) : Bit name in smart card interface mode. 2. When TWRE = 1 or SELSTR3 = 0. 3. When TWRE = 0 and SELSTR3 = 1. Rev. 1.00 Apr. 28, 2008 Page 895 of 994 REJ09B0452-0100 Section 27 List of Registers 27.3 Register States in Each Operating Mode HighSpeed/Medium speed Watch Module Stop Software Standby CIR Register Abbreviation PIDDR PJDDR PIODR PJODR PIPIN PJPIN PJPCR PINOCR PJNOCR CCR1 CCR2 CSTR CEIR BRR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module PORT CIRRDR0 to 7 Initialized HHMIN HHMAX HLMIN HLMAX DT1MIN DT1MAX DT0MIN DT0MAX RMIN RMAX Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 1.00 Apr. 28, 2008 Page 896 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TDPCNT_0 TDPPDMX_0 TDPPDMN_0 Reset Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TDP_0 TDPWDMX_0 Initialized TDPICR_0 TDPICRF_0 TDPCSR_0 TDPCR1_0 TDPIER_0 TDPCR2_0 Initialized Initialized Initialized Initialized Initialized Initialized TDPWDMN_0 Initialized TDPCNT_1 TDPPDMX_1 TDPPDMN_1 Initialized Initialized Initialized TDP_1 TDPWDMX_1 Initialized TDPICR_1 TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 Initialized Initialized Initialized Initialized Initialized Initialized TDPWDMN_1 Initialized TDPCNT_2 TDPPDMX_2 TDPPDMN_1 Initialized Initialized Initialized TDP_2 TDPWDMX_2 Initialized TDPICR_2 TDPICRF_2 TDPCSR_2 Initialized Initialized Initialized Rev. 1.00 Apr. 28, 2008 Page 897 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TDPCR1_2 TDPIER_2 TDPCR2_2 Reset Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TDP_2 TDPWDMN_2 Initialized TCMCNT_0 Initialized TCM_0 TCMMLCM_0 Initialized TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 Initialized Initialized Initialized Initialized Initialized TCMMINCM_0 Initialized TCMCNT_1 Initialized TCM_1 TCMMLCM_1 Initialized TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 Initialized Initialized Initialized Initialized Initialized TCMMINCM_1 Initialized TCMCNT_2 Initialized TCM_2 TCMMLCM_2 Initialized TCMICR_2 TCMICRF_2 TCMCSR_2 TCMCR_2 TCMIER_2 Initialized Initialized Initialized Initialized Initialized TCMMINCM_2 Initialized Rev. 1.00 Apr. 28, 2008 Page 898 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TCMCNT_3 Reset Initialized HighSpeed/Medium speed Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TCM_3 TCMMLCM_3 Initialized TCMICR_3 TCMICRF_3 TCMCSR_3 TCMCR_3 TCMIER_3 Initialized Initialized Initialized Initialized Initialized TCMMINCM_3 Initialized ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D converter SCIF Rev. 1.00 Apr. 28, 2008 Page 899 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation FSIHBARH FSIHBARL FSISR CMDHRARH CMDHRARL FSICMDR FSILSTR1 FSILSTR2 FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL FSIWDRHH FSIWDRHL Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module FSI Rev. 1.00 Apr. 28, 2008 Page 900 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation FSIWDRLH FSIWDRLL FSICR1 FSICR2 FSIBNR FSINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module FSI PWMREG0_A Initialized PWMPRE0_A Initialized PWMREG1_A Initialized PWMPRE1_A Initialized PWMREG2_A Initialized PWMPRE2_A Initialized PWMREG3_A Initialized PWMPRE3_A Initialized PWMREG4_A Initialized PWMPRE4_A Initialized PWMREG5_A Initialized PWMPRE5_A Initialized PWMU_A Rev. 1.00 Apr. 28, 2008 Page 901 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation Reset HighSpeed/Medium speed Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module PWMU_A PWMCONA_A Initialized PWMCONB_A Initialized PWMCONC_A Initialized PWMCOND_A Initialized PWMREG0_B Initialized PWMPRE0_B Initialized PWMREG1_B Initialized PWMPRE1_B Initialized PWMREG2_B Initialized PWMPRE2_B Initialized PWMREG3_B Initialized PWMPRE3_B Initialized PWMREG4_B Initialized PWMPRE4_B Initialized PWMREG5_B Initialized PWMPRE5_B Initialized PWMCONA_B Initialized PWMCONB_B Initialized PWMCONC_B Initialized PWMCOND_B Initialized TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWMU_B TPU_1 Rev. 1.00 Apr. 28, 2008 Page 902 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation LADR1H LADR1L LADR2H LADR2L SCIFADRH SCIFADRL LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 SIRQCR3 P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PHPIN PHDDR PHODR PHNOCR PTCNT0 PTCNT1 PTCNT2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module LPC PORT Rev. 1.00 Apr. 28, 2008 Page 903 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 HICR5 LADR3H LADR3L SIRQCR0 SIRQCR1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module PORT LPC Rev. 1.00 Apr. 28, 2008 Page 904 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation IDR1 ODR1 STR1 SIRQCR4 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMR PGODR PGPIN PGDDR PFODR PEPIN PFPIN PFDDR PCODR PDODR PCPIN PCDDR PDPIN PDDDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module LPC INT PORT TPU_0 Rev. 1.00 Apr. 28, 2008 Page 905 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA MSTPCRB KMIMR KMPCR KMIMRA WUESCR WUESR WER ICRD ICCR_2 ICSR_2 ICRES_2 ICXR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TPU_0 TPU_2 SYSTEM INT PORT INT IIC_2 Rev. 1.00 Apr. 28, 2008 Page 906 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation DACR DADRA DADRB DACNT FCCS FPCS FECS FKEY FMATS FTDAR TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Module PWMX ROM TPU common PS2 TMR_XY TMR_Y IIC_1 Rev. 1.00 Apr. 28, 2008 Page 907 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation KBCR1_3 KBTR_3 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 ICRES_0 ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module PS2_3 IIC_0 IIC_1 PS2_0 PS2_1 PS2_2 IIC_0 INT Rev. 1.00 Apr. 28, 2008 Page 908 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation ISCR16L ISSR16 ISSR PCSR SBYCR LPWRCR MSTPCRH MSTPCRL SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 TCSR_0 TCNT_0 PAODR PAPIN PADDR P1PCR P2PCR P3PCR Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Initialized Initialized Initialized Initialized Initialized Initialized Sleep Module Stop Initialized Initialized Initialized Initialized Initialized Initialized Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Module INT PWMX SYSTEM SCI_1 SCI_2 WDT_0 PORT Rev. 1.00 Apr. 28, 2008 Page 909 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR PBPIN P8DDR P7PIN PBDDR P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module PORT INT SYSTEM BSC TMR_0, TMR_1 Rev. 1.00 Apr. 28, 2008 Page 910 of 994 REJ09B0452-0100 Section 27 List of Registers Register Abbreviation TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 KBCRH_3 KBCRL_3 KBBR_3 KBCR2_3 TCSR_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI TCONRS Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized HighSpeed/Medium speed Watch Sleep Module Stop Software Standby Module TMR_0, TMR_1 IIC_0 PS2_3 WDT_1 TMR_X TMR_X, TMR_Y Rev. 1.00 Apr. 28, 2008 Page 911 of 994 REJ09B0452-0100 Section 27 List of Registers 27.4 Register Selection Condition Register Abbreviation P1DDR P2DDR P1DR P2DR P1PIN (Read) P2PIN (Read) P2PCR P3DDR P4DDR P3DR P4DR P3PIN (Read) P4PIN (Read) P3PCR P5DDR P6DDR P5DR P6DR P5PIN (Read) P6PIN (Read) P6NCE P6NCMC P6NCCS P8DDR P8DR P7PIN (Read) P8PIN (Read) P9DDR P9DR Lower Address H'F900 H'F901 H'F902 H'F903 H'F904 H'F905 H'F907 H'F910 H'F911 H'F912 H'F913 H'F914 H'F915 H'F916 H'F920 H'F921 H'F922 H'F923 H'F924 H'F925 H'F92B H'F92D H'F92F H'F931 H'F933 H'F934 H'F935 H'F940 H'F942 Register Selection Condition PORTS = 1 Module PORT Rev. 1.00 Apr. 28, 2008 Page 912 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'F944 H'F946 H'F950 H'F951 H'F952 H'F953 H'F954 H'F955 H'F957 H'F960 H'F961 H'F962 H'F963 H'F964 H'F965 H'F966 H'F967 H'F968 H'F969 H'F96A H'F96C H'F96E H'F971 H'F973 H'F974 H'F975 H'F977 H'F979 H'F980 H'F981 H'F982 Register Abbreviation P9PIN (Read) P9PCR PADDR PBDDR PAODR PBODR PAPIN (Read) PBPIN (Read) PBPCR PCDDR PDDDR PCODR PDODR PCPIN (Read) PDPIN (Read) PCPCR PDPCR PCNOCR PDNOCR PCNCE PCNCMC PCNCCS PFDDR PFODR PEPIN (Read) PFPIN (Read) PFPCR PFNOCR PGDDR PHDDR PGODR Register Selection Condition PORTS = 1 Module PORT Rev. 1.00 Apr. 28, 2008 Page 913 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'F983 H'F984 H'F985 H'F987 H'F988 H'F989 H'F98A H'F98C H'F98E H'F990 H'F991 H'F992 H'F993 H'F994 H'F995 H'F996 H'F997 H'F998 H'F999 H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA48 H'FA4A H'FA4B H'FA4C H'FA4D H'FA4E Register Abbreviation PHODR PGPIN (Read) PHPIN (Read) PHPCR PGNOCR PHNOCR PGNCE PGNCMC PGNCCS PIDDR PJDDR PIODR PJODR PIPIN (Read) PJPIN (Read) PIPCR PJPCR PINOCR PJNOCR CCR1 CCR2 CSTR CEIR BRR CIRRDR0 to 7 HHMIN HHMAX HLMIN HLMAX DT0MIN DT0MAX DT1MIN Register Selection Condition PORTS = 1 Module PORT No condition MSTPA3 = 0 CIR Rev. 1.00 Apr. 28, 2008 Page 914 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FA4F H'FA50 H'FA51 H'FB40 H'FB42 H'FB44 H'FB46 H'FB48 H'FB4A H'FB4C H'FB4D H'FB4E H'FB4F H'FB50 H'FB60 H'FB62 H'FB64 H'FB66 H'FB68 H'FB6A H'FB6C H'FB6D H'FB6E H'FB6F H'FB70 H'FB80 H'FB82 H'FB84 H'FB86 H'FB88 Register Abbreviation DT1MAX RMIN RMAX TDPCNT_0 TDPWDMX_0 TDPWDMN_0 TDPPDMX_0 TDPICR_0 TDPICRF_0 TDPCSR_0 TDPCR1_0 TDPIER_0 TDPCR2_0 TDPPDMN_0 TDPCNT_1 TDPWDMX_1 TDPWDMN_1 TDPPDMX_1 TDPICR_1 TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 TDPPDMN_1 TDPCNT_1 TDPWDMX_1 TDPWDMN_1 TDPPDMX_1 TDPICR_1 Register Selection Condition MSTPA3 = 0 Module CIR MSTPA6 = 0 TDP_0 MSTPA5 = 0 TDP_1 MSTPA4 = 0 TDP_2 Rev. 1.00 Apr. 28, 2008 Page 915 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FB8A H'FB8C H'FB8D H'FB8E H'FB8F H'FB90 H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBCC H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FBDC H'FBE0 H'FBE2 H'FBE4 H'FBE6 H'FBE8 H'FBE9 H'FBEA H'FBEC Register Abbreviation TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 TDPPDMN_1 TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 TCMMINCM_0 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 TCMMINCM_1 TCMCNT_2 TCMMLCM_2 TCMICR_2 TCMICRF_2 TCMCSR_2 TCMCR_2 TCMIER_2 TCMMINCM_2 Register Selection Condition Module MSTPB1 = 0 TCM_0 MSTPB1 = 0 TCM_1 MSTPB2 = 0 TCM_2 Rev. 1.00 Apr. 28, 2008 Page 916 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FBF0 H'FBF2 H'FBF4 H'FBF6 H'FBF8 H'FBF9 H'FBFA H'FBFC H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC11 H'FC20 H'FC20 H'FC20 H'FC21 H'FC21 H'FC22 H'FC22 H'FC23 H'FC24 H'FC25 H'FC26 H'FC27 H'FC28 Register Abbreviation TCMCNT_3 TCMMLCM_3 TCMICR_3 TCMICRF_3 TCMCSR_3 TCMCR_3 TCMIER_3 TCMMINCM_3 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADCR FRBR FTHR FDLL FIER FDLH FIIR FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR Register Selection Condition MSTPB2 = 0 Module TCM_3 MSTP9 = 0 A/D converter MSTPB3 = 0 SCIF Rev. 1.00 Apr. 28, 2008 Page 917 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FC50 H'FC51 H'FC52 H'FC53 H'FC54 H'FC55 H'FC56 H'FC57 H'FC58 H'FC59 H'FC5A H'FC5B H'FC5C H'FC5D H'FC5E H'FC5F H'FC60 H'FC61 H'FC62 H'FC63 H'FC64 H'FC65 H'FC66 H'FC67 H'FC68 H'FC69 H'FC6A H'FC6B H'FC6C H'FC6D H'FC6E Register Abbreviation FSIHBARH FSIHBARL FSISR CMDHBARH CMDHBARL FSICMDR FSILSTR1 FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL FSIWDRHH FSIWDRHL FSIWDRLH FSIWDRLL FSILSTR2 Register Selection Condition MSTP0 = 0 MSTPA2 = 0 Module FSI Rev. 1.00 Apr. 28, 2008 Page 918 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FC90 H'FC91 H'FC92 H'FC93 H'FC94 H'FC95 H'FC96 H'FC98 H'FC99 H'FC9A H'FC9B H'FC9C H'FC9D H'FC9E H'FC9F H'FCA0 H'FD00 H'FD01 H'FD02 H'FD03 H'FD04 H'FD05 H'FD06 H'FD07 H'FD08 H'FD09 H'FD0A H'FD0B H'FD0C H'FD0D H'FD0E H'FD0F Register Abbreviation FSICR1 FSICR2 FSIBNR FSIINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR PWMREG0_A PWMPRE0_A PWMREG1_A PWMPRE1_A PWMREG2_A PWMPRE2_A PWMREG3_A PWMPRE3_A PWMREG4_A PWMPRE4_A PWMREG5_A PWMPRE5_A PWMCONA_A PWMCONB_A PWMCONC_A PWMCOND_A Register Selection Condition MSTP0 = 0 MSTPA2 = 0 Module FSI MSTPB0 = 0 PWMU_A Rev. 1.00 Apr. 28, 2008 Page 919 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FD10 H'FD11 H'FD12 H'FD13 H'FD14 H'FD15 H'FD16 H'FD17 H'FD18 H'FD19 H'FD1A H'FD1B H'FD1C H'FD1D H'FD1E H'FD1F H'FD3A H'FD3B H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A Register Abbreviation PWMREG0_B PWMPRE0_B PWMREG1_B PWMPRE1_B PWMREG2_B PWMPRE2_B PWMREG3_B PWMPRE3_B PWMREG4_B PWMPRE4_B PWMREG5_B PWMPRE5_B PWMCONA_B PWMCONB_B PWMCONC_B PWMCOND_B SYTSR0 SYTSR1 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 Register Selection Condition MSTPB0 = 0 Module PWMU_B No condition SYSTEM MSTP1 = 0 TPU_1 Rev. 1.00 Apr. 28, 2008 Page 920 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FDC0 H'FDC1 H'FDC2 H'FDC3 H'FDC4 H'FDC5 H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FDDB H'FE00 H'FE01 H'FE02 H'FE03 H'FE04 H'FE05 H'FE06 H'FE07 H'FE08 H'FE0C Register Abbreviation LADR1H LADR1L LADR2H LADR2L SCIFADRH SCIFADRL LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 SIRQCR3 P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PHPIN (Read) PHDDR (Write) Register Selection Condition MSTP0 = 0 Module LPC PORTS = 0 PORT H'FE0D H'FE0E PHODR PHNOCR Rev. 1.00 Apr. 28, 2008 Page 921 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FE10 H'FE11 H'FE12 H'FE14 H'FE16 H'FE19 H'FE1C H'FE1D H'FE20 Register Abbreviation PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR TWR0MW TWR0SW Register Selection Condition No condition Module PORT PORTS = 0 MSTP0 = 0 LPC H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 Rev. 1.00 Apr. 28, 2008 Page 922 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FE32 H'FE33 H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FE45 H'FE46 H'FE47 Register Abbreviation STR3 HICR5 LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR4 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 WUEMR PGODR PGPIN (Read) PGDDR (Write) Register Selection Condition MSTP0 = 0 Module LPC No condition PORTS = 0 INT PORT H'FE49 H'FE4A H'FE4B H'FE4C H'FE4D H'FE4E PFODR PEPIN (Read) (write prohibited) PFPIN (Read) PCODR PDODR PCPIN (Read) PCDDR (Write) H'FE4F PDPIN (Read) PDDDR (Write) Rev. 1.00 Apr. 28, 2008 Page 923 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FE50 H'FE51 H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FE7D H'FE7E H'FE7F H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 Register Abbreviation TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 SYSCR3 MSTPCRA MSTPCRB KMIMR (RELOCATE = 1) KMPCR (RELOCATE = 1) KMIMRA (RELOCATE = 1) WUESCR WUESR WER ICRD Register Selection Condition MSTP1 = 0 Module TPU_0 TPU_2 No condition SYSTEM INT PORT INT Rev. 1.00 Apr. 28, 2008 Page 924 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FE88 H'FE89 H'FE8A H'FE8C H'FE8E H'FE8E H'FE8F H'FE8F H'FEA0 Register Abbreviation ICCR_2 ICSR_2 ICRES_2 ICXR_2 ICDR_2 SARX_2 ICMR_2 SAR_2 DACR (RELOCATE = 1) DADRAH (RELOCATE = 1) Register Selection Condition MSTPB4 = 0 Module IIC_2 ICE in ICCR_2 = 1 ICE in ICCR_2 = 0 ICE in ICCR_2 = 1 ICE in ICCR_2 = 0 MSTP11 = 0 MSTPA1 = 0 REGS in PWMX DACNT/DADRB = 1 REGS in DACNT/DADRB = 0 H'FEA1 H'FEA6 DADRAL (RELOCATE = 1) DADRBH (RELOCATE = 1) DACNTH (RELOCATE = 1) REGS in DACNT/DADRB = 1 REGS in DACNT/DADRB = 0 REGS in DACNT/DADRB = 1 FLSHE = 1 ROM H'FEA7 DADRBL (RELOCATE = 1) DACNTL (RELOCATE = 1) H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE FCCS FPCS FECS FKEY FMATS FTDAR Rev. 1.00 Apr. 28, 2008 Page 925 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECE Register Abbreviation TSTR TSYR KBCR1_0 KBTR_0 KBCR1_1 KBTR_1 KBCR1_2 KBTR_2 TCRXY TCR_Y (RELOCATE = 1) TCSR_Y (RELOCATE = 1) TCORA_Y (RELOCATE = 1) TCORB_Y (RELOCATE = 1) TCNT_Y (RELOCATE = 1) ICDR_1 (RELOCATE = 1) SARX_1 (RELOCATE = 1) Register Selection Condition MSTP1 = 0 Module TPU common MSTP2 = 0 PS2 MSTP8 = 0 TMR_XY TMR_Y MSTP3 = 0 ICE in ICCR_1 = 1 ICE in ICCR_1 = 0 ICE in ICCR_1 = 1 ICE in ICCR_1 = 0 IIC_1 H'FECF ICMR_1 (RELOCATE = 1) SAR_1 (RELOCATE = 1) H'FED0 H'FED1 ICCR_1 (RELOCATE = 1) ICSR_1 (RELOCATE = 1) Rev. 1.00 Apr. 28, 2008 Page 926 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FED2 H'FED3 H'FED4 H'FED5 H'FED8 H'FED9 H'FEDA H'FEDB H'FEDC H'FEDD H'FEDE H'FEDF H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FEE6 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB Register Abbreviation KBCR1_3 KBTR_3 ICXR_0 ICXR_1 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 ICRES_0 ICRA ICRB ICRC ISR ISCRH ISCRL ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L Register Selection Condition MSTPB5 Module PS2_3 MSTP4 = 0 MSTP3 = 0 MSTP2 = 0 IIC_0 IIC_1 PS2 MSTP4 = 0, IICE in STCR = 1 No condition IIC_0 INT Rev. 1.00 Apr. 28, 2008 Page 927 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FEFC H'FEFD H'FF82 Register Abbreviation ISSR16 ISSR PCSR (RELOCATE = 0) PCSR (RELOCATE = 1) Register Selection Condition No condition Module INT FLSHE in STCR = 0 No condition FLSHE in STCR = 0 No condition FLSHE in STCR = 0 No condition FLSHE in STCR = 0 No condition FLSHE in STCR = 0 No condition MSTP6 = 0 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 MSTP6 = 0 MSTP6 = 0, IICE in STCR = 0 MSTP3 = 0, IICE in STCR = 1 PWMX H'FF84 SBYCR (RELOCATE = 0) SBYCR (RELOCATE = 1) SYSTEM H'FF85 LPWRCR (RELOCATE = 0) LPWRCR (RELOCATE = 1) H'FF86 MSTPCRH (RELOCATE = 0) MSTPCRH (RELOCATE = 1) H'FF87 MSTPCRL (RELOCATE = 0) MSTPCRL (RELOCATE = 1) SYSTEM H'FF88 SMR_1 (RELOCATE = 1) SMR_1 (RELOCATE = 0) ICCR_1 (RELOCATE = 0) SCI_1 IIC_1 SCI_1 H'FF89 BRR_1 (RELOCATE = 1) BRR_1 (RELOCATE = 0) ICSR_1 (RELOCATE = 0) IIC_1 Rev. 1.00 Apr. 28, 2008 Page 928 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E Register Abbreviation SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 (RELOCATE = 1) SCMR_1 (RELOCATE = 0) ICDR_1 (RELOCATE = 0) SARX_1 (RELOCATE = 0) Register Selection Condition MSTP6 = 0 Module SCI_1 MSTP6 = 0 MSTP6 = 0, IICE in STCR = 0 ICE in ICCR_1 = 1 MSTP3 = 0 IICE in STCR = 1 ICE in ICCR_1 = 0 ICE in ICCR_1 = 1 ICE in ICCR_1 = 0 MSTP11 = 0 REGS in DACNT/ MSTPA1 = 0 DADRB = 0 IICE in STCR = REGS in DACNT/ 1 DADRB = 1 MSTP5 = 0, IICE in STCR = 0 REGS in DACNT/ MSTP11 = 0 DADRB = 0 MSTPA1 = 0 IICE in STCR = 1 REGS in DACNT/ MSTP11 = 0 DADRB = 0 MSTPA1 = 0 IICE in STCR = REGS in DACNT/ 1 DADRB = 1 MSTP5 = 0, IICE in STCR = 0 MSTP5 = 0 SCI_2 PWMX IIC_1 H'FF8F ICMR_1 (RELOCATE = 0) SAR_1 (RELOCATE = 0) H'FFA0 DADRAH (RELOCATE = 0) DACR (RELOCATE = 0) SMR_2 (RELOCATE = 0) SCI_2 PWMX H'FFA1 DADRAL (RELOCATE = 0) DADRBH (RELOCATE = 0) DACNTH (RELOCATE = 0) BRR_2 (RELOCATE = 0) H'FFA2 H'FFA3 H'FFA4 SCR_2 TDR_2 SSR_2 Rev. 1.00 Apr. 28, 2008 Page 929 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FFA5 H'FFA6 H'FFA7 Register Abbreviation RDR_2 SCMR_2 DADRBL (RELOCATE = 0) DACNTL (RELOCATE = 0) Register Selection Condition MSTP5 = 0 Module SCI_2 MSTP11 = 0 MSTPA1 = 0 IICE in STCR = 1 REGS in DACNT/ DADRB = 0 REGS in DACNT/ DADRB = 1 PWMX H'FFA8 TCSR_0 TCNT_0 (Write) No condition WDT_0 H'FFA9 H'FFAA H'FFAB TCNT_0 (Read) PAODR PAPIN (Read) PADDR (Write) PORTS = 0 PORT H'FFAC H'FFAD H'FFAE H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD P1PCR P2PCR P3PCR P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR (Write) PBPIN (Read) PORTS = 0 PORT Rev. 1.00 Apr. 28, 2008 Page 930 of 994 REJ09B0452-0100 Section 27 List of Registers Lower Address H'FFBE Register Abbreviation P7PIN (Read) PBDDR (Write) Register Selection Condition PORTS = 0 Module PORT H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFCF H'FFD8 H'FFD9 H'FFDE P8DR P9DDR P9DR IER STCR SYSCR MDCR BCR WSCR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 ICCR_0 ICSR_0 ICDR_0 SARX_0 MSTP4 = 0 IICE in STCR = 1 (RELOCATE = 0) MSTP4 = 0 ICE in IICE in STCR = 1 ICCR_0 = 1 (RELOCATE = 0) ICE in ICCR_0 = 0 MSTP4 = 0 ICE in IICE in STCR = 1 ICCR_0 = 1 (RELOCATE = 0) ICE in ICCR_0 = 0 No condition of IIC_0 IICE = 1 when RELOCATE = 1 MSTP12 = 0 TMR_0, TMR_1 MSTP12 = 0 TMR_0, TMR_1 No condition BSC No condition No condition INT SYSTEM H'FFDF ICMR_0 SAR_0 Rev. 1.00 Apr. 28, 2008 Page 931 of 994 REJ09B0452-0100 Section 27 List of Registers Register Lower Address Abbreviation H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFEA KBCRH_3 KBCRL_3 KBBR_3 KBCR2_3 TCSR_1 TCNT_1 (Write) H'FFEB H'FFF0 TCNT_1 (Read) TCR_X (RELOCATE = 1) TCR_X (RELOCATE = 0) TCR_Y (RELOCATE = 0) H'FFF1 KMIMR (RELOCATE = 0) TCSR_X (RELOCATE = 1) TCSR_X (RELOCATE = 0) TCSR_Y (RELOCATE = 0) H'FFF2 KMPCR (RELOCATE = 0) TICRR (RELOCATE = 1) TICRR (RELOCATE = 0) TCORA_Y (RELOCATE = 0) Register Selection Condition MSTPB5 = 0 Module PS2_3 No condition WDT_1 MSTP8 = 0 TMRX/Y MSTP8 = 0 KINWUE in SYSCR = 0 in TCONRS = 0 TMRX/Y in TCONRS = 1 MSTP2 = 0 KINWUE in SYSCR = 1 MSTP8 = 0 TMRX/Y MSTP8 = 0 KINWUE in SYSCR = 0 in TCONRS = 0 TMRX/Y in TCONRS = 1 MSTP2 = 0 KINWUE in SYSCR = 1 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TMRX/Y in TCONRS = 1 TMR_X TMR_Y INT TMR_X TMR_Y PORT TMR_X TMR_Y Rev. 1.00 Apr. 28, 2008 Page 932 of 994 REJ09B0452-0100 Section 27 List of Registers Register Lower Address Abbreviation H'FFF3 KMIMRA (RELOCATE = 0) TICRF (RELOCATE = 1) TICRF (RELOCATE = 0) TCORB_Y (RELOCATE = 0) H'FFF4 TCNT_X (RELOCATE = 1) TCNT_X (RELOCATE = 0) TCNT_Y (RELOCATE = 0) H'FFF5 TCORC (RELOCATE = 1) TCORC (RELOCATE = 0) H'FFF6 TCORA_X (RELOCATE = 1) TCORA_X (RELOCATE = 0) H'FFF7 TCORB_X (RELOCATE = 1) TCORB_X (RELOCATE = 0) H'FFFC TCONRI (RELOCATE = 1) TCONRI (RELOCATE = 0) H'FFFE TCONRS (RELOCATE = 1) TCONRS (RELOCATE = 0) Register Selection Condition MSTP2 = 0, KINWUE in SYSCR = 1 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TMRX/Y in TCONRS = 1 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 TMRX/Y in TCONRS = 1 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 MSTP8 = 0 MSTP8 = 0 TMRX/Y KINWUE in SYSCR = 0 in TCONRS = 0 MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0 MSTP8 = 0 MSTP8 = 0, KINWUE in SYSCR = 0 Module INT TMR_X TMR_Y TMR_X TMR_Y TMR_X TMR_X TMR_X TMR_X TMR_X, TMR_Y Rev. 1.00 Apr. 28, 2008 Page 933 of 994 REJ09B0452-0100 Section 27 List of Registers 27.5 Module INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT Register Addresses (Classification by Type of Module) Register Abbreviation WUEMR KMIMR KMIMRA WUESCR WUESR WER ICRD ICRA ICRB ICRC ISR ISCRH ISCRL KMIMR ABRKCR BARA BARB BARC IER16 ISR16 ISCR16H ISCR16L ISSR16 ISSR IER KMIMRA Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FE45 Data Bus Width 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FE81 8 (RELOCATE = 1) H'FE83 8 (RELOCATE = 1) H'FE84 H'FE85 H'FE86 H'FE87 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED 8 8 8 8 8 8 8 8 8 8 H'FFF1 8 (RELOCATE = 0) H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FFC2 8 8 8 8 8 8 8 8 8 8 8 H'FFF3 8 (RELOCATE = 0) Rev. 1.00 Apr. 28, 2008 Page 934 of 994 REJ09B0452-0100 Section 27 List of Registers Module BSC BSC PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation BCR WSCR P1DDR P2DDR P1DR P2DR P1PIN P2PIN P1PCR P2PCR P3DDR P4DDR P3DR P4DR P3PIN P4PIN P3PCR P5DDR P6DDR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFC6 H'FFC7 H'F900 (PORTS = 1) H'F901 (PORTS = 1) H'F902 (PORTS = 1) H'F903 (PORTS = 1) H'F904 (Read) (PORTS = 1) H'F905 (Read) (PORTS = 1) H'F906 (PORTS = 1) H'F907 (PORTS = 1) H'F910 (PORTS = 1) H'F911 (PORTS = 1) H'F912 (PORTS = 1) H'F913 (PORTS = 1) H'F914 (Read) (PORTS = 1) H'F915 (Read) (PORTS = 1) H'F916 (PORTS = 1) H'F920 (PORTS = 1) H'F921 (PORTS = 1) Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 935 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation P5DR P6DR P5PIN P6PIN P6NCE P6NCMC P6NCCS P8DDR P8DR P7PIN P8PIN P9DDR P9DR P9PIN P9PCR PADDR PBDDR PAODR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'F922 (PORTS = 1) H'F923 (PORTS = 1) H'F924 (Read) (PORTS = 1) H'F925 (Read) (PORTS = 1) H'F92B (PORTS = 1) H'F92D (PORTS = 1) H'F92F (PORTS = 1) H'F931 (PORTS = 1) H'F933 (PORTS = 1) H'F934 (Read) (PORTS = 1) H'F935 (Read) (PORTS = 1) H'F940 (PORTS = 1) H'F942 (PORTS = 1) H'F944 (Read) (PORTS = 1) H'F946 (PORTS = 1) H'F950 (PORTS = 1) H'F951 (PORTS = 1) H'F952 (PORTS = 1) Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 936 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation PBODR PAPIN PBPIN PBPCR PCDDR PDDDR PCODR PDODR PCPIN PDPIN PCPCR PDPCR PCNOCR PDNOCR PCNCE PCNCMC PCNCCS PFDDR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'F953 (PORTS = 1) H'F954 (Read) (PORTS = 1) H'F955 (Read) (PORTS = 1) H'F957 (PORTS = 1) H'F960 (PORTS = 1) H'F961 (PORTS = 1) H'F962 (PORTS = 1) H'F963 (PORTS = 1) H'F964 (Read) (PORTS = 1) H'F965 (Read) (PORTS = 1) H'F966 (PORTS = 1) H'F967 (PORTS = 1) H'F968 (PORTS = 1) H'F969 (PORTS = 1) H'F96A (PORTS = 1) H'F96C (PORTS = 1) H'F96E (PORTS = 1) H'F971 (PORTS = 1) Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 937 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation PFODR PEPIN PFPIN PFPCR PFNOCR PGDDR PHDDR PGODR PHODR PGPIN PHPIN PHPCR PGNOCR PHNOCR PGNCE PGNCMC PGNCCS PIDDR PJDDR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'F973 (PORTS = 1) H'F974 (Read) (PORTS = 1) H'F975 (Read) (PORTS = 1) H'F977 (PORTS = 1) H'F979 (PORTS = 1) H'F980 (PORTS = 1) H'F981 (PORTS = 1) H'F982 (PORTS = 1) H'F983 (PORTS = 1) H'F984 (Read) (PORTS = 1) H'F985 (Read) (PORTS = 1) H'F987 (PORTS = 1) H'F988 (PORTS = 1) H'F989 (PORTS = 1) H'F98A (PORTS = 1) H'F98C (PORTS = 1) H'F98E (PORTS = 1) H'F990 H'F991 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 938 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation PIODR PJODR PIPIN PJPIN PJPCR PINOCR PJNOCR P6NCE P6NCMC P6NCCS PCNCE PCNCMC PCNCCS PGNCE PGNCMC PGNCCS PHPIN Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'F992 H'F993 H'F994 (Read) H'F995 (Read) H'F997 H'F998 H'F999 H'FE00 (PORTS = 0) H'FE01 (PORTS = 0) H'FE02 (PORTS = 0) H'FE03 (PORTS = 0) H'FE04 (PORTS = 0) H'FE05 (PORTS = 0) H'FE06 (PORTS = 0) H'FE07 (PORTS = 0) H'FE08 (PORTS = 0) H'FE0C (Read) (PORTS = 0) H'FE0C (Write) (PORTS = 0) H'FE0D (PORTS = 0) H'FE0E (PORTS = 0) Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PORT PHDDR 8 8 2 PORT PORT PHODR PHNOCR 8 8 8 8 2 2 Rev. 1.00 Apr. 28, 2008 Page 939 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation PTCNT0 PTCNT1 PTCNT2 P9PCR PGNOCR PFNOCR PCNOCR PDNOCR PGODR PGPIN Number of Bits 8 8 8 8 8 8 8 8 8 8 Address H'FE10 (PORTS = 0) H'FE11 (PORTS = 0) H'FE12 (PORTS = 0) H'FE14 (PORTS = 0) H'FE16 (PORTS = 0) H'FE19 (PORTS = 0) H'FE1C (PORTS = 0) H'FE1D (PORTS = 0) H'FE46 (PORTS = 0) H'FE47 (Read) (PORTS = 0) H'FE47 (Write) (PORTS = 0) H'FE49 (PORTS = 0) H'FE4A (Read) (write prohibited) (PORTS = 0) H'FE4B (Read) (PORTS = 0) H'FE4B (Write) (PORTS = 0) Data Bus Width 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 PORT PGDDR 8 8 2 PORT PORT PFODR PEPIN 8 8 8 8 2 2 PORT PFPIN 8 8 2 PORT PFDDR 8 8 2 Rev. 1.00 Apr. 28, 2008 Page 940 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT Register Abbreviation PCODR PDODR PCPIN Number of Bits 8 8 8 Address H'FE4C (PORTS = 0) H'FE4D (PORTS = 0) H'FE4E (Read) (PORTS = 0) H'FE4E (Write) (PORTS = 0) H'FE4F (Read) (PORTS = 0) H'FE4F (Write) (PORTS = 0) Data Bus Width 8 8 8 Access States 2 2 2 PORT PCDDR 8 8 2 PORT PDPIN 8 8 2 PORT PDDDR 8 8 2 PORT KMPCR 8 H'FE82 8 (RELOCATE = 1) (PORTS = 0) H'FFAA (PORTS = 0) H'FFAB (Read) (PORTS = 0) H'FFAB (Write) (PORTS = 0) H'FFAC (PORTS = 0) H'FFAD (PORTS = 0) H'FFAE (PORTS = 0) H'FFB0 (PORTS = 0) H'FFB1 (PORTS = 0) H'FFB2 (PORTS = 0) 8 8 8 8 8 8 8 8 8 2 PORT PORT PORT PORT PORT PORT PORT PORT PORT PAODR PAPIN PADDR P1PCR P2PCR P3PCR P1DDR P2DDR P1DR 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 941 of 994 REJ09B0452-0100 Section 27 List of Registers Module PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT Register Abbreviation P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR PBODR P8DDR PBPIN P7PIN PBDDR P8DR P9DDR P9DR KMPCR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFB3 (PORTS = 0) H'FFB4 (PORTS = 0) H'FFB5 (PORTS = 0) H'FFB6 (PORTS = 0) H'FFB7 (PORTS = 0) H'FFB8 (PORTS = 0) H'FFB9 (PORTS = 0) H'FFBA (PORTS = 0) H'FFBB (PORTS = 0) H'FFBC (PORTS = 0) H'FFBD (Write) (PORTS = 0) H'FFBD (Read) (PORTS = 0) H'FFBE (Read) (PORTS = 0) H'FFBE (Write) (PORTS = 0) H'FFBF (PORTS = 0) H'FFC0 (PORTS = 0) H'FFC1 (PORTS = 0) Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FFF2 8 (RELOCATE = 0) (PORTS = 0) Rev. 1.00 Apr. 28, 2008 Page 942 of 994 REJ09B0452-0100 Section 27 List of Registers Module TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_0 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_1 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 TDP_2 Register Abbreviation TDPCNT_0 TDPWDMX_0 TDPWDMN_0 TDPPDMX_0 TDPICR_0 TDPICRF_0 TDPCSR_0 TDPCR1_0 TDPIER_0 TDPCR2_0 TDPPDMN_0 TDPCNT_1 TDPWDMX_1 TDPWDMN_1 TDPPDMX_1 TDPICR_1 TDPICRF_1 TDPCSR_1 TDPCR1_1 TDPIER_1 TDPCR2_1 TDPPDMN_1 TDPCNT_2 TDPWDMX_2 TDPWDMN_2 TDPPDMX_2 TDPICR_2 TDPICRF_2 TDPCSR_2 TDPCR1_2 TPDIER_2 Number of Bits 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 16 16 16 16 16 16 16 8 8 8 Address H'FB40 H'FB42 H'FB44 H'FB46 H'FB48 H'FB8A H'FB8C H'FB4D H'FB4E H'FB4F H'FB50 H'FB60 H'FB62 H'FB64 H'FB66 H'FB68 H'FB6A H'FB6C H'FB6D H'FB6E H'FB6F H'FB70 H'FB80 H'FB82 H'FB84 H'FB86 H'FB88 H'FB8A H'FB8C H'FB8D H'FB8E Data Bus Width 8 8 8 8 8 8 8 8 8 8 16 16 6 16 16 16 16 8 8 8 8 16 16 16 16 16 16 16 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 943 of 994 REJ09B0452-0100 Section 27 List of Registers Module TDP_2 TDP_2 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_0 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_1 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_2 TCM_3 TCM_3 TCM_3 TCM_3 TCM_3 Register Abbreviation TDPCR2_2 TDPPDMN_2 TCMCNT_0 TCMMLCM_0 TCMICR_0 TCMICRF_0 TCMCSR_0 TCMCR_0 TCMIER_0 Number of Bits 8 16 16 16 16 16 8 8 8 Address H'FB8F H'FB90 H'FBC0 H'FBC2 H'FBC4 H'FBC6 H'FBC8 H'FBC9 H'FBCA H'FBCC H'FBD0 H'FBD2 H'FBD4 H'FBD6 H'FBD8 H'FBD9 H'FBDA H'FBDC H'FBE0 H'FBE2 H'FBE4 H'FBE6 H'FBE8 H'FBE9 H'FBEA H'FBEC H'FBF0 H'FBF2 H'FBF4 H'FBF6 H'FBF8 Data Bus Width 8 16 16 16 16 16 8 8 8 16 16 16 16 16 8 8 8 16 16 16 16 16 8 8 8 16 16 16 16 16 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TCMMINCM_0 16 TCMCNT_1 TCMMLCM_1 TCMICR_1 TCMICRF_1 TCMCSR_1 TCMCR_1 TCMIER_1 16 16 16 16 8 8 8 TCMMINCM_1 16 TCMCNT_2 TCMMLCM_2 TCMICR_2 TCMICRF_2 TCMCSR_2 TCMCR_2 TCMIER_2 16 16 16 16 8 8 8 TCMMINCM_2 16 TCMCNT_3 TCMMLCM_3 TCMICR_3 TCMICRF_3 TCMCSR_3 16 16 16 16 8 Rev. 1.00 Apr. 28, 2008 Page 944 of 994 REJ09B0452-0100 Section 27 List of Registers Module TCM_3 TCM_3 TCM_3 FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI Register Abbreviation TCMCR_3 TCMIER_3 Number of Bits 8 8 Address H'FBF9 H'FBFA H'FBFC H'FC50 H'FC51 H'FC52 H'FC53 H'FC54 H'FC55 H'FC56 H'FC57 H'FC58 H'FC59 H'FC5A H'FC5B H'FC5C H'FC5D H'FC5E H'FC5F H'FC60 H'FC61 H'FC62 H'FC63 H'FC64 H'FC65 H'FC66 H'FC67 H'FC68 H'FC69 H'FC6A H'FC6B Data Bus Width 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TCMMINCM_3 16 FSIHBARH FSIHBARL FSISR CMDHBARH CMDHBARH FSICMDR FSILSTR1 FSIGPR1 FSIGPR2 FSIGPR3 FSIGPR4 FSIGPR5 FSIGPR6 FSIGPR7 FSIGPR8 FSIGPR9 FSIGPRA FSIGPRB FSIGPRC FSIGPRD FSIGPRE FSIGPRF SLCR FSIARH FSIARM FSIARL FSIWDRHH FSIWDRHL 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 945 of 994 REJ09B0452-0100 Section 27 List of Registers Module FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI FSI CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR CIR Register Abbreviation FSIWDRLH FSIWDRLL FSILSTR2 FSICR1 FSICR2 FSIBNR FSINS FSIRDINS FSIPPINS FSISTR FSITDR0 FSITDR1 FSITDR2 FSITDR3 FSITDR4 FSITDR5 FSITDR6 FSITDR7 FSIRDR CCR1 CCR2 CSTR CEIR BRR CIRRDR0 to 7 HHMIN HHMAX HLMIN HLMAX DT0MIN DT0MAX Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 Address H'FC6C H'FC6D H'FC6E H'FC90 H'FC91 H'FC92 H'FC93 H'FC94 H'FC95 H'FC96 H'FC98 H'FC99 H'FC9A H'FC9B H'FC9C H'FC9D H'FC9E H'FC9F H'FCA0 H'FA40 H'FA41 H'FA42 H'FA43 H'FA44 H'FA45 H'FA46 H'FA48 H'FA4A H'FA4B H'FA4C H'FA4D Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 946 of 994 REJ09B0452-0100 Section 27 List of Registers Module CIR CIR CIR CIR PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_A PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B PWMU_B Register Abbreviation DT1MIN DT1MAX RMIN RMAX PWMREG0 PWMPRE0 PWMREG1 PWMPRE1 PWMREG2 PWMPRE2 PWMREG3 PWMPRE3 PWMREG4 PWMPRE4 PWMREG5 PWMPRE5 PWMCONA PWMCONB PWMCONC PWMCOND PWMREG0 PWMPRE0 PWMREG1 PWMPRE1 PWMREG2 PWMPRE2 PWMREG3 PWMPRE3 PWMREG4 PWMPRE4 PWMREG5 PWMPRE5 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FA4E H'FA4F H'FA50 H'FA51 H'FD00 H'FD01 H'FD02 H'FD03 H'FD04 H'FD05 H'FD06 H'FD07 H'FD08 H'FD09 H'FD0A H'FD0B H'FD0C H'FD0D H'FD0E H'FD0F H'FD10 H'FD11 H'FD12 H'FD13 H'FD14 H'FD15 H'FD16 H'FD17 H'FD18 H'FD19 H'FD1A H'FD1B Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 947 of 994 REJ09B0452-0100 Section 27 List of Registers Module PWMU_B PWMU_B PWMU_B PWMU_B PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX PWMX TPU_0 TPU_0 Register Abbreviation PWMCONA PWMCONB PWMCONC PWMCOND DACR DADRAH DADRAL DADRBH DACNTH DADRBL DACNTL PCSR DACR DADRAH DADRAL DACNTH DADRBH DACNTL DADRBL TCR_0 TMDR_0 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FD1C H'FD1D H'FD1E H'FD1F H'FEA0 (RELOCATE = 1) Data Bus Width 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FEA0 8 (RELOCATE = 1) H'FEA1 8 (RELOCATE = 1) H'FEA6 8 (RELOCATE = 1) H'FEA6 8 (RELOCATE = 1) H'FEA7 8 (RELOCATE = 1) H'FEA7 8 (RELOCATE = 1) H'FF82 8 H'FFA0 8 (RELOCATE = 0) H'FFA0 8 (RELOCATE = 0) H'FFA1 8 (RELOCATE = 0) H'FFA6 8 (RELOCATE = 0) H'FFA6 8 (RELOCATE = 0) H'FFA7 8 (RELOCATE = 0) H'FFA7 8 (RELOCATE = 0) H'FE50 H'FE51 8 8 Rev. 1.00 Apr. 28, 2008 Page 948 of 994 REJ09B0452-0100 Section 27 List of Registers Module TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU common TPU common TMR_0 TMR_0 TMR_0 Register Abbreviation TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TSTR TSYR TCR_0 TCSR_0 TCORA_0 Number of Bits 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 Address H'FE52 H'FE53 H'FE54 H'FE55 H'FE56 H'FE58 H'FE5A H'FE5C H'FE5E H'FD40 H'FD41 H'FD42 H'FD44 H'FD45 H'FD46 H'FD48 H'FD4A H'FE70 H'FE71 H'FE72 H'FE74 H'FE75 H'FE76 H'FE78 H'FE7A H'FEB0 H'FEB1 H'FFC8 H'FFCA H'FFCC Data Bus Width 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 16 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 949 of 994 REJ09B0452-0100 Section 27 List of Registers Module TMR_0 TMR_0 TMR_1 TMR_1 TMR_1 TMR_1 TMR_1 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y Register Abbreviation TCORB_0 TCNT_0 TCR_1 TCSR_1 TCORA_1 TCORB_1 TCNT_1 TCR_X TCSR_X TICRR TICRF TCNT_X TCORC TCORA_X TCORB_X TCONRI TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TCR_Y TCSR_Y TCORA_Y TCORB_Y Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFCE H'FFD0 H'FFC9 H'FFCB H'FFCD H'FFCF H'FFD1 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFFC Data Bus Width 16 16 8 16 16 16 16 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FEC8 8 (RELOCATE = 1) H'FEC9 8 (RELOCATE = 1) H'FECA 8 (RELOCATE = 1) H'FECB 8 (RELOCATE = 1) H'FECC 8 (RELOCATE = 1) H'FFF0 8 (RELOCATE = 0) H'FFF1 8 (RELOCATE = 0) H'FFF2 8 (RELOCATE = 0) H'FFF3 8 (RELOCATE = 0) Rev. 1.00 Apr. 28, 2008 Page 950 of 994 REJ09B0452-0100 Section 27 List of Registers Module TMR_Y TMR_XY TMR_X TMR_X, TMR_Y WDT_0 WDT_0 WDT_0 WDT_0 WDT_1 WDT_1 WDT_1 WDT_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 IIC_0 IIC_0 IIC_0 IIC_0 Register Abbreviation TCNT_Y TCRXY TCONRI TCONRS TCSR_0 TCSR_0 TCNT_0 TCNT_0 TCSR_1 TCSR_1 TCNT_1 TCNT_1 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ICXR_0 ICCR_0 ICSR_0 ICDR_0 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address Data Bus Width Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FFF4 8 (RELOCATE = 0) H'FEC6 H'FFFC H'FFFE H'FFA8 (Write) H'FFA8 (Read) H'FFA8 (Write) H'FFA9 (Read) H'FFEA (Write) H'FFEA (Read) H'FFEA (Write) H'FFEB (Read) H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FED4 H'FFD8 H'FFD9 H'FFDE 8 8 8 16 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 951 of 994 REJ09B0452-0100 Section 27 List of Registers Module IIC_0 IIC_0 IIC_0 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_1 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 IIC_2 Register Abbreviation SARX_0 ICMR_0 SAR_0 ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_1 ICSR_1 ICXR_1 ICCR_1 ICSR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 ICCR_2 ICSR_2 ICRES_2 ICXR_2 ICDR_2 SARX_2 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFDE H'FFDF H'FFDF Data Bus Width 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 H'FECE 8 (RELOCATE = 1) H'FECE 8 (RELOCATE = 1) H'FECF 8 (RELOCATE = 1) H'FECF 8 (RELOCATE = 1) H'FED0 8 (RELOCATE = 1) H'FED1 8 (RELOCATE = 1) H'FED5 8 H'FF88 8 (RELOCATE = 0) H'FF89 8 (RELOCATE = 0) H'FF8E 8 (RELOCATE = 0) H'FF8E 8 (RELOCATE = 0) H'FF8F 8 (RELOCATE = 0) H'FF8F 8 (RELOCATE = 0) H'FE88 H'FE89 H'FE8A H'FE8C H'FE8E H'FE8E 8 8 8 8 8 8 Rev. 1.00 Apr. 28, 2008 Page 952 of 994 REJ09B0452-0100 Section 27 List of Registers Module IIC_2 IIC_2 IIC_0 PS2_0 PS2_0 PS2_0 PS2_0 PS2_0 PS2_0 PS2_1 PS2_1 PS2_1 PS2_1 PS2_1 PS2_1 PS2_2 PS2_2 PS2_2 PS2_2 PS2_2 PS2_2 PS2_3 PS2_3 PS2_3 PS2_3 PS2_3 PS2_3 LPC LPC LPC LPC Register Abbreviation ICMR_2 SAR_2 ICRES_0 KBCR1_0 KBTR_0 KBCRH_0 KBCRL_0 KBBR_0 KBCR2_0 KBCR1_1 KBTR_1 KBCRH_1 KBCRL_1 KBBR_1 KBCR2_1 KBCR1_2 KBTR_2 KBCRH_2 KBCRL_2 KBBR_2 KBCR2_2 KBCR1_3 KBTR_3 KBCRH_3 KBCRL_3 KBBR_3 KBCR2_3 LADR1H LADR1L LADR2H LADR2L Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FE8F H'FE8F H'FEE6 H'FEC0 H'FEC1 H'FED8 H'FED9 H'FEDA H'FEDB H'FEC2 H'FEC3 H'FEDC H'FEDD H'FEDE H'FEDF H'FEC4 H'FEC5 H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FED2 H'FED3 H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FDC0 H'FDC1 H'FDC2 H'FDC3 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 953 of 994 REJ09B0452-0100 Section 27 List of Registers Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC Register Abbreviation SCIFADRH SCIFADRL LADR4H LADR4L IDR4 ODR4 STR4 HICR4 SIRQCR2 SIRQCR3 TWR0MW TWR0SW TWR1 TWR2 TWR3 TWR4 TWR5 TWR6 TWR7 TWR8 TWR9 TWR10 TWR11 TWR12 TWR13 TWR14 TWR15 IDR3 ODR3 STR3 HICR5 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FDC4 H'FDC5 H'FDD4 H'FDD5 H'FDD6 H'FDD7 H'FDD8 H'FDD9 H'FDDA H'FDDB H'FE20 H'FE20 H'FE21 H'FE22 H'FE23 H'FE24 H'FE25 H'FE26 H'FE27 H'FE28 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE31 H'FE32 H'FE33 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 954 of 994 REJ09B0452-0100 Section 27 List of Registers Module LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC LPC Register Abbreviation LADR3H LADR3L SIRQCR0 SIRQCR1 IDR1 ODR1 STR1 SIRQCR4 IDR2 ODR2 STR2 HISEL HICR0 HICR1 HICR2 HICR3 Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 Address H'FE34 H'FE35 H'FE36 H'FE37 H'FE38 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3D H'FE3E H'FE3F H'FE40 H'FE41 H'FE42 H'FE43 H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC11 H'FC20 H'FC20 H'FC20 H'FC21 H'FC21 H'FC22 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A/D converter ADDRA A/D converter ADDRB A/D converter ADDRC A/D converter ADDRD A/D converter ADDRE A/D converter ADDRF A/D converter ADDRG A/D converter ADDRH A/D converter ADCSR A/D converter ADCR SCIF SCIF SCIF SCIF SCIF SCIF FRBR FTHR FDLL FIER FDLH FIIR Rev. 1.00 Apr. 28, 2008 Page 955 of 994 REJ09B0452-0100 Section 27 List of Registers Module SCIF SCIF SCIF SCIF SCIF SCIF SCIF ROM ROM ROM ROM ROM ROM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Register Abbreviation FFCR FLCR FMCR FLSR FMSR FSCR SCIFCR FCCS FPCS FECS FKEY FMATS FTDAR SYSCR3 MSTPCRA MSTPCRB SBYCR LPWRCR MSTPCRH MSTPCRL STCR SYSCR MDCR Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FC22 H'FC23 H'FC24 H'FC25 H'FC26 H'FC27 H'FC28 H'FEA8 H'FEA9 H'FEAA H'FEAC H'FEAD H'FEAE H'FE7D H'FE7E H'FE7F H'FF84 H'FF85 H'FF86 H'FF87 H'FFC3 H'FFC4 H'FFC5 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access States 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Apr. 28, 2008 Page 956 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 lists the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Power supply voltage* Input voltage (except ports 7, D, A, G, I, PE4, PE2 to PE0, P97, P86, P52, and P42) Symbol Value VCC Vin -0.3 to +4.3 -0.3 to VCC + 0.3 -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC +0.3 or -0.3 to AVCC +0.3 whichever is lower -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +4.3 -0.3 to AVCC + 0.3 -20 to +75 0 to +75 -55 to +125 C Unit V Input voltage (ports A, G, I, PE4, PE2 to PE0, Vin P97, P86, P52, and P42) Input voltage (AN input is not selected for port Vin D) Input voltage (AN input is selected for port D) Input voltage (port 7) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Vin Vin AVref AVCC VAN Topr Operating temperature (when flash memory is Topr programmed or erased) Storage temperature Caution: Note: * Tstg Permanent damage to this LSI may result if absolute maximum ratings are exceeded. Make sure the applied power supply does not exceed 4.3 V. Voltage applied to the VCC pin. The VCL pin should not be applied a voltage. Rev. 1.00 Apr. 28, 2008 Page 957 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.2 DC Characteristics Table 28.2 lists the DC characteristics. Table 28.3 lists the permissible output currents. Table 28.4 lists the bus drive characteristics. Table 28.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V Test Item Schmitt trigger input voltage P67 to P60, IRQ7 to IRQ0, IRQ15 to IRQ8 KIN7 to KIN0, KIN15 to KIN8, WUE15 to WUE8 ExIRQ7 to ExIRQ6, and ExIRQ15 to ExIRQ8 Input high voltage RES, NMI, MD2, MD1, and ETRST EXTAL Port 7 Ports A, G, I, PE4, PE2 to PE0, P97, P86, P52, and P42 Input pins other than (1) and (2) above Input low voltage RES, MD2, MD1, and ETRST (3) NMI, EXTAL, and input pins other than (1) and (3) above Output high voltage All output pins (except for ports A, G, I, P97, P86, P52, and P42) Ports A, G, I, P97, P86, P52, and P42*2 Output low voltage All output pins *3 Ports 1, 2, 3, C, and D VOL 0.4 1.0 IOL = 1.6 mA IOL = 5 mA VOH VCC - 0.5 VCC - 1.0 0.5 IOH = -200 A IOH = -1 mA IOH = - 200 A VIL - 0.3 -0.3 VCC x 0.1 VCC x 0.2 VCC x 0.7 VCC + 0.3 VCC x 0.7 VCC x 0.7 VCC x 0.7 VCC + 0.3 AVCC + 0.3 5.5 (2) VIH VCC x 0.9 VCC + 0.3 VT+ - VT- VCC x 0.05 VT+ VCC x 0.7 (1) Symbol VT - Min. VCC x 0.2 Typ. Max. Unit V Conditions Rev. 1.00 Apr. 28, 2008 Page 958 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V Item Input leakage current RES NMI, MD2, MD1, ETRST PE0 to PE2, and PE4 Port 7 Three-state leakage current (off state) Input pull-up MOS current Input capacitance Ports 1 to 3, P95 to P90, ports 6, B to D, F, H, and J All pins Cin 10 pF Vin = 0 V f = 1 MHz Ta = 25 C Supply current* 4 Symbol Min. | Iin | Typ. Max. 10.0 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V | ITSI | 1.0 1.0 Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V Ports 1 to 6, 8, 9, A to D, PE3, and F to J - Ip 20 150 A Vin = 0 V Normal operation ICC 25 40 mA VCC = 3.0 V to 3.6 V f = 20 MHz, all modules operating, high-speed mode Sleep mode 20 35 VCC = 3.0 V to 3.6 V f = 20 MHz Standby mode 35 1 0.01 1 0.01 0 70 200 2 5 2 5 0.8 20 A Ta 50 C 50 C < Ta Analog power supply current Reference power supply current VCC start voltage VCC rising edge During A/D conversion A/D conversion standby During A/D conversion A/D conversion standby AICC mA A mA A V ms/V AVref = 3.0 V to AVCC AVCC = 3.0 V to 3.6 V AIref VCCSTART SVCC Rev. 1.00 Apr. 28, 2008 Page 959 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range from 3.0 V to 3.6 V to the AVCC and AVref pins by connecting to the power supply (VCC). The relationship between these two pins should be AVref AVCC. 2. Ports A, G, I, P97, P86, P52, P42, and peripheral module outputs multiplexed on the pin are NMOS push-pull outputs. An external pull-up resistor is necessary to provide high-level output from SCL0, SCL1, SDA0, SDA1, SDA2, SCL2, ExSCLA, ExSCLB, ExSDAA, and ExSDAB (ICE bit in ICCR is 1). Ports A, G, I, P97, P86, P52, and P42 (ICE bit in ICCR is 0) high levels are driven by NMOS. An external pull-up resistor is necessary to provide high-level output from these pins when they are used as an output. 3. Indicates values when ICCS = 0, ICE = 0, and KBIOE = 0. Low level output when the bus drive function is selected is rated separately. 4. Current consumption values are for VIH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off state. Table 28.2 DC Characteristics (3) Using LPC Function Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V Item Input high voltage P37 to P30, P82 to P80, PB1, PB0 Input low voltage P37 to P30, P82 to P80, PB1, PB0 Output high voltage P37, P33 to P30, P82 to P80, PB1, PB0 Output low voltage P37, P33 to P30, P82 to P80, PB1, PB0 VOL VCCx0.1 V IOL = 1.5 mA VOH VCC x 0.9 V IOH = - 0.5 mA VIL VCC x 0.3 V Symbol VIH Min. VCC x 0.5 Max. Unit V Test Conditions Rev. 1.00 Apr. 28, 2008 Page 960 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Table 28.2 DC Characteristics (4) Using FSI Function Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V Item Input high voltage Input low voltage Output high voltage Output low voltage PB7 to PB4 Symbol VIH VIL VOH Min. VCC x 0.7 - 0.3 VCC - 0.5 VCC - 0.3 VOL Typ. Max. VCC + 0.3 VCC x 0.2 0.4 Unit V Test Conditions IOH = -200 A IOH = -1 mA IOL = 1.6 mA Input pull-up MOS current Input capacitance - lP Cin 30 300 10 A pF Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25 C Table 28.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VSS = 0V Item Permissible output low SCL0, SDA0, SCL1, SDA1, SCL2, current (per pin) SDA2, ExSCLA, ExSDAA, ExSCLB, ExSDAB, PS2AC to PS2DC, PS2AD to S2DD, and PA7 to PA4 (bus drive function selected) Ports 1, 2, 3, C, and D Other output pins Permissible output low Total of ports 1, 2, 3, C, and D current (total) Total of all output pins, including the above Permissible output high All output pins current (per pin) Permissible output high Total of all output pins current (total) IOL Symbol Min. Typ. Max. Unit IOL 8 mA -IOH - IOH 5 2 40 60 2 30 Notes: 1. To protect LSI reliability, do not exceed the output current values in table 28.3. 2. When driving a Darlington transistor or LED, always insert a current-limiting resistor in the output line, as show in figures 28.1 and 28.2. Rev. 1.00 Apr. 28, 2008 Page 961 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Table 28.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: SCL0, SDA0, SCL1, SDA1, SCL2, SDA2, ExSCLA, ExSDAA, ExSCLB, and ExSDAB (bus drive function selected) Item Schmitt trigger input voltage Symbol Min. VT VT - Typ. Max. VCC x 0.7 5.5 VCC x 0.3 0.5 0.4 10 1.0 Unit V Test Conditions VCC x 0.3 - + VT - VT Input high voltage Input low voltage Output low voltage VI H VIL VOL Cin | ITSI | + VCC x 0.05 VCC x 0.7 -0.5 IOL = 8 mA IOL = 3 mA pF A Vin = 0 V, f = 1 MHz, Ta = 25 C Vin = 0.5 to VCC - 0.5 V Input capacitance Three-state leakage current (off state) Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V Applicable Pins: PS2AC to PS2DC, PS2AD to PS2DD, and PA7 to PA4 (bus drive function selected) Item Output low voltage Symbol Min. VOL Typ. Max. 0.5 0.4 Unit V Test Conditions IOL = 8 mA IOL = 3 mA This LSI 2 k Port Darlington transistor Figure 28.1 Darlington Transistor Drive Circuit (Example) Rev. 1.00 Apr. 28, 2008 Page 962 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics This LSI 600 Ports 1 to 3, C and D LED Figure 28.2 LED Drive Circuit (Example) 28.3 AC Characteristics Figure 28.3 shows the test conditions for the AC characteristics. 3V C = 30pF : All ports RL = 2.4 k RH = 12 k I/O timing test levels * Low level : 0.8 V * High level : 1.5 V RL LSI output pin C RH Figure 28.3 Output Load Circuit Rev. 1.00 Apr. 28, 2008 Page 963 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.3.1 Clock Timing Table 28.5 shows the clock timing. The clock timing specified here covers clock output () and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 25, Clock Pulse Generator. Table 28.5 Clock Timing Condition A: Condition B: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 10 MHz VCC = 3.0 V to 3.6 V, VSS = 0 V, = 10 MHz to 20 MHz Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Reset oscillation stabilization (crystal) Software standby oscillation stabilization time (crystal) Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 Min. 100 30 30 20 8 500 Max. 125 20 20 Condition B Min. 50 20 20 20 8 500 Max. 100 5 5 s ms Figure 28.5 Figure 28.6 Figure 28.5 Unit ns Reference Figure 28.4 External clock output stabilization delay tDEXT time tcyc tCH tCf tCL tCr Figure 28.4 System Clock Timing Rev. 1.00 Apr. 28, 2008 Page 964 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics EXTAL tDEXT VCC tOSC1 RES Figure 28.5 Oscillation Stabilization Timing NMI IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) WUEi ( i = 8 to 15 ) PS2AC to PS2DC tOSC2 Figure 28.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) Rev. 1.00 Apr. 28, 2008 Page 965 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.3.2 Control Signal Timing Table 28.6 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD can be operated based on the subclock ( = 32.768 kHz). Table 28.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz, 8 MHz to maximum operating frequency Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS Min. 200 20 150 10 200 150 Max. Unit ns tcyc ns Figure 28.8 Test Conditions Figure 28.7 Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE8) IRQ hold time (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE8) IRQ pulse width (IRQ15 to IRQ0, KIN15 to KIN0, WUE15 to WUE8) (exiting software standby mode) tIRQH 10 tIRQW 200 tRESS RES tRESW tRESS Figure 28.7 Reset Input Timing Rev. 1.00 Apr. 28, 2008 Page 966 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tNMIS NMI tNMIW tNMIH IRQi (i = 0 to 15) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input tIRQS KINi (i = 0 to 15) WUEi (i = 0 to 15) tIRQH tIRQW Figure 28.8 Interrupt Input Timing Rev. 1.00 Apr. 28, 2008 Page 967 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.3.3 Timing of On-Chip Peripheral Modules Table 28.7 shows the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock ( = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, WUE8 to WUE15, and KBCA to KBCD) and watchdog timer (WDT_1) only. The system clock or LCLK operation can be used in the FSI. Table 28.7 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 32.768 kHz*1, = 8 MHz to maximum operating frequency, FSICK = 8 MHz to maximum operating frequency or LCLK (33 MHz) Symbol Output data delay time*2 Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Single edge Both edges tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tTCMS tTCMCKS tTCMCKW tTDPS tTDPCKS tTDPCKW tPWOD tScyc Min. 30 30 30 30 1.5 2.5 30 30 1.5 2.5 30 30 1.5 30 30 1.5 4 6 tSCKW 0.4 Max. 50 50 50 50 0.6 tScyc tcyc ns tcyc Figure 28.19 Figure 28.20 tcyc ns Figure 28.17 Figure 28.18 ns Figure 28.15 Figure 28.16 tcyc ns Figure 28.12 Figure 28.14 Figure 28.13 tcyc Figure 28.11 ns Figure 28.10 Unit ns Test Conditions Figure 28.9 Item I/O ports Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges TCM TCM input setup time TCM clock input setup time TCM clock pulse width TDP TDP input setup time TDP clock input setup time TDP clock pulse width PWMU, PWMX SCI Pulse output delay time Input clock cycle Asynchronous Synchronous Input clock pulse width Rev. 1.00 Apr. 28, 2008 Page 968 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Test Conditions Figure 28.20 Item SCI Input clock rise time Input clock fall time Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) FSI Clock cycle Clock pulse width (high) Clock pulse width (low) SS signal rise delay time SS signal fall delay time Transmit signal delay time Receive signal setup time Receive signal hold time Symbol tSCKr tSCKf tTXD tRXS tRXH tCYC tCKH tCKL tSSH tSSL tTXD tRXS tRXH Min. 50 50 30 13 13 12 12 5 5 Max. 1.5 1.5 50 12 Unit tcyc ns Figure 28.21 ns Figure 28.22 Notes: 1. Applied only for the peripheral modules that are available during subclock operation. 2. Other than P52, P97, P86, P42, port A, port G, and port I. T1 T2 tPRS Ports 1 to 9 and A to J (read) tPRH tPWD Ports 1 to 6, 8, 9, A to D and F to J (write) Figure 28.9 I/O Port Input/Output Timing Rev. 1.00 Apr. 28, 2008 Page 969 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tTOCD Output compare outputs* tTICS Input capture inputs* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, and TIOCD0 Figure 28.10 TPU Input/Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 28.11 TPU Clock Input Timing tTMOD TMO_0, TMO_1 TMO_X, TMO_Y Figure 28.12 8-Bit Timer Output Timing tTMCS TMI_0, TMI_1 TMI_X, TMI_Y tTMCWL tTMCWH tTMCS Figure 28.13 8-Bit Timer Clock Input Timing Rev. 1.00 Apr. 28, 2008 Page 970 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tTMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 28.14 8-Bit Timer Reset Input Timing tTCMS TCMCYI TCMMCI Figure 28.15 TCM Input Setup Time tTCMCKS TCMCKI tTCMCKW tTCMCKW Figure 28.16 TCM Clock Input Timing tTDPS TDPCYI TDPMCI Figure 28.17 TDP Input Setup Time Rev. 1.00 Apr. 28, 2008 Page 971 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tTDPCKS TDPCKI tTDPCKW tTDPCKW Figure 28.18 TDP Clock Input Timing tPWOD PWMU5A to PWMU0A, PWMU5B to PWMU0B, PWX1, PWX0 Figure 28.19 PWMU, PWMX Output Timing tSCKW SCK1 tScyc tSCKr tSCKf Figure 28.20 SCK Clock Input Timing SCK1 tTXD TxD1 (transmit data) tRXS RxD1 (receive data) tRXH Figure 28.21 SCI Input/Output Timing (Clock Synchronous Mode) Rev. 1.00 Apr. 28, 2008 Page 972 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tCKH FSICK tCKL FSICK tSSL FSISS tCYC tSSH tTXD FSIDO tRXS FSIDI tRXH Figure 28.22 FSI Input/Output Timing Table 28.8 PS2 Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to maximum operating frequency Standard Value Item KCLK, KD output fall time KCLK, KD input data hold time KCLK, KD input data setup time KCLK, KD output delay time KCLK, KD capacitive load Note: * Symbol Min. tKBF tKBIH tKBIS tKBOD Cb 150 150 Typ. Max. 250 450 400 pF Test Unit Conditions Remarks ns Figure 28.23 When KCLK and KD are output, an external pull-up register must be connected, as shown in figure 28.23. Rev. 1.00 Apr. 28, 2008 Page 973 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics (1) Receive tKBIS tKBIH KCLK/KD* (2) Transmit (a) tKBOD KCLK/KD* Transmit (b) KCLK/KD* tKBF Note: * KCLK : PS2AC to PS2DC KD : PS2AD to PS2DD Figure 28.23 PS2 Timing Rev. 1.00 Apr. 28, 2008 Page 974 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Table 28.9 I2C Bus Timing Conditions: Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Note: * VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to maximum operating frequency Symbol Min. tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb 12 3 5 5 3 3 3 0.5 0 Typ. Max. 7.5* 300 1 400 2 Unit tcyc Test Conditions Figure 28.24 ns tcyc ns pF 17.5 tcyc can be set according to the clock selected for use by the I C module. SDA0 to SDA2 ExSDAA ExSDAB VIH VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0 to SCL2 ExSCLA ExSCLB P* S* tSf tSCLL tSCL tSr tSDAH Sr* tSDAS P* Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 28.24 I2C Bus Interface Input/Output Timing Rev. 1.00 Apr. 28, 2008 Page 975 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Table 28.10 LPC Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, = 8 MHz to maximum operating frequency, Ta = -20 to +75C Symbol tLcyc tLCKH tLCKL tTXD tOFF tRXS tRXH Min. 30 11 11 2 7 0 Typ. Max. 11 28 Unit ns Test Conditions Figure 28.25 Item Input clock cycle Input clock pulse width (H) Input clock pulse width (L) Transmit signal delay time Transmit signal floating delay time Receive signal setup time Receive signal hold time tLCKH LCLK tLcyc tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (transmit signal) tRXS LAD3 to LAD0, SERIRQ, CLKRUN, LFRAME (receive signal) tRXH tOFF LAD3 to LAD0, SERIRQ, CLKRUN (transmit signal) Figure 28.25 LPC Interface Timing Rev. 1.00 Apr. 28, 2008 Page 976 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Test voltage: 0.4Vcc 50 pF Figure 28.26 Test Conditions for Tester Table 28.11 JTAG Timing Conditions: Item ETCK clock cycle time ETCK clock high pulse width ETCK clock low pulse width ETCK clock rise time ETCK clock fall time ETRST pulse width Reset hold transition pulse width ETMS setup time ETMS hold time ETDI setup time ETDI hold time ETDO data delay time Note: * When tcyc tTCKcyc VCC = 3.0 V to 3.6 V, VSS = 0 V, = 8 MHz to 20 MHz Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tRSTHW tTMSS tTMSH tTDIS tTDIH tTDOD Min. 50* 20 20 20 3 20 20 20 20 Max. 125* 5 5 20 ns tcyc Figure 28.28 Figure 28.29 Unit ns Test Conditions Figure 28.27 Rev. 1.00 Apr. 28, 2008 Page 977 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics tTCKcyc tTCKH ETCK tTCKL tTCKr tTCKf Figure 28.27 JTAG ETCK Timing ETCK RES tRSTHW ETRST tTRSTW Figure 28.28 Reset Hold Timing ETCK tTMSS ETMS tTDIS ETDI tTDOD ETDO tTDIH tTMSH Figure 28.29 JTAG Input/Output Timing Rev. 1.00 Apr. 28, 2008 Page 978 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.4 A/D Conversion Characteristics Table 28.12 lists the A/D conversion characteristics. Table 28.12 A/D Conversion Characteristics (AN15 to AN0 Input: 134/266-State Conversion) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, = 8 MHz to 20 MHz Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. 10 4.0* 20 5 7.0 7.5 7.5 0.5 8.0 Typ. Max. Unit Bits s pF k LSB Note: The power supply to Avref must either be made simultaneously with or follow the power supply to Avcc. * Value when using the maximum operating frequency of 40 states (ADCLK = 10 MHz). Rev. 1.00 Apr. 28, 2008 Page 979 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.5 Flash Memory Characteristics Table 28.13 lists the flash memory characteristics. Table 28.13 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS = 0 V Ta = 0C to +75C (operating temperature range for programming/erasing) Symbol Min. 124 Item Programming time* * * Erase time* * * 124 Typ. 1 40 300 600 1.4 1.4 2.9 3 Max. 10 130 800 1500 4 4 8 Unit ms/128 bytes ms/4-Kbyte block ms/32-Kbyte block ms/64-Kbyte block s/160 Kbytes s/160 Kbytes s/160 Kbytes Times Years Test Conditions tP tE Programming time (total)* * * Erase time (total)* * * 124 124 tP tE tPE NWEC tDRP 100* 10 Ta = 25 C Ta = 25 C Ta = 25 C Programming and Erase time 124 (total)* * * Reprogramming count Data retention time* 4 1000 Notes: 1. Programming and erase time depends on the data. 2. Programming and erase time do not include data transfer time. 3 This value indicates the minimum number of which the flash memory are reprogrammed with all characteristics guaranteed. (The guaranteed value ranges from 1 to the minimum number.) 4. This value indicates the characteristics while the flash memory is reprogrammed within the specified range (including the minimum number). Rev. 1.00 Apr. 28, 2008 Page 980 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics 28.6 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin, and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 28.30. Vcc power supply Bypass capacitor 10 F 0.01 F External capacitor for internal step-down power stabilization VCC One 0.1 F / 0.47 F or two in parallel VCL VSS VSS It is recommended that a bypass capacitor be connected to the VCC pin. (The values are reference values.) When connecting, place a bypass capacitor near the pin. Do not connect Vcc power supply to the VCL pin. Always connect a capacitor for internal step-down power stabilization. Use one or two ceramic multilayer capacitor(s) (0.1 F / 0.47 F: connect in parallel when using two) and place it (them) near the pin. Figure 28.30 Connection of VCC and VCL Capacitors Rev. 1.00 Apr. 28, 2008 Page 981 of 994 REJ09B0452-0100 Section 28 Electrical Characteristics Rev. 1.00 Apr. 28, 2008 Page 982 of 994 REJ09B0452-0100 Appendix Appendix A. I/O Port States in Each Pin State I/O Port States in Each Pin State Reset T T T T T T Software Standby Mode keep keep keep keep keep keep T keep keep [DDR = 1]H [DDR = 0]T T keep keep T keep keep Watch Mode keep keep keep keep keep keep T keep keep EXCL input/ keep Sleep Mode keep keep keep keep keep keep T keep keep [DDR = 1] Clock output [DDR = 0]T keep keep ExEXCL input/T keep keep keep keep T keep keep Program Execution State I/O port I/O port I/O port I/O port I/O port I/O port Input port I/O port I/O port Clock output/ EXCL input/ Input port I/O port I/O port ExEXCL input/ input port I/O port I/O port Table A.1 Port Name Pin Name Port 1 Port 2 Port 3 Port 4 Ports 52 to 50 Port 6 Ports 7 and E4 to T E1 Port 8 Port 97 Port 96 , EXCL Ports 95 to 90 T T T Ports A to D, T F, G, and H5 to H0 Port E0 Port I Port J T T T [Legend] H: High level L: Low level T: High impedance keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up MOS remains on). Output ports maintain their previous state. Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port function determined by DDR and DR. DDR: Data direction register Rev. 1.00 Apr. 28, 2008 Page 983 of 994 REJ09B0452-0100 Appendix B. Product Lineup Type Code R4F2117R Mark Code F2117RTE20V F2117RBG20V F2117RLP20V Package (Code) PTQP0144LC-A (TFP-144V) PLBG0176GA-A (BP-176V) PTLG0145JB-A (TLP-145V) Product Type H8S/2117R Flash memory version Rev. 1.00 Apr. 28, 2008 Page 984 of 994 REJ09B0452-0100 C. JEITA Package Code P-TQFP144-16x16-0.40 RENESAS Code PTQP0144LC-A Previous Code TFP-144/TFP-144V MASS[Typ.] 0.6g HD *1 D 108 72 73 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Package Dimensions 109 bp E HE b1 *2 c1 144 36 37 ZE c Terminal cross section Index mark Reference Symbol Dimension in Millimeters Min D E A2 Nom 16 16 1.00 HD 17.8 18.0 18.2 Max 1 ZD F A A2 HE c 17.8 A 18.0 18.2 1.20 *3 A1 A1 0.05 L L1 bp b1 0.13 0.10 0.18 0.16 0.15 0.23 Figure C.1 Package Dimensions (TFP-144V) y bp x M e Detail F c c1 0.12 0.17 0.15 0.22 e x y ZD ZE L L1 0 0.4 8 0.07 0.08 1.0 1.0 0.4 0.5 1.0 0.6 Appendix Rev. 1.00 Apr. 28, 2008 Page 985 of 994 REJ09B0452-0100 Appendix JEITA Package Code P-LFBGA176-13x13-0.80 RENESAS Code PLBG0176GA-A D wSA wSB Previous Code BP-176/BP-176V MASS[Typ.] 0.45g x4 v y1 S A S y S e A e ZD Reference Dimension in Millimeters Symbol Min Nom Max R P N M L K J H G F E D A1 E D E B v w A A1 e b ZE 13.0 13.0 0.15 0.20 1.40 0.35 0.45 0.40 0.80 0.50 0.45 0.55 0.08 0.10 0.2 C B A x y y1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SD SE ZD ZE 0.90 0.90 b x M S A B Figure C.2 Package Dimensions (BP-176V) Rev. 1.00 Apr. 28, 2008 Page 986 of 994 REJ09B0452-0100 Appendix JEITA Package Code P-TFLGA145-9x9-0.65 RENESAS Code PTLG0145JB-A Previous Code MASS[Typ.] 0.15g wSA D wSB x4 v y1 S S A yS e A ZD N M L K J H G F E D ZE Reference Symbol e E Dimension in Millimeters B Min Nom 9.0 9.0 Max D E v w A A1 e 1 2 3 4 5 6 7 b 8 9 10 11 12 13 xn S A B 0.15 0.20 1.2 C B A 0.65 0.30 0.35 0.40 0.08 0.1 0.20 b x y y1 SD SE ZD ZE 0.6 0.6 Figure C.3 Package Dimensions (TLP-145V) Rev. 1.00 Apr. 28, 2008 Page 987 of 994 REJ09B0452-0100 Appendix D. Treatment of Unused Pins The treatments of unused pins are listed in table D.1. Table D.1 Pin Name RES ETRST MD2, MD1 NMI EXTAL XTAL Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 Port A Port B Port C Port D Port F Port G Port H Port I Port J Port 7 Port E * * Connect each pin to AVCC via a pull-up resistor or to AVSS via a pull-down resistor Connect each pin to VCC via a pull-up resistor Treatment of Unused Pins Example of Pin Treatment (Always used as a reset pin) (Always used as a reset pin) (Always used as mode pins) * Connect to VCC via a pull-up resistor (Always used as a clock pin) (Always used as a clock pin) * Connect each pin to VCC via a pull-up resistor or to VSS via a pull-down resistor Rev. 1.00 Apr. 28, 2008 Page 988 of 994 REJ09B0452-0100 Index Numerics 14-bit PWM timer (PWMX)................... 219 16-bit count mode................................... 380 16-bit cycle measurement timer (TCM)..................................................... 305 16-bit timer pulse unit............................. 237 8-bit timer (TMR) ................................... 355 C Cascaded connection............................... 380 Clock pulse generator ............................. 833 Clocked synchronous mode .................... 441 CMIA ...................................................... 384 CMIB ...................................................... 384 Communications protocol ....................... 804 Compare-match count mode ................... 380 Condition field .......................................... 56 Condition-code register (CCR) ................. 40 Conversion cycle..................................... 229 Conversion time ...................................... 737 CPU operating modes ............................... 32 Crystal resonator ..................................... 834 Cycle measurement mode ....................... 319 A A/D converter ......................................... 727 A/D converter activation......................... 289 Absolute address....................................... 58 Address map ............................................. 74 Address space ........................................... 36 Addressing modes..................................... 57 ADI ......................................................... 739 Advanced mode ........................................ 34 Arithmetic operations instructions............ 48 Asynchronous mode ............................... 424 D Data transfer instructions .......................... 47 Download pass/fail result parameter....... 767 B Base cycle ............................................... 229 Bcc...................................................... 45, 53 Bit manipulation instructions.................... 51 Bit rate .................................................... 419 Block sata transfer instructions................. 55 Block structure........................................ 753 Boot mode ...................................... 750, 776 Branch instructions ................................... 53 Buffer operation...................................... 275 Bus controller (BSC) .............................. 133 E Effective address................................. 57, 61 Effective address extension....................... 56 ERI1........................................................ 460 Error protection....................................... 799 Exception handling ................................... 75 Exception handling vector table.......... 76, 78 Extended control register (EXR)............... 39 Extended vector mode............................. 107 External clock ......................................... 835 Rev. 1.00 Apr. 28, 2008 Page 989 of 994 REJ09B0452-0100 F Flash erase block select parameter ......... 775 Flash memory ................................. 329, 749 Flash multipurpose address area parameter ................................................ 774 Flash multipurpose data destination parameter ................................................ 774 Flash pass and fail parameter.................. 768 Flash program/erase frequency parameter ................................................ 773 FOVI....................................................... 350 Framing error.......................................... 431 interrupt mask level .................................. 39 Interval timer mode................................. 399 K Keyboard buffer control unit (PS2) ........ 587 L Logic operations instructions.................... 50 LPC interface (LPC) ............................... 615 LPC interface clock start request ............ 673 LSI internal states in each operating mode ............................... 849 G General registers ....................................... 38 M H H8S/2140B group compatible vector mode ............................................ 101 Hardware protection ............................... 798 Memory indirect ....................................... 60 Mode transition diagram ......................... 848 Module stop mode .................................. 854 Multiply-accumulate register (MAC) ....... 41 Multiprocessor communication function ................................................... 435 I I2C bus data format ................................. 560 I2C bus interface (IIC) ............................ 529 ICIA........................................................ 350 ICIX........................................................ 384 IICI ......................................................... 581 Immediate ................................................. 59 Input capture operation........................... 382 Instruction set ........................................... 45 Interface.................................................. 403 Internal block diagram................................ 8 Interrupt controller.................................... 85 Interrupt exception handling..................... 81 interrupt exception handling vector table ............................................. 108 Interrupt mask bit ..................................... 40 Rev. 1.00 Apr. 28, 2008 Page 990 of 994 REJ09B0452-0100 N Noise canceler......................................... 579 Normal mode ............................................ 32 O OCIA....................................................... 350 OCIB....................................................... 350 On-board programming .......................... 776 On-board programming mode................. 776 Operation field .......................................... 56 Output buffer control .............................. 154 Overflow ................................................. 398 Overrun error .......................................... 431 OVI ......................................................... 384 P Parity error.............................................. 431 Pin arrangement in each operating mode ......................................... 12 Pin assignments .......................................... 9 Pin functions ............................................. 19 Power-down modes ................................ 841 Program counter (PC) ............................... 39 program-counter relative .......................... 59 Programmer mode .......................... 750, 802 Programming/erasing interface............... 754 Programming/erasing interface parameters............................................... 765 Programming/erasing interface register .................................................... 759 Protection................................................ 798 PWM modes ........................................... 279 R RAM ....................................................... 747 Register direct........................................... 57 Register field............................................. 56 Register indirect........................................ 57 Register indirect with displacement.......... 58 Register indirect with post-Increment....... 58 Register indirect with pre-decrement........ 58 Registers ABRKCR.............................................. 91 ADCR ................................................. 734 ADCSR............................................... 732 ADDR................................................. 731 BAR...................................................... 92 BCR .................................................... 133 BRR .................................................... 419 DACNT .............................................. 221 DACR ................................................. 224 DADR ................................................. 222 DPFR .................................................. 767 FCCS................................................... 759 FDLH .................................................. 498 FDLL .................................................. 498 FEBS................................................... 775 FECS................................................... 761 FFCR................................................... 502 FIER.................................................... 499 FIIR..................................................... 500 FKEY .................................................. 762 FLCR .................................................. 503 FLSR................................................... 506 FMATS ............................................... 763 FMCR ................................................. 504 FMPAR............................................... 774 FMPDR............................................... 774 FMSR.................................................. 510 FPCS ................................................... 761 FPEFEQ .............................................. 773 FPFR ................................................... 768 FRBR .................................................. 497 FRSR................................................... 497 FSCR................................................... 511 FTDAR ............................................... 764 FTHR .................................................. 498 FTSR................................................... 498 HICR................................................... 620 HISEL ................................................. 659 ICCR ................................................... 543 ICDR................................................... 536 ICMR .................................................. 540 ICR........................................................ 90 ICRES ................................................. 555 ICSR.................................................... 551 ICXR................................................... 556 IDR ..................................................... 637 IER........................................................ 96 ISCR...................................................... 93 ISR ........................................................ 97 Rev. 1.00 Apr. 28, 2008 Page 991 of 994 REJ09B0452-0100 ISSR.................................................... 103 KBBR ................................................. 598 KBCR1 ............................................... 591 KBCR2 ............................................... 593 KBCRH .............................................. 594 KBCRL............................................... 596 KBTR ................................................. 598 LADR ................................................. 634 LPWRCR............................................ 844 MDCR .................................................. 68 MSTPCR ............................................ 845 ODR.................................................... 637 PTCNT0 ............................................. 194 PTCNT2 ............................................. 196 RDR.................................................... 407 RSR .................................................... 407 SAR .................................................... 537 SARX ................................................. 538 SBYCR............................................... 842 SCIFCR .............................................. 512 SCMR................................................. 418 SCR .................................................... 411 SIRQCR.............................................. 645 SMR.................................................... 408 SSR..................................................... 414 STCR .................................................... 71 STR..................................................... 638 SYSCR ................................................. 69 SYSCR3 ............................................... 73 TCMCNT ........................................... 309 TCMCR .............................................. 313 TCMCSR............................................ 311 TCMICR............................................. 310 TCMICRF........................................... 310 TCMIER ............................................. 315 TCMMINCM ..................................... 310 TCMMLCM ....................................... 309 TCNT.................................. 263, 360, 394 TCONRI ............................................. 373 TCONRS ............................................ 373 Rev. 1.00 Apr. 28, 2008 Page 992 of 994 REJ09B0452-0100 TCOR.................................................. 361 TCR............................................. 243, 362 TCSR .................................................. 367 TDPCNT............................................. 333 TDPCR1 ............................................. 338 TDPCR2 ............................................. 340 TDPCSR ............................................. 335 TDPICR .............................................. 335 TDPICRF............................................ 335 TDPIER .............................................. 341 TDPPDMN ......................................... 334 TDPPDMX ......................................... 334 TDPWDMN........................................ 334 TDPWDMX........................................ 333 TDR .................................................... 407 TGR .................................................... 263 TICRF ................................................. 372 TICRR................................................. 372 TIOR ................................................... 249 TMDR................................................. 247 TSR ..................................................... 260 TSTR................................................... 263 TSYR .................................................. 264 TWR ................................................... 638 WER ................................................... 104 WSCR ................................................. 134 WUESCR............................................ 104 WUESR .............................................. 104 Reset ......................................................... 79 Reset exception handling .......................... 79 RXI1 ....................................................... 460 S Scan mode............................................... 736 Serial communication interface (SCI)..... 403 Serial communication interface with FIFO (SCIF)............................................ 493 Serial data reception........................ 431, 445 Serial data transmission .................. 429, 443 Serial formats.......................................... 560 Shift instructions....................................... 50 Single mode ............................................ 735 Sleep mode ............................................. 851 Smart card............................................... 403 Smart card interface................................ 449 Software protection................................. 799 Software standby mode........................... 851 Stack pointer (SP)..................................... 38 Stack status ............................................... 83 Standard serial communication interface specifications for boot mode................... 802 Synchronous operation ........................... 273 System control instructions....................... 54 TGI2A..................................................... 288 TGI2B ..................................................... 288 Toggle output.......................................... 270 Trace bit .................................................... 39 Trap instruction exception handling.......... 81 TRAPA instruction ............................. 59, 81 TXI1........................................................ 460 U USB 2.0 host/function module (USB) .... 469 User boot MAT ....................................... 801 User boot mode ....................................... 789 User MAT ............................................... 801 User program mode......................... 750, 780 T TCI0V..................................................... 288 TCI1U..................................................... 288 TCI1V..................................................... 288 TCI2U..................................................... 288 TCI2V..................................................... 288 TEI1........................................................ 460 TGI0A..................................................... 288 TGI0B..................................................... 288 TGI0C..................................................... 288 TGI0D..................................................... 288 TGI1A..................................................... 288 TGI1B..................................................... 288 V Vector address switching ........................ 130 W Watch mode ............................................ 853 Watchdog timer (WDT) .......................... 391 Watchdog timer mode............................. 398 Waveform output by compare match...... 269 WOVI...................................................... 400 Rev. 1.00 Apr. 28, 2008 Page 993 of 994 REJ09B0452-0100 Rev. 1.00 Apr. 28, 2008 Page 994 of 994 REJ09B0452-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2117R Group Publication Date: Rev.1.00, Apr. 28, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 H8S/2117R Group Hardware Manual |
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